TI TPS65185RSLR

TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
www.ti.com
®
PMIC FOR E Ink Vizplex™ ENABLED ELECTRONIC PAPER
DISPLAY
Check for Samples: TPS65185
FEATURES
1
• Single Chip Power Management Solution for
E Ink® Vizplex™ Electronic Paper Displays
• Generates Positive and Negative Gate and
Source Driver Voltages and Back-Plane Bias
from a Single, Low-Voltage Input Supply
• Supports 9.7 Inch and Larger Panel Size
• 3-V to 6-V Input Voltage Range
• Boost Converter for Positive Rail Base
• Inverting Buck-Boost Converter for Negative
Rail Base
• Two Adjustable LDOs for Source Driver
Supply
– LDO1: 15 V, 120 mA (VPOS)
– LDO2: –15 V, 120 mA (VNEG)
• Accurate Output Voltage Tracking
– VPOS - VNEG = ±50 mV
• Two Charge Pumps for Gate Driver Supply
– CP1: 22 V, 10 mA (VDDH)
– CP2: –20 V, 12 mA, (VEE)
• Adjustable VCOM Driver for Accurate
Panel-Backplane Biasing
– User Programmable Default
– 0 V to -5.11 V
– ± 1.5% accuracy (±10 mV)
– 9-Bit Control (10-mV Nominal Step Size)
2345
•
•
•
•
•
•
Active Discharge on All Rails
Flexible Power-Up and Power Down
Sequencing
Integrated 10-Ω, 3.3-V Power Switch for
Disabling System Power Rail to E-Ink Panel
Thermistor Monitoring
– –10°C to 85°C Temperature Range
– ±1°C Accuracy from 0°C to 50°C
I2C Serial Interface
– Slave Address 0x68h
Package Options:
– 48-Pin, 0.5 mm Pitch,
7 mm x 7 mm x 0.9 mm (QFN) RGZ
– 48-Pin, 0.4 mm Pitch,
6 mm x 6 mm x 0.9 mm (QFN) RSL
APPLICATIONS
•
•
•
•
•
•
Power Supply for Active Matrix E Ink®
Vizplex™ Panels
EPD Power Supply
E-Book Readers
EPSON® S1D13522 (ISIS) Timing Controller
EPSON® S1D13521 (Broadsheet) Timing
Controller
Application Processors With Integrated or
Software Timing Controller ( OMAP™)
DESCRIPTION
The TPS65185 is a single-chip power supply designed to for E Ink® Vizplex™ displays used in portable e-reader
applications and supports panel sizes up to 9.7 inches and greater. Two high efficiency DC/DC boost converters
generate ±16-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver
supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to
120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific panel
requirements.
Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to -5.11 V with 9-bit
control through the serial interface and can source or sink current depending on panel condition. The TPS65185
supports automatic panel kickback voltage measurement which eliminates the need of manual VCOM calibration
in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM
power-up default value.
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP is a trademark of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
TPS65185 is available in two packages, a 48-pin 7x7 mm2 QFN with 0.5-mm pitch and a 48-pin 6x6 mm2 QFN
with 0.4-mm pitch.
FUNCTIONAL BLOCK DIAGRAM
10uF
10uF
2.2uH
VIN_P
VB_SW
From Battery
(3 .0 V-6 .0V)
4.7uF
DCDC 1
PGND 1
From Battery
(3.0V-6.0V)
4.7uH
VN_SW
DCDC 2
VN
VB
VDDH_IN
4. 7uF
VEE_IN
100n
100n
VDDH_D
VDDH (22V)
1M
2.2uF
10nF
VDDH
CHARGE
PUMP
VDDH_DRV
VDDH_FB
VDDH_ DIS
47.5k
VEE_D
VEE
CHARGE
PUMP
1k
1k
PGND2
4.7uF
VPOS
VPOS_ DIS
4.7uF
VEE_EN
PGND 2
PGND2
VPOS_IN
PGND2
LDO1
AGND 2
43k
PGND2
ADC
TMST_VALUE[7:0]
VIN
From Input Supply
(3 .0 V-6.0V)
4. 7uF
VNEG
(-15V)
VNEG_DIS
4.7uF
VNEG_EN
TS
TEMP
SENSOR
52. 3k
VNEG
1k
PGND2
10k NTC
2.2uF
VNEG_IN
LDO2
1k
VPOS_EN
VEE_DIS
VEE
(-20V)
1M
10nF
PGND2
VDDH_EN
VPOS (15V)
VEE_DRV
VEE_FB
PBKG
PowerPad®
INT _LDO
INT_LDO
4. 7uF
VREF
10uF
VREF
4.7uF
AGND 1
4. 7uF
VCOM
To panel back-plane
(0 to -5.11 V)
VCOM _CTRL
From uC
DAC
VCOM[8:0]
4. 7uF
VCOM _PWR
VCOM_ DIS
1k
VIN3P3
V3P3_EN
GATE DRIVER
3 .3V supply from system
V3P3
To EPD panel
1k
VIO 10k
VIO 10k
SDA
SCL
From uC
From/to uC or DSP
From uC
From uC
2
PWRUP
WAKEUP
DGND
DIGITAL
CORE
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INT
PWR_GOOD
10k VIO
10k VIO
To uC
To uC
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS65185
TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
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ORDERING INFORMATION (1)
TA
-10°C to 85°C
(1)
(2)
PACKAGE (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
RGZ
TPS65185RGZR
TPS65185
RSL
TPS65185RSLR
TPS65185
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVICE INFORMATION
25 – VN_SW
26 – VN
27 – VEE_IN
28 – VEE_DRV
29 – VEE_DIS
30 – VEE_D
31 – VEE_FB
32 – PGND2
33 – VDDH_FB
34 – VDDH_D
36 – VDDH_DRV
35 – VDDH_DIS
RGZ OR RSL PACKAGE
(TOP VIEW)
VDDH_IN – 37
24 – VIN_P
N/C – 38
23 – PWR_GOOD
N/C – 39
22 – PBKG
VB_SW – 40
21 – PWRUP
PGND1 – 41
20 – N/C
VB – 42
19 – VPOS_DIS
VPOS_IN – 43
18 – SDA
VPOS – 44
VIN3P3 – 45
17 – SCL
16 – VCOM_PWR
V3P3 – 46
15 – VCOM
TS – 47
14 – VCOM_DIS
VCOM_CTRL – 12
N/C – 11
VIN – 10
VNEG_DIS – 9
AGND1 – 8
INT_LDO – 7
DGND – 6
WAKEUP – 5
VNEG – 3
VNEG_IN – 4
nINT – 2
13 – N/C
VREF – 1
AGND2 – 48
TERMINAL FUNCTIONS (3)
TERMINAL
(3)
I/O
DESCRIPTION
NAME
NO.
VREF
1
O
Filter pin for 2.25-V internal reference to ADC
INT
2
O
Open drain interrupt pin (active low)
VNEG
3
O
Negative supply output pin for panel source drivers
VNEG_IN
4
I
Input pin for LDO2 (VNEG)
WAKEUP
5
I
Wake up pin (active high). Pull this pin high to wake up from sleep mode. IC accepts I2C
commands after WAKEUP pin is pulled high but power rails remain disabled until
PWRUP pin is pulled high.
DGND
6
INT_LDO
7
Digital ground. Connect to ground plane.
O
Filter pin for 2.7-V internal supply
There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively.
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TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
TERMINAL
4
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I/O
DESCRIPTION
NAME
NO.
AGND1
8
VNEG_DIS
9
O
Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the
rail is disabled. Leave floating if discharge function is not desired.
VIN
10
I
Input power supply to general circuitry
N/C
11
VCOM_CTRL
12
N/C
13
VCOM_DIS
14
I
Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever
VCOM is disabled. Leave floating if discharge function is not desired.
VCOM
15
O
Filter pin for panel common-voltage driver
VCOM_PWR
16
I
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
SCL
17
I
Serial interface (I2C) clock input
SDA
18
I/O
VPOS_DIS
19
I
N/C
20
PWRUP
21
PBKG
22
PWR_GOOD
23
Analog ground for general analog circuitry
Not internally connected
I
VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low
and VN is enabled, VCOM discharge is enabled.
Not internally connected
Serial interface (I2C) data input/output
Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge
VPOS to ground whenever the rail is disabled. Leave floating if discharge function is not
desired.
Not internally connected
I
Power-up pin. Pull this pin high to power-up all output rails.
Die substrate. Connect to VN (-16 V) with short, wide trace. Wide copper trace will
improve heat dissipation.
O
Open drain power good output pin. Pin is pulled low when one or more rails are disabled
or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.
VIN_P
24
I
Input power supply to inverting buck-boost converter (DCDC2)
VN_SW
25
O
Inverting buck-boost converter switch out (DCDC2)
VN
26
I
Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and
VEE charge pump
VEE_IN
27
I
Input supply pin for negative charge pump (CP2) (VEE)
VEE_DRV
28
O
Driver output pin for negative charge pump (CP2)
VEE_DIS
29
I
Discharge pin for VEE. Connect a resistor from VEE _DIS to VEE to discharge VEE to
ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VEE_D
30
O
Base voltage output pin for negative charge pump (CP2)
VEE_FB
31
I
Feedback pin for negative charge pump (CP2)
PGND2
32
VDDH_FB
33
I
Feedback pin for positive charge pump (CP1)
VDDH_D
34
O
Base voltage output pin for positive charge pump (CP1)
VDDH_DIS
35
I
Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the
rail is disabled. Leave floating if discharge function is not desired.
VDDH_DRV
36
O
Driver output pin for positive charge pump (CP1)
VDDH_IN
37
I
Input supply pin for positive charge pump (CP1)
N/C
38
Not internally connected
N/C
39
Not internally connected
VB_SW
40
PGND1
41
VB
42
VPOS_IN
VPOS
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
O
Boost converter switch out (DCDC1)
Power ground for DCDC1
I
Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge
pump
43
I
Input pin for LDO1 (VPOS)
44
O
Positive supply output pin for panel source drivers
VIN3P3
45
I
Input pin to 3.3-V power switch
V3P3
46
O
Output pin of 3.3-V power switch
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TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
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TERMINAL
I/O
DESCRIPTION
NAME
NO.
TS
47
AGND2
48
Reference point to external thermistor and linearization resistor
PowerPad
N/A
Power Pad, internally connected to PBKG. Connect to VN with short, wide trace. Wide
copper trace will improve heat dissipation. PowerPad must not be connected to ground.
I
Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor
between this pin and AGND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
(2)
VALUE
UNIT
–0.3 to 7
V
Ground pins to system ground
–0.3 to 0.3
V
Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB,
PWR_GOOD, nINT
–0.3 to 3.6
V
Voltage on VB, VB_SW, VPOS_IN, VPOS_DIS, VDDH_IN
–0.3 to 20
V
VDDH_DIS
–0.3 to 30
V
Voltage on VN, VEE_IN, VCOM_PWR, VNEG_DIS, VNEG_IN
–20 to 0.3
V
Voltage from VIN_P to VN_SW
–0.3 to 30
V
Voltage on VCOM_DIS
–5 to 0.3
V
VEE_DIS
–30 to 0.3
V
Internally limited
mA
Input voltage range at VIN , VIN_P, VIN3P3
Peak output current
Continuous total power dissipation
2
W
θJA
Junction-to-ambient thermal resistance (3)
23
°C/W
TJ
Operating junction temperature
-10 to 125
°C
-10 to 85
°C
-65 to 150
°C
TA
Operating ambient temperature
Tstg
Storage temperature
(4)
ESD rating
(1)
(2)
(3)
(4)
(HBM) Human body model
±2000
(CDM) Charged device model
±500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and
2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application.
It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad
is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the
buck-boost output will help heat dissipated efficiently.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage range at VIN, VIN_P, VIN3P3
3
3.7
6
V
Voltage range at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL,
VDDH_FB, VEE_FB, PWR_GOOD, nINT
0
3.6
V
TA
Operating ambient temperature range
–10
85
°C
TJ
Operating junction temperature range
–10
125
°C
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TPS65185
SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
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RECOMMENDED EXTERNAL COMPONENTS
PART NUMBER
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
4.7 µH
4 mm x 4 mm x 1.65 mm
Murata
NR4018T4R7M
4.7 µH
4 mm x 4 mm x 1.8 mm
Taiyo Yuden
VLS252015ET-2R2M
2.2 µH
2 mm x 2.5 mm x 1.5 mm
TDK
NR4012T2R2M
2.2 µH
4 mm x 4 mm x 1.2 mm
Taiyo Yuden
GRM21BC81E475KA12L
4.7 µF, 25 V, X6S
805
Murata
GRM32ER71H475KA88L
4.7 µF, 50 V, X7R
1210
Murata
BAS3010
SOD-323
Infineon
MBR130T1
SOD-123
ON-Semi
SOT-23
Fairchild
603
Murata
INDUCTORS
CAPACITORS
All other caps
X5R or better
DIODES
BAV99
THERMISTOR
NCP18XH103F03RB
10 KΩ
ELECTRICAL CHARACTERISTICS
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.7
6
UNIT
INPUT VOLTAGE
VIN
Input voltage range
VUVLO
Undervoltage lockout threshold
VIN falling
2.9
V
V
VHYS
Undervoltage lockout hysteresis
VIN rising
400
mV
INPUT CURRENT
IQ
Operating quiescent current into VIN
Device switching, no load
5.5
mA
ISTD
Operating quiescent current into VIN
Device in standby mode
130
µA
ISLEEP
Shutdown current
Device in sleep mode
3.5
10
µA
INTERNAL SUPPLIES
VINT_LDO
Internal supply
CINT_LDO
Nominal output capacitor
VREF
Internal supply
CREF
Nominal output capacitor
Capacitor tolerance ±10%
Capacitor tolerance ±10%
1
2.7
V
4.7
µF
2.25
V
3.3
4.7
µF
3
3.7
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
Input voltage range
PG
90
%
Power good time-out
Not tested in production
50
ms
Output current
RDS(ON)
MOSFET on resistance
VIN = 3.7 V
LDCDC1
Inductor
CDCDC1
Nominal output capacitor
ESR
Output capacitor ESR
V
4.5
%
250
mA
350
mΩ
1.5 (1)
Switch current accuracy
Switching frequency
6
-4.5
Switch current limit
fSW
(1)
16
DC set tolerance
IOUT
ILIMIT
V
Fraction of nominal output voltage
Output voltage range
VOUT
6
Power good threshold
-30
1
2.2
Capacitor tolerance ±10%
1
A
30
%
MHz
µH
2x4.7
µF
20
mΩ
Contact factory for 1-A, 2-A, or 2.5-A option.
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SLVSAQ8B – FEBRUARY 2011 – REVISED OCTOBER 2011
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.7
6
UNIT
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
Input voltage range
PG
VOUT
Fraction of nominal output voltage
90
%
Power good time-out
Not tested in production
50
ms
Output voltage range
-16
DC set tolerance
IOUT
Output current
RDS(ON)
MOSFET on resistance
ILIMIT
V
Power good threshold
-4.5
VIN = 3.7 V
Switch current accuracy
Inductor
CDCDC1
Nominal output capacitor
ESR
Capacitor ESR
%
250
mA
350
mΩ
1.5 (2)
Switch current limit
LDCDC1
V
4.5
-30
A
30
µH
4.7
Capacitor tolerance ±10%
1
%
3x4.7
µF
20
mΩ
LDO1 (VPOS)
VPOS_IN
PG
Input voltage range
16.8
V
90
%
Power good time-out
Not tested in production
50
ms
Output voltage set value
VINTERVAL
Output voltage set resolution
VOUTTOL
Output tolerance
VDROPOUT
Dropout voltage
VLOADREG
Load regulation – DC
ILOAD
Load current range
ILIMIT
Output current limit
CLDO1
16
Fraction of nominal output voltage
VSET
RDIS
15.2
Power good threshold
Discharge impedance to ground
VIN = 16 V,
VSET[2:0] = 0x3h to 0x6h
VIN = 16 V
VSET = 15 V, ILOAD = 20 mA
15
250
-1
ILOAD = 120 mA
250
1
120
120
Enabled when rail is disabled
800
%
mV
%
mA
mA
1000
-2
Capacitor tolerance ±10%
V
mV
1
ILOAD = 10% to 90%
Mismatch to any other RDIS
Nominal output capacitor
14.25
1
4.7
15.2
16
1200
Ω
2
%
µF
LDO2 (VNEG)
VNEG_IN
PG
Input voltage range
90
%
Power good time-out
Not tested in production
50
ms
VIN = –16 V
VSET[2:0] = 0x3h to 0x6h
Output voltage set value
VINTERVAL
Output voltage set resolution
VOUTTOL
Output tolerance
VSET = –15 V, ILOAD = –20 mA
VDROPOUT
Dropout voltage
ILOAD = 120 mA
VLOADREG
Load regulation – DC
ILOAD
Load current range
ILIMIT
Output current limit
Discharge impedance to ground
Soft start time
CLDO2
Nominal output capacitor
-15
VIN = –16 V
-14.25
250
-1
250
1
120
180
Enabled when rail is disabled
800
Capacitor tolerance ±10%
1
%
mV
%
mA
mA
1000
-2
Not tested in production
V
mV
1
ILOAD = 10% to 90%
Mismatch to any other RDIS
TSS
(2)
V
Fraction of nominal output voltage
VSET
RDIS
16.8
Power good threshold
1200
2
Ω
%
1
ms
4.7
µF
Contact factory for 1-A, 2-A, or 2.5-A option.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
-50
TYP
MAX
UNIT
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF
Difference between VPOS and VNEG
50
mV
VCOM DRIVER
IVCOM
Drive current
Allowed operating range
Accuracy
VCOM
15
-5.5
1
VCOM[8:0] = 0x07Dh
(-1.25 V), VIN = 3.4 V to 4.2 V, no load
-0.8
0.8
VCOM[8:0] = 0x07Dh
(-1.25 V), VIN = 3.0 V to 6.0 V, no load
-1.5
1.5
Output voltage range
Resolution
Max number of EEPROM writes
RIN
Input impedance, HiZ state
Discharge impedance to ground
RDIS
Nominal output capacitor
-5.11
0
10
VCOM calibration
V
mV
100
HiZ = 1
150
VCOM_CTRL = low, HiZ = 0
800
MΩ
1000
-2
Capacitor tolerance ±10%
V
%
1LSB
Mismatch to any other RDIS
CVCOM
mA
Outside this range VCOM is shut down
and VCOMF interrupt is set
3.3
4.7
15.2
16
1200
Ω
2
%
µF
CP1 (VDDH) CHARGE PUMP
VDDH_IN
PG
Input voltage range
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
Feedback voltage
VFB
Accuracy
VDDH_OUT
Output voltage range
ILOAD
Load current range
fSW
Switching frequency
Discharge impedance to ground
RDIS
ILOAD = 2 mA
-2
VSET = 22 V, ILOAD = 2 mA
21
Driver capacitor
CO
Output capacitor
50
ms
V
2
22
800
1000
-2
%
23
V
10
mA
560
Enabled when rail is disabled
V
%
0.998
Mismatch to any other RDIS
CD
16.8
90
KHz
1200
2
Ω
%
10
nF
1
2.2
µF
15.2
16
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
PG
Power good threshold
Fraction of nominal output voltage
Power good time-out
Not tested in production
Feedback voltage
VFB
Accuracy
VEE_OUT
Output voltage range
ILOAD
Load current range
fSW
Switching frequency
RDIS
Discharge impedance to ground
Driver capacitor
CO
Nominal output capacitor
8
ILOAD = 2 mA
-2
VSET = –20 V, ILOAD = 3 mA
-21
50
ms
-20
V
2
%
-19
V
12
560
Enabled when rail is disabled
800
1000
-2
Capacitor tolerance ±10%
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1
V
%
-0.994
Mismatch to any other RDIS
CD
16.8
90
mA
KHz
1200
2
Ω
%
10
nF
2.2
µF
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
THERMISTOR MONITOR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(3)
ATMS
Temperature to voltage ratio
OffsetTMS
Offset
VTMS_HOT
Temp hot trip voltage (T = 50°C)
VTMS_COOL Temp hot escape voltage (T = 45°C)
Not tested in production
-0.0161
V/°C
Temperature = 0°C
1.575
V
TEMP_HOT_SET = 0x8C
0.768
V
TEMP_COOL_SET = 0x82
0.845
V
VTMS_MAX
Maximum input level
RNTC_PU
Internal pull up resistor
RLINEAR
External linearization resistor
ADCRES
ADC resolution
ADCDEL
ADC conversion time
Not tested in production
TMSTTOL
Accuracy
Not tested in production
Not tested in production, 1 bit
2.25
V
7.307
KΩ
43
KΩ
16.1
mV
19
µs
-1
1
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(bias)
Input bias current
IO = 3 mA, sink current
(SDA, nINT, PWR_GOOD)
0.4
V
1
µA
V
VIO = 1.8 V
Not tested in production
500
Deglitch time, PWRUP pin
Not tested in production
400
tdischarge
Discharge delay
Not tested in production
100 (4)
fSCL
SCL clock frequency
I2C slave address
V
1.2
Deglitch time, WAKEUP pin
tdeglitch
0.4
µs
ms
400
KHz
0x68h (5)
7-bit address
OSCILLATOR
fOSC
Oscillator frequency
Frequency accuracy
9
TA = –40°C to 85°C
-10
MHz
10
%
THERMAL SHUTDOWN
TSHTDWN
Thermal trip point
Thermal hysteresis
(3)
(4)
(5)
150
°C
20
°C
10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel
temperature measurement.
Contact factory for 50-ms, 200-ms or 400-ms option.
Contact factory for alternate address of 0x48h.
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TYPICAL CHARACTERISTICS
10
DEFAULT POWER-UP SEQUENCE
DEFAULT POWER-DOWN SEQUENCE
Figure 1.
Figure 2.
INRUSH CURRENT @ VIN = 3.7 V, CIN = 100 µF
INRUSH CURRENT @ VIN = 5 V, CIN = 100 µF
Figure 3.
Figure 4.
SWITCHING WAVE FORMS, VN
VIN = 3 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
SWITCHING WAVE FORMS, VB
VIN = 3 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
SWITCHING WAVE FORMS, VN
VIN = 3.7 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
SWITCHING WAVE FORMS, VB
VIN = 3.7 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
Figure 7.
Figure 8.
SWITCHING WAVE FORMS, VN
VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
SWITCHING WAVE FORMS, VB
VIN = 5 V, RLOAD, VPOS = 330 Ω, RLOAD, VNEG = 330 Ω,
No Load on VDDH, VEE
Figure 9.
Figure 10.
VB DCDC EFFICIENCY, T = 25°C
100
90
90
80
80
70
70
60
V IN= 3. 5
50
V IN= 5V
Efficiency [%]
Efficiency [%]
VN DCDC EFFICIENCY, T = 25°C
100
40
60
VIN= 3. 5
50
VIN= 5V
40
30
30
20
20
10
10
0
0
0
25
50
75
100
125
150
175
0
25
50
75
100
Output Current [m A]
Output Current [m A]
Figure 11.
Figure 12.
125
150
175
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TYPICAL CHARACTERISTICS (continued)
VEE CHARGE PUMP EFFICIENCY, T = 25°C
VDDH CHARGE PUMP EFFICIENCY, T = 25°C
100
100
90
90
VIN=5V
VIN=5V
80
80
VIN=3.5V
VIN=3. 5
70
Efficiency [%]
Efficiency [%]
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0
2
4
6
8
10
12
0
2
6
8
10
12
Output Current [mA]
Figure 13.
Figure 14.
3p3V SWITCH IMPEDANCE
VIN = 3.7 V, ILOAD, V3p3 = 10 mA
SOURCE DRIVER SUPPLY TRACKING
VIN = 3.7 V
50
25
IPO S = INE G
40
IPO S s we ep, IN E G= 15m A
30
20
VPOS + VNEG[mV]
R[W], (VIN3p3-V3P3)/10mA
4
Output Current [mA]
15
10
IPO S = 15m A , IN EG s w eep
20
10
0
-1 0
-2 0
-3 0
5
-4 0
-5 0
0
1
1.5
2
2.5
3
3.5
0
4
25
50
75
100
125
1 50
1 75
C u rre n t [m A]
VIN3P3[V]
Figure 15.
Figure 16.
VCOM INTEGRATED NON-LINEARITY
VIN = 3.7 V, RLOAD, VCOM = 1 kΩ
VCOM DIFFERENTIAL NON-LINEARITY
VIN = 3.7 V, RLOAD, VCOM = 1 kΩ
5
0.2
4
0 .15
3
0.1
DNL[LSB]
INL [mV]
2
1
0
-1
0 .05
0
-0 .05
-2
-0.1
-3
-0 .15
-4
-0.2
-5
0
64
128
192
25 6
320
384
44 8
512
Figure 17.
12
0
64
12 8
1 92
2 56
3 20
384
448
512
V CO M C OD E
VC O M C OD E
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
KICKBACK VOLTAGE MEASUREMENT TIMING
VIN = 3.7 V; AVG[1:0] = 00 (Single Measurement)
Time from ACQ Bit Set to ACQC Interrupt Received
KICKBACK VOLTAGE MEASUREMENT ERROR
VIN = 3.7 V
2
Measurementerror [LSB]
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
640 12 80 192 0 2560 3200 3840 44 80 512 0
F o rce d Kick ba c k Vo lta g e [m V]
Figure 19.
Figure 20.
KICKBACK VOLTAGE MEASUREMENT TIMING
VIN = 3.7 V; AVG[1:0] = 11 (Eight Measurements)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 21.
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MODES OF OPERATION
The TPS65185 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the
lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the
device is ready to accept commands through the I2C interface. In ACTIVE mode one or more power rails are
enabled.
SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off, registers are
reset to default values and the device does not respond to I2C communications. TPS65185
enters SLEEP mode whenever WAKEUP pin is pulled low.
STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept
commands through the I2C interface but none of the power rails are enabled. The device
enters STANDBY mode when the WAKEUP pin is pulled high and either the PWRUP pin is
pulled low or the STANDBY bit is set. The device also enters STANDBY mode if input Under
Voltage Lock Out (UVLO), positive boost Under Voltage (VB_UV), or inverting buck-boost
Under Voltage (VN_UV) is detected, thermal shutdown occurs, or the PROG bit is set (see
VCOM calibration).
ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault
condition is present. This is the normal mode of operation while the device is powered up.
MODE TRANSISITONS
SLEEP → ACTIVE
WAKEUP pin is pulled high with PWRUP pin high. Rails come up in the order defined by the
UPSEQx registers (OK to tie WAKEUP and PWRUP pin together).
SLEEP → STANDBY
WAKEUP pin is pulled high with PWRUP pin low. Rails will remain powered down.
STANDBY → ACTIVE
WAKEUP pin is high and PWRRUP pin is pulled high (rising edge) or the ACTIVE bit is set.
Output rails will power up in the order defined by the UPSEQx registers.
ACTIVE → STANDBY
WAKEUP pin is high and STANDBY bit is set or PWRUP pin is pulled low (falling edge).
Rails are shut down in the order defined by DWNSEQx registers. Device also enters
STANDBY in the event of Thermal Shut Down (TSD), Under Voltage Lock Out (UVLO),
positive boost or inverting buck-boost Under Voltage (UV), VCOM fault (VCOMF), or when
the PROG bit is set (see VCOM calibration).
STANDBY → SLEEP
WAKEUP pin is pulled low while none of the output rails are enabled.
ACTIVE → SLEEP
WAKEUP pin is pulled low while at least one output rail is enabled. Rails are shut down in
the order defined by DWNSEQx registers.
14
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POWER DOWN
All rails
= OFF
V3P3 switch = OFF
I2C
= NO
Registers à default
SLEEP
WAKEUP = high & PWRUP = high
WAKEUP = high &
PWRUP= low
WAKEUP = low
WAKEUP = low
Battery removed
All rails
I2C
STANDBY
WAKEUP = high &
(STANDBY bit = 1||
PWRUP(?) || FAULT )
= OFF
= YES
WAKEUP = high &
(ACTIVE bit = 1 || PWRUP( ) )
?
ACTIVE
NOTES:
||, &
( ), (?)
UVLO
TSD
UV
= logic OR, logic AND.
= rising edge, falling edge.
= Under Voltage Lock Out
= Thermal Shut Down
= Under Voltage
FAULT
= UVLO || TSD || BOOST UV || VCOM fault.
Rails
I2C
= ON
= YES
?
Figure 22. Global State Diagram
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WAKE-UP AND POWER UP SEQUENCING
The power-up/down order and timing is defined by user register settings. The default settings support the E Ink®
Vizplex™ panel and typically do not need to be changed.
In SLEEP mode the TPS65185 is completely turned off, the I2C registers are reset, and the device does not
accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY
mode which enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails
are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set
the ACTIVE bit in the ENABLE register to ‘1’ to execute the power-up sequence and bring up all power rails.
Alternatively pull the PWRUP pin high (rising edge).
After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive
boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB
is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is
issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and
delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and
the last rail has been enabled.
To power-down the device, set the STANDBY bit of the ENABLE register to ‘1’ or pull the PWRUP pin low (falling
edge) and the TPS65185 will power down in the order defined by DWNSEQx registers. The delay times DDLY2,
DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power-down of
the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is
shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for
another 100 ms (discharge delay) to allow complete discharge of all rails. After the discharge delay, VN is
powered down and the device enters STANDBY or SLEEP mode, depending on the WAKEUP pin.
If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the
power-down sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or
may not be powered down and the discharge delay may be cut short depending on the relative timing of
STROBE4 to the new power-up event.
During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted
and the power-down sequence starts immediately.
DEPENDENCIES BETWEEN RAILS
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed below.
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power
good.
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VN PG
VN
powers up
VB PG
VB
powers up
STROBE 1
STROBE 2
PG1
UDLY1
STROBE 1
DDLY1
STROBE 2
DDLY2
1st rail
powers down
2 nd rail
powers down
PG3
UDLY3
2 nd rail
powers up
STROBE 3
DDLY3
STROBE 4
PG2
UDLY2
1st rail
powers up
ACTIVE bit
or
WAKEUP high
STROBE 3
PG4
UDLY4
3 nd rail
powers up
4 th rail
powers up
STROBE 4
DDLY4
3 nd rail
powers down
4 th rail
powers down
Discharge DELAY
VB
powers down
STANDBY bit
or
WAKEUP low
VN
powers down
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after
ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register
and delays between STROBES are defined in UPSEQ1 register.
BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down
sequence are set in DWNSEQ0 and DWNSEQ1 register.
Figure 23. Power-Up and Power-Down Sequence
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VIN
I2C
1.8ms (1)
PWRUP
SLEEP
WAKEUP
STANDBY
ACTIVE
ACTIVE
Discharge Delay
VN
VB
UDLY 1
DDLY 4
UDLY 1
VNEG
UDLY 2
UDLY 2
VEE
UDLY 3
DDLY 3
UDLY3
VPOS
UDLY 4
DDLY 2
UDLY 4
VDDH
DDLY 1
PWR_GOOD
300 us (max)
300 us (max)
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
In this example the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is
initiated by pulling the WAKEUP pin low (device enters SLEEP mode). The 2nd power-up sequence is initiated by
pulling the WAKEUP pin high while the PWRUP pin is also high (power up from SLEEP to ACTIVE).
Figure 24. Power-Up and Power-Down Timing Diagram
SOFTSTART
TPS65185 supports soft-start for all rails, i.e. inrush current is limited during startup of DCDC1, DCDC2, LDO1,
LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the
corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters
STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out
limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set
and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.
ACTIVE DISCHARGE
TPS65185 provides low-impedance discharge paths for the display power rails (VEE, VNEG, VPOS, VDDH, and
VCOM) which are enabled whenever the corresponding rail is disabled. The discharge paths are connected to
the rails on the PCB which allows adding external resistors to customize the discharge time. However, external
resistors are not required.
Active discharge remains enabled for 100 ms after the last rail has been disabled (STROBE4 has been
executed). During this time the negative boost converter (VN) remains up. After the discharge delay, VN is shut
down and the device enters STANDBY or SLEEP mode, depending on the state of the WAKEUP pin.
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VPOS/VNEG SUPPLY TRACKING
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV.
V3P3 POWER SWITCH
The integrated power switch is used to cut the 3.3-V supply to the EPD panel and is controlled through the
V3P3_EN pin of the ENABLE register. In SLEEP mode the switch is automatically turned off and its output is
discharged to ground. The default power-up state is OFF. To turn the switch ON, set the V3P3_ENbit to 1.
VCOM ADJUSTMENT
VCOM is the output of a power-amplifier with an output voltage range of 0 V to -5.11 V, adjustable in 10-mV
steps. In a typical application VCOM is connected to the VCOM terminal of the EPD panel and the amplifier is
controlled through the VCOM_CTRL pin. With VCOM_CTRL high, the amplifier drives the VCOM pin to the
voltage specified by the VCOM1 and VCOM2 register. When pulled low, the amplifier turns off and VCOM is
actively discharged to ground through VCOM_DIS pin. If active discharge is not desired, simply leave the
VCOM_DIS pin open.
For ease of design, the VCOM_CTRL pin may also be tied to the battery or IO supply. In this case, VCOM is
enabled with STROBE4 during the power-up sequence and disabled on STROBE1 of the power-down sequence.
Therefore VCOM is the last rail to be enabled and the first to be disabled.
KICK-BACK VOLTAGE MEASUREMENT
TPS65185 can perform a voltage measurement on the VCOM pin to determine the kick-back voltage of the
panel. This allows in-system calibration of VCOM. To perform a kick-back voltage measurement, follow these
steps:
• Pull the WAKEUP pin and the PWRUP pin high to enable all output rails.
• Set the HiZ bit in the VCOM2 register. This puts the VCOM pin in a high-impedance state.
• Drive the panel with the Null waveform. Refer to E-Ink specification for detail.
• Set the ACQ bit in the VCOM2 register to 1. This starts the measurement routine.
• When the measurement is complete, the ACQC (Acquisition Complete) bit in the INT1 register is set and the
nINT pin is pulled low.
• The measurement result is stored in the VCOM[8:0] bits of the VCOM1 and VCOM2 register.
Please note that the measurement result is not automatically programmed into non-volatile memory. Changing
the power-up default is described in the following paragraph.
STORING THE VCOM POWER-UP DEFAULT VALUE IN MEMORY
The power-up default value of VCOM can be user-set and programmed into non-volatile memory. To do so, write
the default value to the VCOM[8:0] bits of the VCOM1 and VCOM2 register, then set the PROG bit in VCOM2
register to 1. First, all power rails are shut-down, then the VCOM[8:0] value is committed to non-volatile memory
such that it becomes the new power-up default. Once programming is complete, the PRGC bit in the INT1
register is set and the nINT pin is pulled low. To verify that the new value has been saved properly, first write the
VCOM[8:0] bits to 0x000h, then pull the WAKEUP pin low. After the WAKEUP pin is pulled back high, read the
VCOM[8:0] bits to verify that the new default value is correct.
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10uF
VIN
From Input Supply
(3.0V-6.0V)
INT_LDO
INT_LDO
4.7uF
4.7uF
VCOM_DIS
VREF
AGND1
4.7uF
VCOM
To panel back -plane
(-0.5 to -5.0V, 15mA)
From uC
VREF
500
VCOM_CTRL
DAC
VCOM[8:0]
4.7uF
VCOM_PWR
From VN (-17V)
Figure 25. Block Diagram of VCOM Circuit
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SETUP
Pull WAKEUP = HIGH
Pull PWRUP= HIGH
Write HiZ = 1
Device enters ACTIVE mode
All power rails are up except VCOM
VCOM pin is in HiZ state
Processor drives panel with NULL waveform
MEASUREMENT
Write ACQ = 1
Wait for ACQC interrupt
Read result from VCOM1/2
registers
VERIFICATION
PROGRAMMING
Pull PWRUP= LOW
Write HiZ = 0
Write PROG= 1
Wait for PRGC interrupt
Starts A/D conversion
Indicates A/D conversion is complete
If AVG[1:0] is <> 00, interrupt is issed
after all conversions are complete and
average has been calcutated.
Check result and decide to keep the
value or repeat measurment.
Device enters STANDBY mode
Starts the EEPROM programming cycle
.
Power must not be interrupted.
Indicates programming is complete
Pull WAKEUP = LOW
Device enters SLEEP mode
Pull WAKEUP = HIGH
Device enters STANDBY mode
Read VCOM[8:0]
Compare against written value to
confirm new default has been
programmed correctly.
Figure 26. VCOM Calibration Flow
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FAULT HANDLING AND RECOVERY
The TPS65185 monitors input and output voltages and die temperature and will take action if operating
conditions are outside normal limits. Whenever the TPS65185 encounters:
• Thermal Shutdown (TSD)
• Positive Boost Under Voltage (VB_UV)
• Inverting Buck-Boost Under Voltage (VN_UV)
• Input Under Voltage Lock Out (UVLO)
it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx
registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected,
the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register.
Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2
register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge
sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, i.e. it must bring the
PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I2C interface.
Whenever the TPS65185 encounters under-voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV)
or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the
corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault
has been removed.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high (by an external pull-up resistor)
when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails
encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only
after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).
INTERRUPT PIN
The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT1 or INT2 bits
are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit
has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32 µs.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register,
i.e. the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits
affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits
themselves.
Note that persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended
period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set
the corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the
fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
PANEL TEMPERATURE MONITORING
The TPS65185 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor
(NTC) to monitor the display panel temperature in a range from -10°C to 85°C with and accuracy of ±1°C from
0°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature
reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the
programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed
by more than a user-defined threshold from the baseline value. Details are explained under “HOT, COLD, and
temperature-change interrupts”.
22
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NTC BIAS CIRCUIT
Figure 27 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-kΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1.
Table 1. ADC Output Value vs Termperature
TEMPERATURE
TMST_VALUE[7:0]
< -10°C
1111 0110
-10°C
1111 0110
-9°C
1111 0111
...
...
-2°C
1111 1110
-1°C
1111 1111
0°C
0000 0000
1°C
0000 0001
2°C
0000 0010
...
...
25°C
0001 1001
...
85°C
0101 0101
> 85°C
0101 0101
2.25V
7.307k
10
Digital
ADC
TS
43k
10k NTC
AGND2
Figure 27. NTC Bias and Measurement Circuit
A temperature measurement is triggered by setting the READ_THERM bit of the TMST1 register to 1.During the
A/D conversion the CONV_END bit of the TMST1 register reads ‘0’, otherwise it reads ‘1’. At the end of the A/D
conversion the EOC bit in the INT2 register is set and the temperature value is available in the TMST_VALUE
register.
HOT, COLD, AND TEMPERATURE-CHANGE INTERRUPTS
Each temperature acquisition is compared against the programmable TMST_HOT and TMST_COLD thresholds
and to the baseline temperature, to determine if the display is within allowed operating temperature range and if
the temperature has changed by more than a user-defined threshold since the last update. The first temperature
reading after the WAKEUP pin has been pulled high automatically becomes the baseline temperature. Any
subsequent reading is compared against the baseline temperature. If the difference is equal or greater than the
threshold value, an interrupt is issued (DTX bit in register INT1 is set to ‘1’) and the latest value becomes the
new baseline. If the difference is less than the threshold value, no action is taken. The threshold value is defined
by DT[1:0] bits in the TMST1 register and has a default value of ±2°C. In summary:
• When the temperature is equal or less than the TMST_COLD[3:0] threshold, the TMST_COLD interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
• When the temperature is greater than TMST_COLD but lower then TMST_HOT, no action is taken.
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•
•
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When the temperature is equal or greater than the TMST_HOT[3:0] threshold, the TMST_HOT interrupt bit of
the INT1 register is set, and the nINT pin is pulled low.
If the last temperature is different from the baseline temperature by ±2°C (default) or more, the DTX interrupt
bit of the INT1 register is set. The latest temperature becomes the new baseline temperature. Please note
that by default the DTX interrupt is disabled, i.e. the nINT pin is not pulled low unless the DTX_EN bit was
previously set high.
If the last temperature change is less than ±2°C (default), no action is taken.
TYPICAL APPLICATION OF THE TEMPERATURE MONITOR
In a typical application the temperature monitor and interrupts are used in the following manner:
• After the WAKEUP pin has been pulled high, the Application Processor (AP) writes 0x80h to the TMST1
register (address 0x0Dh). This starts the temperature measurement.
• The AP waits for the EOC interrupt. Alternatively the AP can poll the CONV_END bit in register TMST1. This
will notify the AP that the A/D conversion is complete and the new temperature reading is available in the
TMST_VALUE register (address (0x00h).
• The AP reads the temperature value from the TMST_VALUE register (address (0x00h).
• If the temperature changes by ±2°C (default) or more from the first reading, the processor is notified by the
DTX interrupt. The A/P may or may not decide to select a different set of wave forms to drive the panel.
• If the temperature is outside the allowed operating range of the panel, the processor is notified by the THOT
and TCOLD interrupts, respectively. It may or may not decide to continue with the page update.
• Once an over/under temperature has been detected, the AP should reset the TMST_HOT_EN or
TMST_COLD_EN bits, respectively, to avoid the nINT pin to be continuously pulled low. The TMST_HOT and
TMST_COLD interrupt bits then should be polled continuously, to determine when the panel temperature
recovers to the normal operating range. Once the temperature has recovered, the TMST_HOT_EN or
TMST_COLD_EN bits should be set to ‘1’ again and normal operation can resume.
I2C BUS OPERATION
The TPS65185 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Reg Address
S
A6 A5 A4 A3 A2 A1 A0
S
Start Condition
A
Acknowledge
A6 ... A0 Device Address
Read / not Write
P
Stop Condition
S7 ... S0 Sub-Address
R/nW
R/nW
A
S7 S6 S5 S4 S3 S2 S1 S0
Data
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
D7 ... D0 Data
Figure 28. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 30. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate slave address bits are set for the device, then the device will issue an
acknowledge pulse and prepare to receive the register address. Depending on the R/nW bit, the next byte
received from the master is written to the addressed register (R/nW = 0) or the device responds with 8-bit data
from the register (R/nW = 1). Data transmission is completed by either the reception of a stop condition or the
24
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reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the
SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the
low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and
data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be
sent for a given I2C transmission. Reference Figure 29 and Figure 30 for deail.
S
SLAVE ADDRESS
W A
REG ADDRESS
A
DATA REGADDR
A
DATA SUBADDR +n
A
DATA SUBADDR +n+1
Ā P
A S
SLAVE ADDRESS
R A
DATA REGADDR +n
A
n bytes + ACK
S
SLAVE ADDRESS
W A
REG ADDRESS
DATA REGADDR
A
DATA REGADDR + n+1
Ā P
n bytes + ACK
From master to slave
R Read (high)
S Start
Ā Not Acknowlege
From slave to master
W Write (low)
P Stop
A Acknowlege
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 29. I2C Data Protocol
SDA
SCL
1-7
8
9
ADDRESS
R/W
ACK
1-7
8
9
1-7
8
9
S
START
P
DATA
ACK
DATA
ACK/
nACK
STOP
Figure 30. I2C Start/Stop/Acknowledge Protocol
SDA
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT tHIGH
tSU;STA
tSU;STO
Sr
tf
P
S
Figure 31. I2C Data Transmission Timing
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DATA TRANSMISSION TIMING
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(SCL)
Serial clock frequency
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
Data hold time
tSU;DAT
Data set-up time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU;STO
Set-up time for STOP condition
tBUF
Bus Free Time Between Stop and Start Condition
tSP
Pulse width of spikes which mst be suppressed
by the input filter
Cb
Capacitive load for each bus line
26
TYP
100
tLOW
tHD;DAT
MIN
MAX
400
UNIT
KHz
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
µs
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
µs
SCL = 400 KHz
600
SCL = 100 KHz
0
3.45
µs
SCL = 400 KHz
0
900
ns
SCL = 100 KHz
250
SCL = 400 KHz
100
ns
ns
SCL = 100 KHz
1000
SCL = 400 KHz
300
SCL = 100 KHz
300
SCL = 400 KHz
300
ns
ns
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
SCL = 100 KHz
n/a
n/a
SCL = 400 KHz
0
50
µs
SCL = 100 KHz
400
SCL = 400 KHz
400
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REGISTER ADDRESS MAP
REGISTER
ADDRESS (HEX)
NAME
DEFAULT
VALUE
0
0x00
TMST_VALUE
N/A
Thermistor value read by ADC
1
0x01
ENABLE
N/A
Enable/disable bits for regulators
2
0x02
VADJ
N/A
VPOS/VNEG voltage adjustment
3
0x03
VCOM1
N/A
Voltage settings for VCOM
4
0x04
VCOM2
N/A
Voltage settings for VCOM + control
5
0x05
INT_EN1
N/A
Interrupt enable group1
6
0x06
INT_EN2
N/A
Interrupt enable group2
7
0x07
INT1
N/A
Interrupt group1
8
0x08
INT2
N/A
Interrupt group2
9
0x09
UPSEQ0
N/A
Power-up strobe assignment
10
0x0A
UPSEQ1
N/A
Power-up sequence delay times
11
0x0B
DWNSEQ0
N/A
Power-down strobe assignment
12
0x0C
DWNSEQ1
N/A
Power-down sequence delay times
13
0x0D
TMST1
N/A
Thermistor configuration
14
0x0E
TMST2
N/A
Thermistor hot temp set
15
0x0F
PG
N/A
Power good status each rails
16
0x10
REVID
N/A
Device revision ID information
DESCRIPTION
THERMISTOR READOUT (TMST_VALUE)
Address – 0x00h
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
TMST_VALUE[7:0]
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
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ENABLE (ENABLE)
Address – 0x01h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
ACTIVE
STANDBY
V3P3_EN
VCOM_EN
VDDH_EN
VPOS_EN
VEE_EN
VNEG_EN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
STANDBY to ACTIVE transition bit
ACTIVE
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by UPSEQx registers
0 – no effect
NOTE: After transition bit is cleared automatically
STANDBY to ACTIVE transition bit
STANDBY
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by DWNSEQx registers
0 – no effect
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.
VIN3P3 to V3P3 switch enable
V3P3_EN
1 – switch is ON
0 – switch is OFF
VCOM buffer enable
VCOM_EN
1 – enabled
0 – disabled
VDDH charge pump enable
VDDH_EN
1 – enabled
0 – disabled
VPOS LDO regulator enable
VPOS_EN
1 – enabled
0 – disabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
VEE charge pump enable
VEE_EN
1 – enabled
0 – disabled
VNEG LDO regulator enable
VNEG_EN
1 – enabled
0 – disabled
NOTE: When VNEG is disabled VPOS will also be disabled.
(1)
28
Enable bits always reflect actual status of the corresponding rail.
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VOLTAGE ADJUSTMENT REGISTER (VADJ)
Address – 0x02h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
not used
not used
not used
not used
not used
READ/WRITE
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0E2
1E2
1E2
D2
D1
D0
FIELD NAME
VSET[2:0]
BIT DEFINITION
not used
N/A
not used
N/A
not used
N/A
not used
N/A
not used
N/A
VPOS and VNEG voltage setting
000 - not valid
001 - not valid
010 - not valid
VSET[2:0]
011 - ±15.000 V
100 - ±14.750 V
101 - ±14.500 V
110 - ±14.250 V
111 - reserved
VCOM 1 (VCOM1)
Address – 0x03h
DATA BIT
D7
D6
D5
D4
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0E2
1E2
1E2
1E2
1
1
0
1
FIELD NAME
VCOM [7:0]
FIELD NAME
VCOM[7:0]
D3
BIT DEFINITION
VCOM voltage, least significant byte. See VCOM2 register for details.
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VCOM 2 (VCOM2)
Address – 0x04h
DATA BIT
D7
D6
D5
D4
D3
D1
D0
FIELD NAME
ACQ
PROG
HiZ
not used
not used
VCOM[8]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
0
0
1
0
0E2
FIELD NAME
AVG[1:0]
D2
BIT DEFINITION
Kick-back voltage acquisition bit
1 – starts kick-back voltage measurement routine
ACQ
0 – no effect
NOTE: After measurement is complete bit is cleared automatically and measurement result is
reflected in VCOM[8:0] bits.
VCOM programming bit
PROG
1 – VCOM[8:0] value is committed to non-volatile memory and becomes new power-up default
0 – no effect
NOTE: After programming bit is cleared automatically and TPS65185 will enter STANDBY mode.
VCOM HiZ bit
HiZ
1 – VCOM pin is placed into hi-impedance state to allow VCOM measurement
0 – VCOM amplifier is connected to VCOM pin
Number of acquisitions that is averaged to a single kick-back voltage measurement
00 – 1x
01 – 2x
AVG[1:0]
10 – 4x
11 – 8x
NOTE: When the ACQ bit is set, the state machine repeat the A/D conversion of the kick-back
voltage AVD[1:0] times and returns a single, averaged, value to VCOM[8:0]
not used
N/A
not used
N/A
VCOM voltage adjustment
VCOM = VCOM[8:0] x -10 mV in the range from 0 mV to -5.110 V
0x000h – 0 0000 0000 – -0 mV
0x001h – 0 0000 0001 – -10 mV
VCOM[8:0]
0x002h – 0 0000 0010 – -20 mV
...
0x07Dh - 0 0111 1101 - -1250 mV
...
0x1FEh – 1 1111 1110 – -5100 mV
0x1FFh – 1 1111 1111 – -5110 mV
30
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INTERRUPT ENABLE 1 (INT_EN1)
Address – 0x05h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
TMST_COLD
_EN
UVLO_EN
ACQC_EN
PRGC_EN
FIELD NAME
DTX_EN
TSD_EN
HOT_EN
TMST_HOT
_EN
READ/WRITE
R
R/W
R/W
R/W
R/W
R/W
R
R
RESET VALUE
0
1
1
1
1
1
1
1
BIT DEFINITION (1)
FIELD NAME
Panel temperature-change interrupt enable
DTX_EN
1 – enabled
0 – disabled
Thermal shutdown interrupt enable
TSD_EN
1 – enabled
0 – disabled
Thermal shutdown early warning enable
HOT_EN
1 – enabled
0 – disabled
Thermistor hot interrupt enable
TMST_HOT_EN
1 – enabled
0 – disabled
Thermistor cold interrupt enable
TMST_COLD_EN
1 – enabled
0 – disabled
VIN under voltage detect interrupt enable
UVLO_EN
1 – enabled
0 – disabled
VCOM acquisition complete interrupt enable
ACQC_EN
1 – enabled
0 – disabled
VCOM programming complete interrupt enable
PRGC_EN
1 – enabled
0 – disabled
(1)
Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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INTERRUPT ENABLE 2 (INT_EN2)
Address – 0x06h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VBUVEN
VDDHUVEN
VNUV_EN
VPOSUVEN
VEEUVEN
VCOMFEN
VNEGUVEN
EOCEN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
1
1
1
1
1
1
1
BIT DEFINITION (1)
FIELD NAME
Positive boost converter under voltage detect interrupt enable
VBUVEN
1 – enabled
0 – disabled
VDDH under voltage detect interrupt enable
VDDHUVEN
1 – enabled
0 – disabled
Inverting buck-boost converter under voltage detect interrupt enable
VNUVEN
1 – enabled
0 – disabled
VPOS under voltage detect interrupt enable
VPOSUVEN
1 – enabled
0 – disabled
VEE under Voltage detect interrupt enable
VEEUVEN
1 – enabled
0 – disabled
VCOM FAULT interrupt enable
VCOMFEN
1 – enabled
0 – disabled
VNEG under Voltage detect interrupt enable
VNEGUVEN
1 – enabled
0 – disabled
Temperature ADC end of conversion interrupt enable
EOCEN
1 – enabled
0 – disabled
(1)
32
Enabled means nINT pin is pulled low when interrupt occurs.
Disabled means nINT pin is not pulled low when interrupt occurs.
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INTERRUPT 1 (INT1)
Address – 0x07h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
DTX
TSD
HOT
TMST_HOT
TMST_COLD
UVLO
ACQC
PRGC
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
N/A
N/A
N/A
N/A
N/A
0
0
FIELD NAME
BIT DEFINITION
Panel temperature-change interrupt
DTX
1 – temperature has changed by 3 deg or more over previous reading
0 – no significance
Thermal shutdown interrupt
TSD
1 – chip is in over-temperature shutdown
0 – no fault
Thermal shutdown early warning
HOT
1 – chip is approaching over-temperature shutdown
0 – no fault
Thermistor hot interrupt
TMST_HOT
1 – thermistor temperature is equal or greater than TMST_HOT threshold
0 – no fault
Thermistor cold interrupt
TMST_COLD
1 – thermistor temperature is equal or less than TMST_COLD threshold
0 – no fault
VIN under voltage detect interrupt
UVLO
1 – input voltage is below UVLO threshold
0 – no fault
VCOM acquisition complete
ACQC
1 – VCOM measurement is compete
0 – no significance
VCOM programming complete
PRGC
1 – VCOM programming is complete
0 – no significance
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INTERRUPT 2 (INT2)
Address – 0x08h
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
EOC
FIELD NAME
VB_UV
VDDH_UV
VN_UV
VPOS_UV
VEE_UV
VCOMF
VNEG_UV
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
BIT DEFINITION
Positive boost converter under voltage detect interrupt
VB_UV
1 – under-voltage on DCDC1 detected
0 – no fault
VDDH under voltage detect interrupt
VDDH_UV
1 – under-voltage on VDDH charge pump detected
0 – no fault
Inverting buck-boost converter under voltage detect interrupt
VN_UV
1 – under-voltage on DCDC2 detected
0 – no fault
VPOS under voltage detect interrupt
VPOS_UV
1 – under-voltage on LDO1(VPOS) detected
0 – no fault
VEE under Voltage detect interrupt
VEE_UV
1 – under-voltage on VEE charge pump detected
0 – no fault
VCOM fault detection
VCOMF
1 – fault on VCOM detected (VCOM is outside normal operating range)
0 – no fault
VNEG under Voltage detect interrupt
VNEG_UV
1 – under-voltage on LDO2(VNEG) detected
0 – no fault
ADC end of conversion interrupt
EOC
1 – ADC conversion is complete (temperature acquisition is complete)
0 – no significance
34
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POWER UP SEQUENCE REGISTER 0 (UPSEQ0)
Address – 0x09h
DATA BIT
D7
FIELD NAME
D6
VDDH_UP[1:0]
D5
D4
D3
VPOS_UP[1:0]
D2
VEE_UP[1:0]
D1
D0
VNEG_UP[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1E2
1E2
1E2
0E2
0E2
1E2
0E2
0E2
FIELD NAME
BIT DEFINITION
VDDH power-up order
00 – power up on STROBE1
VDDH_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VPOS power-up order
00 – power up on STROBE1
VPOS_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VEE power-up order
00 – power up on STROBE1
VEE_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
VNEG power-up order
00 – power up on STROBE1
VNEG_UP[1:0]
01 – power up on STROBE2
10 – power up on STROBE3
11 – power up on STROBE4
6ms
6ms
6ms
6ms
6ms
48ms
VDDH
VPOS
VNEG
VEE
Figure 32. Default Power-Up/Down Sequence
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POWER UP SEQUENCE REGISTER 1 (UPSEQ1)
Address – 0x0Ah
DATA BIT
D7
FIELD NAME
D6
UDLY4[1:0]
D5
D4
UDLY3[1:0]
D3
D2
UDLY2[1:0]
D1
D0
UDLY1[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0E2
1E2
0E2
1E2
0E2
1E2
0E2
1E2
FIELD NAME
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up.
00 – 3 ms
UDLY4[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up.
00 – 3 ms
UDLY3[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up.
00 – 3 ms
UDLY2[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
DLY1 delay time set; defines the delay time from VN_PG high to STROBE1 during power-up.
00 – 3 ms
UDLY1[1:0]
01 – 6 ms
10 – 9 ms
11 – 12 ms
36
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POWER DOWN SEQUENCE REGISTER 0 (DWNSEQ0)
Address – 0x0Bh
DATA BIT
D7
D6
D5
D4
D3
D2
D0
FIELD NAME
VDDH_DWN[1:0]
VPOS_DWN[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0E2
0E2
0E2
1E2
1E2
1E2
1E2
0E2
FIELD NAME
VEE_DWN[1:0]
D1
VNEG_DWN[1:0]
BIT DEFINITION
VDDH power-down order
00 – power down on STROBE1
VDDH_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VPOS power-down order
00 – power down on STROBE1
VPOS_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VEE power-down order
00 – power down on STROBE1
VEE_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
VNEG power-down order
00 – power down on STROBE1
VNEG_DWN[1:0]
01 – power down on STROBE2
10 – power down on STROBE3
11 – power down on STROBE4
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POWER DOWN SEQUENCE REGISTER 1 (DWNSEQ1)
Address – 0x0Ch
DATA BIT
D7
FIELD NAME
D6
DDLY4[1:0]
D5
D4
D2
DDLY2[1:0]
D1
D0
DDLY1
DFCTR
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1E2
1E2
1E2
0E2
0E2
0E2
0E2
0E2
FIELD NAME
DDLY3[1:0]
D3
BIT DEFINITION
DLY4 delay time set; defines the delay time from STROBE3 to STROBE4 during power-down.
00 – 6 ms
DDLY4[1:0]
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY3 delay time set; defines the delay time from STROBE2 to STROBE3 during power-down.
00 – 6 ms
DDLY3[1:0]
01 – 12 ms
10 – 24 ms
11 – 4 8ms
DLY2 delay time set; defines the delay time from STROBE1 to STROBE2 during power-down.
00 – 6 ms
DDLY2[1:0]
01 – 12 ms
10 – 24 ms
11 – 48 ms
DLY2 delay time set; defines the delay time from WAKEUP low to STROBE1 during power-down.
DDLY1
0 – 3 ms
1 – 6 ms
At power-down delay time DLY2[1:0], DLY3[1:0], DLY4[1:0] are multiplied with DFCTR[1:0]
DFCTR
0 – 1x
1 – 16x
38
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THERMISTOR REGISTER 1 (TMST1)
Address – 0x0Dh
DATA BIT
D7
D6
D5
D4
D3
D2
FIELD NAME
READ_THERM
not used
CONV_END
not used
not used
not used
READ/WRITE
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0
0
0
FIELD NAME
D1
D0
DT[1:0]
BIT DEFINITION
Read thermistor value
READ_THERM
1 – initiates temperature acquisition
0 – no effect
NOTE: Bit is self-cleared after acquisition is completed
not used
N/A
ADC conversion done flag
CONV_END
1 – conversion is finished
0 – conversion is not finished
not used
N/A
not used
N/A
Panel temperature-change interrupt threshold
00 – 2°C
01 – 3°C
DT[1:0]
10 – 4°C
11 – 5°C
DTX interrupt is issued when difference between most recent temperature reading and baseline
temperature is equal to or greater than threshold value. See “HOT, COLD, and temperature-change
interrupts” section for details.
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THERMISTOR REGISTER 2 (TMST2)
Address – 0x0Eh
DATA BIT
D7
FIELD NAME
D6
D5
D4
D3
D2
TMST_COLD[3:0]
D1
D0
TMST_HOT[3:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
1
1
1
1
0
0
0
FIELD NAME
BIT DEFINITION
Thermistor COLD threshold
0000 – -7°C
0001 – -6°C
0010 – -5°C
0011 – -4°C
0100 – -3°C
0101 – -2°C
0110 – -1°C
TMST_COLD [3:0]
0111 – 0°C
1000 – 1°C
1001 – 2°C
1010 – 3°C
1011 – 4°C
1100 – 5°C
1101 – 6°C
1110 – 7°C
1111 – 8°C
NOTE: An interrupt is issued when thermistor temperature is equal or less than COLD threshold
Thermistor HOT threshold
0000 – 42°C
0001 – 43°C
0010 – 44°C
0011 – 45°C
0100 – 46°C
0101 – 47°C
0110 – 48°C
TMST_HOT [3:0]
0111 – 49°C
1000 – 50°C
1001 – 51°C
1010 – 52°C
1011 – 53°C
1100 – 54°C
1101 – 55°C
1110 – 56°C
1111 – 57°C
NOTE: An interrupt is issued when thermistor temperature is equal or greater than HOT threshold
40
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POWER GOOD STATUS (PG)
Address – 0x0Fh
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_PG
VDDH_PG
VN_PG
VPOS_PG
VEE_PG
not used
VNEG_PG
not used
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
D2
D1
D0
BIT DEFINITION (1)
FIELD NAME
Positive boost converter power good
VB_PG
1 – DCDC1 is in regulation
0 – DCDC1 is not in regulation or turned off
VDDH power good
VDDH_PG
1 – VDDH charge pump is in regulation
0 – VDDH charge pump is not in regulation or turned off
Inverting buck-boost power good
VN_PG
1 – DCDC2 is in regulation
0 – DCDC2 is not in regulation or turned off
VPOS power good
VPOS_PG
1 – LDO1(VPOS) is in regulation
0 – LDO1(VPOS) is not in regulation or turned off
VEE power good
VEE_PG
1 – VEE charge pump is in regulation
0 – VEE charge pump is not in regulation or turned off
not used
N/A
VNEG power good
VNEG_PG
1 – LDO2(VNEG) is in regulation
0 – LDO2(VNEG) is not in regulation or turned off
not used
(1)
N/A
PG pin is pulled hi (HiZ state) when VDDH_PG = VPOS_PG = VEE_PG = VNEG_PG = 1
REVISION AND VERSION CONTROL (REVID)
Address – 0x10h
DATA BIT
D7
D6
D5
D4
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
1
0
0
0E2
1E2
0E2
1E2
FIELD NAME
D3
REVID[7:0]
FIELD NAME
BIT DEFINITION
REVID[7:6]
MJREV
REVID[5:4]
MNREV
REVID[3:0]
VERSION
0100 0101 - TPS65185 1p0
REVID [7:0]
0101 0101 – TPS65185 1p1
0110 0101 – TPS65185 1p2
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS65185RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
E INK
TPS65185
TPS65185RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
E INK
TPS65185
TPS65185RSLR
ACTIVE
VQFN
RSL
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65185
TPS65185RSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65185
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS65185RGZR
VQFN
RGZ
48
TPS65185RGZT
VQFN
RGZ
TPS65185RSLR
VQFN
RSL
TPS65185RSLT
VQFN
RSL
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
48
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
48
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
48
250
180.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65185RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
TPS65185RGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
TPS65185RSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS65185RSLT
VQFN
RSL
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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