TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 ® PMIC FOR E Ink Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY Check for Samples: TPS65182, TPS65182B FEATURES 1 • Single Chip Power Management Solution for E Ink® Vizplex™ Electronic Paper Displays • Generates Positive and Negative Gate and Source Driver Voltages and Back-Plane Bias from a Single, Low-Voltage Input Supply • 3-V to 6-V Input Voltage Range • Boost Converter for Positive Rail Base • Inverting Buck-Boost Converter for Negative Rail Base • Two Adjustable LDOs for Source Driver Supply – LDO1: 15 V, 120 mA (VPOS) – LDO2: –15 V, 120 mA (VNEG) • Accurate Output Voltage Tracking – VPOS - VNEG = ±50 mV • Two Charge Pumps for Gate Driver Supply – CP1: 22 V, 10 mA (VDDH) – CP2: –20 V, 12 mA, (VEE) • Adjustable VCOM Driver for Accurate Panel-Backplane Biasing – –0.3 V to –2.5 V – Adjustable Through External Potentiometer – 15-mA Max Integrated Switch • 2345 • • • • Thermistor Monitoring – –10°C to 85°C Temperature Range – ±1°C Accuracy from 0°C to 50°C I2C Serial Interface – Slave Address 0x48h (1001000) Flexible Power-Up Sequencing Sleep Mode Support Thermally Enhanced Package for Efficient Heat Management (48-Pin 7 mm x 7 mm x 0.9 mm QFN) APPLICATIONS • • • • • Power Supply for Active Matrix E Ink® Vizplex™ Panels E-Book Readers EPSON® S1D13522 (ISIS) Timing Controller EPSON® S1D13521 (Broadsheet) Timing Controller Application Processors With Integrated or Software Timing Controller ( OMAP™) DESCRIPTION The TPS65182/TPS65182B device is a single-chip power supplies designed to for E Ink® Vizplex™ displays used in portable e-reader applications and support panel sizes up to 9.7 inches. Two high efficiency DC/DC boost converters generate ±17-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to 120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific panel requirements. Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or the I2C interface. The VCOM driver can source or sink current depending on panel condition. The TPS65182/TPS65182B provides precise temperature measurement function to monitor the panel temperature during operation. The temperature reading is updated every 60 s and can be accessed through the I2C interface. 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OMAP is a trademark of Texas Instruments. Vizplex is a trademark of E Ink Corporation. E Ink is a registered trademark of E Ink Corporation. EPSON is a registered trademark of Seiko Epson Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM 10uF 10uF VIN_P 2.2uH VB_SW From Input Supply (3.0V-6.0V) From Input Supply (3.0V-6.0V) 4.7uH 4.7uF DCDC1 PGND3 DCDC2 VB VN_SW VN 10uF PBKG 4.7uF VDDH_IN POSITIVE CHARGE PUMP VDDH_DRV 1M 4.7uF 10nF 4.7uF VEE_IN VDDH_D Gate driver Supply (22V, 10mA) VDDH_FB NEGATIVE CHARGE PUMP VEE_D Gate driver Supply (-20V, 12mA) VEE_DRV VEE_FB 1M 10nF 47.5k 4.7uF 53.6k PGND2 VPOS_IN VNEG_IN 4.7uF Source Driver Supply (15V, 120mA) 4.7uF 4.7uF VPOS LDO1 LDO2 VNEG Source Driver Supply (-15V, 120mA) 4.7uF 10k NTC TS TEMP SENSOR INT_LDO1 INT_LDO1 4.7uF 43k ADC INT_LDO2 INT_LDO2 4.7uF 10uF VIN From Input Supply (3.0V-6.0V) VREF VREF 4.7uF VCOM VCOM_XADJ 4.7uF AGND1 VNEG AGND2 VCOM_PWR DGND 4.7uF 4.7uF GATE DRIVER To panel back -plane (-0.3 to -2.5V, 15mA) From uC or DSP VCOM_PANEL VCOM_CTRL PWR[1] From uC or DSP From uC or DSP 10k VIO To uC or DSP PWR[2] From uC or DSP From uC or DSP PWR_GOOD PWR[3] From uC or DSP DIGITAL CORE PWR[0] SDA I2C WAKEUP 10k VIO From uC or DSP SCL From /to uC or DSP ORDERING INFORMATION (1) TA PACKAGE -10°C to 85°C (1) (2) RGZ (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TPS65182RGZR TPS65182 TPS65182BRGZR TPS65182B For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. SELECTION GUIDE 2 DEVICE PART NUMBER STATUS TPS6518 TPS65182RGZR Not recommended for new designs TPS6518B TPS65182BRGZR Active Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 DEVICE INFORMATION 25 - VN_SW 27 - VIN_P 26 - N/C 29 - VEE_IN 28 - VN 31 - VEE_D 30 - VEE_DRV 33 - PGND2 32 - VEE_FB 34 - VDDH_FB 36 - VDDH_DRV 35 - VDDH_D RGZ PACKAGE (TOP VIEW) 24 - PWR_GOOD 23 - PBKG VDDH_IN - 37 N/C - 38 22 - PWR0 N/C - 39 VB_SW - 40 21 - PWR1 20 - PWR2 PGND3 - 41 VB - 42 VPOS_IN - 43 19 - PWR3 18 - SDA 17 - SCL 16 - VCOM_PWR 15 - VCOM VPOS - 44 N/C - 45 N/C - 46 TS - 47 14 - VCOM_PANEL 13 - N/C VCOM_CTRL - 12 AGND1 - 8 INT_LDO1 -9 VIN – 10 VCOM_XADJ - 11 DGND - 6 INT_LDO2 - 7 N/C - 2 VNEG - 3 VNEG_IN - 4 WAKEUP - 5 VREF - 1 AGND2 - 48 TERMINAL FUNCTIONS (1) TERMINAL (1) I/O DESCRIPTION NAME NO. VREF 1 N/C 2 VNEG 3 O Negative supply output pin for panel source drivers VNEG_IN 4 I Input pin for LDO2 (VNEG) WAKEUP 5 I Wake up pin (active high). Pull this pin high to wake up from sleep mode. DGND 6 INT_LDO2 7 O Filter pin for 2.25-V internal reference to ADC Not connected Digital ground O Internal supply (digital circuitry) filter pin AGND1 8 INT_LDO1 9 O Analog ground for general analog circuitry Internal supply (analog circuitry) filter pin VIN 10 I Input power supply to general circuitry VCOM_XADJ 11 I Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set through I2C interface. VCOM_CTRL 12 I VCOM_PANEL gate driver enable (active high) N/C 13 Not connected There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 3 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 TERMINAL www.ti.com I/O DESCRIPTION NAME NO. VCOM_PANEL 14 O Panel common-voltage output pin VCOM 15 O Filter pin for panel common-voltage driver VCOM_PWR 16 I Internal supply input pin to VCOM buffer. Connect to the output of DCDC2. SCL 17 I Serial interface (I2C) clock input SDA 18 I/O PWR3 19 I Enable pin for CP1 (VDDH) (active high) PWR2 20 I Enable pin for LDO1 (VPOS) (active high) PWR1 21 I Enable pin for CP2 (VEE) (active high) PWR0 22 I Enable pin for LDO2 (VNEG) and VCOM (active high) PWR_GOOD 24 O Open drain power good output pin (active low) VN_SW 25 O Inverting buck-boost converter switch out (DCDC2) N/C 26 VIN_P 27 I Input power supply to inverting buck-boost converter (DCDC2) VN 28 I Feedback pin for inverting buck-boost converter (DCDC2) Serial interface (I2C) data input/output Not connected VEE_IN 29 I Input supply pin for CP1 (VEE) VEE_DRV 30 O Driver output pin for negative charge pump (CP2) VEE_D 31 O Base voltage output pin for negative charge pump (CP2) VEE_FB 32 I Feedback pin for negative charge pump (CP2) PGND2 33 VDDH_FB 34 I Feedback pin for positive charge pump (CP1) Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps VDDH_D 35 O Base voltage output pin for positive charge pump (CP1) VDDH_DRV 36 O Driver output pin for positive charge pump (CP1) VDDH_IN 37 I Input supply pin for positive charge pump (CP1) N/C 38 N/C 39 VB_SW 40 PGND3 41 Not connected Not connected O Boost converter switch out (DCDC1) Power ground for DCDC1 VB 42 I Feedback pin for boost converter (DCDC1) VPOS_IN 43 I Input pin for LDO1 (VPOS) VPOS 44 O Positive supply output pin for panel source drivers N/C 45 Not connected N/C 46 Not connected TS 47 AGND2 48 Reference point to external thermistor and linearization resistor PowerPad (PBKG) 23 Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will improve heat dissipation. PowerPad must not be connected to ground. 4 I Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor between this pin and AGND2. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT –0.3 to 7 V Ground pins to system ground –0.3 to 0.3 V Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD –0.3 to 3.6 V VCOM_XADJ –3.6 to 0.3 V Voltage on VB, VB_SW, VPOS_IN, VDDH_IN –0.3 to 20 V Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR –20 to 0.3 V Voltage from VINP to VN_SW –0.3 to 30 V Internally limited mA Input voltage range at VIN, VINP Peak output current Continuous total power dissipation 2 W qJA Junction-to-ambient thermal resistance (3) 23 °C/W TJ Operating junction temperature -10 to 125 °C -10 to 85 °C -65 to 150 °C TA Operating ambient temperature Tstg Storage temperature (4) ESD rating (1) (2) (3) (4) (HBM) Human body model ±2000 (CDM) Charged device model ±500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and 2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application. It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the buck-boost output will help heat dissipated efficiently. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Input voltage range at VIN, VINP 3 3.7 6 V Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD 0 3.6 V TA Operating ambient temperature range –10 85 °C TJ Operating junction temperature range –10 125 °C RECOMMENDED EXTERNAL COMPONENTS PART NUMBER VALUE SIZE MANUFACTURER INDUCTORS LQH44PN4R7MP0 4.7 µH 4 mm x 4 mm x 1.65 mm Murata VLS252012T-2R2M1R3 2.2 µH 2 mm x 2.5 mm x 1.2 mm TDK CAPACITORS GRM21BC81E475KA12L 4.7 µF, 25 V, X6S 805 Murata GRM32ER71H475KA88L 4.7 µF, 50 V, X7R 1210 Murata All other caps X5R or better DIODES BAS3010 SOD-323 Infineon MBR130T1 SOD-123 ON-Semi 603 Murata THERMISTOR NCP18XH103F03RB 10 KΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 5 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3 3.7 6 UNIT INPUT VOLTAGE VIN Input voltage range VUVLO Undervoltage lockout threshold VIN falling 2.9 V V VHYS Undervoltage lockout hysteresis VIN rising 400 mV mA INPUT CURRENT IQ Operating quiescent current into VIN Device switching, no load 5.5 ISTD Operating quiescent current into VIN Device in standby mode 130 ISLEEP Shutdown current Device in sleep mode 2.8 µA 10 µA INTERNAL SUPPLIES VINT_LDO1 Internal supply 2.7 V VINT_LDO2 Internal supply 2.7 V VREF Internal supply 2.25 V DCDC1 (POSITIVE BOOST REGULATOR) VIN Input voltage range 3 Output voltage range VOUT Output current RDS(ON) MOSFET on resistance -5 VIN = 3.7 V fSW Switching frequency L Inductor C Capacitor ESR Capacitor ESR 5 350 -30 % mA mΩ 1.5 Switch current accuracy V V 160 Switch current limit ILIMIT 6 17 DC set tolerance IOUT 3.7 A 30 1 % MHz 2.2 µH 2x4.7 µF 20 mΩ DCDC2 (INVERTING BUCK-BOOST REGULATOR) VIN Input voltage range 3 Output voltage range VOUT DC set tolerance IOUT Output current RDS(ON) MOSFET on resistance -5 Switch current accuracy L Inductor C Capacitor ESR Capacitor ESR 6 V 5 % V 160 VIN = 3.7 V Switch current limit ILIMIT 3.7 -17 mA 350 mΩ 1.5 A -30 30 4.7 % µH 2x4.7 µF 20 mΩ LDO1 (VPOS) VPOS_IN Input voltage range VSET Output voltage set value VINTERVAL Output voltage set resolution VPOS_OUT Output voltage range VSET = 15 V, ILOAD = 20 mA 14.85 VOUTTOL Output tolerance VSET = 15 V, ILOAD = 20 mA -1 VDROPOUT Dropout voltage VLOADREG Load regulation – DC ILOAD Load current range ILIMIT Output current limit TSS Soft start time 6 VIN = 17 V 16.15 17 17.85 V 14.25 15 15.75 V VIN = 17 V 250 15 ILOAD = 120 mA V 1 % 250 ILOAD = 10% to 90% 1 120 200 mV % mA mA 1 Submit Documentation Feedback mV 15.15 ms Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER C TEST CONDITIONS MIN Recommended output capacitor TYP MAX 4.7 UNIT µF LDO2 (VNEG) VNEG_IN Input voltage range VSET Output voltage set value VIN = –17 V -17.85 -17 -16.15 -15.75 -15 -14.25 VINTERVAL Output voltage set resolution VIN = –17 V VNEG_OUT Output voltage range VSET = –15 V, ILOAD = –20 mA -15.15 VOUTTOL Output tolerance VSET = –15 V, ILOAD = –20 mA -1 VDROPOUT Dropout voltage ILOAD = 120 mA VLOADREG Load regulation – DC ILOAD Load current range ILIMIT Output current limit TSS Soft start time C Recommended output capacitor 250 -15 V mV -14.85 V 1 % 250 ILOAD = 10% to 90% V 1 120 mV % mA 200 mA 1 ms 4.7 µF LD01 (POS) AND LDO2 (VNEG) TRACKING VDIFF Difference between VPOS and VNEG VSET = ±15 V, ILOAD = ±20 mA, 0°C to 60°C -50 50 -2.5 -0.3 mV VCOM DRIVER VCOM Output voltage range G VCOM gain (VCOM_XADJ/VCOM) VCOM_ADJ = 0 V 1 V V/V VCOM SWITCH VCOM = –1.25 V, VCOM_PANEL = 0 V CVCOM = 4.7 µF, CVCOM_PANEL = 4.7 µF TON Switch ON time 1 RDS(ON) MOSFET ON resistance VCOM = –1.25 V, ICOM = 30 mA 20 ILIMIT MOSFET current limit Not tested in production 200 ISWLEAK Switch leakage current VCOM = 0 V, VCOM_PANEL = –2.5 V 35 ms Ω mA 8.3 nA 17.85 V CP1 (VDDH) CHARGE PUMP VDDH_IN VFB Input voltage range 16.15 Feedback voltage 17 1 Accuracy -3 VSET = 22 V, ILOAD = 2 mA 21 V 3 22 % VDDH_OUT Output voltage range 23 ILOAD Load current range V 10 mA fSW Switching frequency CD Recommended driver capacitor 10 nF CO Recommended output capacitor 4.7 µF 560 KHz CP2 (VEE) NEGATIVE CHARGE PUMP VEE_IN VFB Input voltage range -17.75 Feedback voltage -17 -16.15 V 3 % -1 Accuracy -3 VSET = –20 V, ILOAD = 3 mA -21 -20 V VEE_OUT Output voltage range ILOAD Load current range -19 V 12 mA fSW Switching frequency CD Recommended driver capacitor 10 nF CO Recommended output capacitor 4.7 µF 560 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B KHz 7 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMISTOR MONITOR (1) ATMS Temperature to voltage ratio OffsetTMS Offset VTMS_HOT Temp hot trip voltage (T = 50°C) Not tested in production VTMS_COOL Temp hot escape voltage (T = 45°C) -0.0158 V/°C Temperature = 0°C 1.575 V TEMP_HOT_SET = 0x8C 0.768 V TEMP_COOL_SET = 0x82 0.845 V VTMS_MAX Maximum input level RNTC_PU Internal pull up resistor RLINEAR External linearization resistor ADCRES ADC resolution ADCDEL ADC conversion time Not tested in production TMSTTOL Accuracy Not tested in production Not tested in production, 1 bit 2.25 V 7.307 KΩ 43 KΩ 16.1 mV 19 -1 µs 1 LSB LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP) VOL Output low threshold level VIL Input low threshold level VIH Input high threshold level I(bias) Input bias current tlow,WAKEUP WAKEUP low time fSCL IO = 3 mA, sink current (SDA, PWR_GOOD) 0.4 V 0.4 V 1 µA 1.2 V VIO = 1.8 V minimum low time for WAKEUP pin 150 ms SCL clock frequency 400 KHz OSCILLATOR fOSC Oscillator frequency Frequency accuracy 9 TA = –40°C to 85°C -10 MHz 10 % THERMAL SHUTDOWN TSHTDWN Thermal trip point Thermal hysteresis (1) 8 150 °C 20 °C 10-KΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 KΩ, 1%) are used at TS pin for panel temperature measurement. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 MODES OF OPERATION The TPS65182/TPS65182B has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode one or more power rails are enabled. SLEEP This is the lowest power mode of operation. All internal circuitry is turned off and the device does not respond to I2C communications. TPS65182/TPS65182B enters SLEEP mode whenever WAKEUP pin is pulled low. STANDBY In STANDBY all internal support circuitry is powered up and the device is ready to accept commands either through GPIO or I2C control but none of the power rails are enabled. To enter STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be pulled low. The device also enters STANDBY mode if input under voltage lock out (UVLO), positive boost under voltage (VB_UV), or inverting buck-boost under voltage (VN_UV) is detected, or thermal shutdown occurs. ACTIVE The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is the normal mode of operation while the device is powered up. In ACTIVE mode, a falling edge on any PWRx pin shuts down and a rising edge powers up the corresponding rail. MODE TRANSISITONS SLEEP → ACTIVE WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in a pre-defined power-up sequence. SLEEP → STANDBY WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails will remain down until one or more PWRx pin is pulled high. ACTIVE → SLEEP WAKEUP pin is pulled low (falling edge). Rails are shut down following the pre-defined power-down sequence. ACTIVE → STANDBY WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), under voltage lock out (UVLO), positive boost or inverting buck-boost under voltage (UV), the device shuts down all rails in a pre-defined power-down sequence. STANDBY → ACTIVE WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the same order as PWRx pins are pulled high. STANDBY → SLEEP WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 9 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com POWER DOWN Battery removed All rails I2 C WAKEUP (¯) (* ) WAKEUP () & any P WRx pin = high (*) SLEEP WAKEUP WAKEUP ( ) & All PWRx pins = low (¯ ) All rails I2 C STANDBY WAKEUP all PWRx pins = high & (**) = ( ¯) || (**) FAULT ) (*) (**) = = = = = = OFF = YES WAKEUP = high & (**) any PWRx pin ( ) ) Rails I2 C ACTIVE NOTES : ||, & ( ), ( ¯ ) FAULT = OFF = NO logic OR , logic AND . rising edge , falling edge . UVLO || TSD ( thermal shutdown )|| BOOST UV Device follows default power - up /down sequence Power sequencing is GPIO controlled . = ON = YES . . Figure 1. Global State Diagram WAKE-UP AND POWER UP SEQUENCING The TPS65182/TPS65182B supports a default power-up sequence supporting E Ink® Vizplex™ displays. It also offers full user control of the power-up sequence through GPIO control using the PWR3, 2, 1, 0 pins. Using GPIO control, the output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted, respectively, and the power-up timing is controlled by the host only. Rails are in regulation 2 ms after their respective PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power up. The additional time is needed to power up the positive and inverting buck-boost regulator which need to be turned on before any other rail can be enabled. Once all rails are enabled and in regulation the PWR_GOOD pin is released (pin status = HiZ and power good line is pulled high by external pull-up resistor). The PWRx pins are assigned to the rails as follows: • PWR0: LDO2 (VNEG) and VCOM • PWR1: CP2 (VEE) • PWR3: LDO2 (VPOS) • PWR4: CP1 (VDDH) Rails are powered down whenever the host de-asserts the respective PWRx pin, and once all rails are disabled the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode which is the lowest-power mode of operation. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 It is possible for the host to force the TPS65182/TPS65182B directly into SLEEP mode from ACTIVE mode by de-asserting the WAKEUP pin in which case the device follows the pre-defined power-down sequence before entering SLEEP mode. DEPENDENCIES BETWEEN RAILS Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. These dependencies are listed below. 1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled. Internally, DCDC1 enable is gated by DCDC2 power good. 2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable is gated DCDC1 power-good. 3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is gated by DCDC1 power good. 4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally CP2 enable is gated by DCDC1 power good. 5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally CP1 enable is gated by DCDC1 power good. 6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power good. 7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) rails will be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding rail. In this case, the default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and CP1(VDDH). If any two PWRx pins are pulled low then all rails will go down at the same time. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 11 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com VIN PWR0 PWR1 D0 1.8ms (1) D1 PWR2 D2 PWR3 D3 WAKEUP SLEEP STANDBY ACTIVE ACTIVE VN VB VNEG DLY 1 VCOM 6ms (2,5) DLY 2 DLY 0 + 4ms (2) VEE 1ms (5) DLY 3 DLY 1 VPOS 2ms (5) DLY 2 DLY 0 VDDH 1ms (5) DLY 3 PWR_GOOD 300 us (max) 11 .8ms (min) (1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction . (2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled . (5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled. DLY 0-DLY 3 are power up /down delays are factory -set to 2ms. Figure 2. Power-Up and Power-Down Timing Diagram SOFTSTART Softstart for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the device enters STANDBY mode. VCOM ADJUSTMENT VCOM can be adjusted by an external potentiometer by connecting a potentiometer to the VCOM_XADJ pin. The potentiometer must be connected between ground and a negative supply. The gain from VCOM_XADJ to VCOM is 1 and therefore the voltage applied to VCOM_XADJ pin should range from -0.3 to -2.5V. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 VPOS / VNEG SUPPLY TRACKING LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV. FAULT HANDLING AND RECOVERY The TPS65182/TPS65182B monitors input and output voltages and die temperature and will take action if operating conditions are outside normal limits. Whenever the TPS65182/TPS65182B encounters: • Thermal Shutdown (TSD) • Positive Boost Under Voltage (VB_UV) • Inverting Buck-Boost Under Voltage (VN_UV) • Input Under Voltage Lock Out (UVLO) it will shut down all power rails and enter STANDBY mode. Shut down follows the pre-defined power-down sequence and once a fault is detected, the PWR_GOOD pin is pulled low. Whenver the TPS65182/TPS65182B encounters under voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail (plus any dependent rail) only and remain in ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD pin will be pulled low. As the PWRx inputs are edge sensitive, the host must toggle the PWRx pins to re-enable the rails through GPIO control, i.e. it must bring the PWRx pins low before asserting them again. POWER GOOD PIN The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor). PANEL TEMPERATURE MONITORING The TPS65182/TPS65182B provides circuitry to bias and measure an external negative temperature coefficient resistor (NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature reading is automatically updated every 60 s. NTC BIAS CIRCUIT Figure 3 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-KΩ bias resistor. A 43-KΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-KΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 13 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com Table 1. ADC Output Value vs Termperature TEMPERATURE TMST_VALUE[7:0] < -10°C 1111 0110 -10°C 1111 0110 -9°C 1111 0111 ... ... -2°C 1111 1110 -1°C 1111 1111 0°C 0000 0000 1°C 0000 0001 2°C 0000 0010 ... ... 25°C 0001 1001 ... 85°C 0101 0101 > 85°C 0101 0101 2.25V 7.307 kW 10 Digital 10 bit ADC 43 kW 10 kW NTC TPS6518x Figure 3. NTC Bias and Measurement Circuit I2C BUS OPERATION The TPS65182/TPS65182B supports a special I2C mode making it compatible with the EPSON® Broadsheet S1D13521 timing controller. Standard I2C protocol requires the following steps to read data from a register: 1. Send device slave address, R/nW bit set low (write command) 2. Send register address 3. Send device slave address, R/nW set high (read command) 4. The slave will respond with data from the specified register address.end device slave address, R/nW set high (read command). The EPSON® Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed registers, therefore the TPS65182/TPS65182B I2C interface has been modified and the reading the temperature data is reduced to two steps: 1. Send device address, R/nW set high (read command) 2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 S SLAVE ADDRESS R A DATA 0 A P From master to slave R Read S Start From slave to master A Acknowlege P Stop Figure 4. Subaddress in I2C Transmission The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open Drain output to transmit data on the serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. Data transmission is initiated with a start bit from the controller as shown in Figure 5. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the appropriate group and address bits are set for the device, then the device will issue an acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as per the Register Map section of this document. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. Reference Figure 5. SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 S START P ADDRESS R/W ACK DATA ACK DATA ACK/ nACK STOP Figure 5. I2C Start/Stop/Acknowledge Protocol SDA tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA S tHD;DAT tHIGH tSU;STA tSU;STO Sr tf P S Figure 6. I2C Data Transmission Timing Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 15 TPS65182, TPS65182B SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 www.ti.com DATA TRANSMISSION TIMING VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) PARAMETER TEST CONDITIONS f(SCL) Serial clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock tSU;STA TYP 100 Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data set-up time tr Rise time of both SDA and SCL signals tf Fall time of both SDA and SCL signals tSU;STO Set-up time for STOP condition tBUF Bus Free Time Between Stop and Start Condition tSP Pulse width of spikes which mst be suppressed by the input filter Cb Capacitive load for each bus line 16 MIN MAX 400 UNIT KHz SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 4.7 SCL = 400 KHz 1.3 µs SCL = 100 KHz 4 SCL = 400 KHz 600 µs ns SCL = 100 KHz 4.7 µs SCL = 400 KHz 600 SCL = 100 KHz 0 3.45 µs SCL = 400 KHz 0 900 ns SCL = 100 KHz 250 SCL = 400 KHz 100 ns ns SCL = 100 KHz 1000 SCL = 400 KHz 300 SCL = 100 KHz 300 SCL = 400 KHz 300 ns ns SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 4.7 SCL = 400 KHz 1.3 SCL = 100 KHz n/a n/a SCL = 400 KHz 0 50 µs SCL = 100 KHz 400 SCL = 400 KHz 400 Submit Documentation Feedback ns pF Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B TPS65182, TPS65182B www.ti.com SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010 REGISTER ADDRESS MAP REGISTER ADDRESS (HEX) NAME DEFAULT VALUE DESCRIPTION 0 0x00 TMST_VALUE N/A Thermistor value read by ADC THERMISTOR READOUT (TMST_VALUE) Address – 0x00h DATA BIT D7 D6 D5 READ/WRITE R R R R R R R R RESET VALUE N/A N/A N/A N/A N/A N/A N/A N/A FIELD NAME D4 D3 D2 D1 D0 TMST_VALUE[7:0] FIELD NAME BIT DEFINITION Temperature read-out 1111 0110 – < -10°C 1111 0110 – -10°C 1111 0111 – -9°C ... 1111 1110 – -2°C 1111 1111 – -1 °C TMST_VALUE[7:0] 0000 0000 – 0 °C 0000 0001 – 1°C 0000 0010 – 2°C ... 0001 1001 – 25°C ... 0101 0101 – 85°C 0101 0101 – > 85°C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65182 TPS65182B 17 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS65182BRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS65182BRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS65182RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS65182RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS65182BRGZR VQFN RGZ 48 TPS65182BRGZT VQFN RGZ TPS65182RGZR VQFN RGZ TPS65182RGZT VQFN RGZ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65182BRGZR VQFN RGZ 48 2500 346.0 346.0 33.0 TPS65182BRGZT VQFN RGZ 48 250 190.5 212.7 31.8 TPS65182RGZR VQFN RGZ 48 2500 346.0 346.0 33.0 TPS65182RGZT VQFN RGZ 48 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee® Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated