LTC3111 15V, 1.5A Synchronous Buck-Boost DC/DC Converter DESCRIPTION FEATURES Regulated Output with VIN Above, Below or Equal to VOUT n2.5V to 15V Input and Output Voltage Range n1.5A Continuous Output Current: V ≥ 5V, IN VOUT = 5V, PWM Mode n Single Inductor n Accurate RUN Threshold n Up to 95% Efficiency n800kHz Switching Frequency, Synchronizable Between 600kHz and 1.5MHz n49µA No-Load Quiescent Current in Burst Mode® Operation n Output Disconnect in Shutdown n Shutdown Current < 1µA n Internal Soft-Start n Small, Thermally Enhanced 14-Lead (3mm × 4mm × 0.75mm) DFN and 16-Lead MSOP Packages The LTC®3111 is a fixed frequency, synchronous buckboost DC/DC converter with an extended input and output range. The unique 4-switch, single inductor architecture provides low noise and seamless operation from input voltages above, below or equal to the output voltage. n With an input and output range of 2.5V to 15V, the LTC3111 is well suited for a wide variety of single or multiple-cell batteries, back-up capacitor or wall adapter source applications. Low RDS(ON) internal N-channel MOSFET switches and selectable PWM or Burst Mode operation produce high efficiency over a wide range of operating conditions. An accurate RUN pin allows the user to program the turn-on threshold voltage of the converter. Other features include: short-circuit protection, internal soft-start and thermal shutdown. The LTC3111 is offered in both thermally enhanced 14-lead (3mm × 4mm × 0.75mm) DFN and 16-lead MSOP packages. APPLICATIONS 3.3V or 5V from 1, 2 or 3 Li-Ion, Multiple-Cell Alkaline/NiMH Batteries n RF Transmitters n Military, Industrial Power Systems n L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, LTspice are registered trademarks and No RSENSE and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6404251, 6166527, 5481178, 6304066, 6580258. TYPICAL APPLICATION 5V, 800kHz Wide Input Voltage Buck-Boost Regulator Efficiency at 5VOUT 100 4.7µH VIN 2.5V TO 15V SW1 SW2 BST1 BST2 VIN 10µF VOUT LTC3111 0.1µF 680pF COMP BURST PWM OFF ON PWM/SYNC 1M 20k 33pF 27pF RUN SNSGND SGND 26.1k VOUT 5V 1.5A 22µF (VIN > 5V) PGND 1µF BURST 70 60 50 FB VCC 80 EFFICIENCY (%) 0.1µF PWM 90 191k 3111 TA01a VIN = 2.7V VIN = 5V VIN = 12V 40 30 0.0001 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 3111 TA01b 3111fa For more information www.linear.com/LTC3111 1 LTC3111 ABSOLUTE MAXIMUM RATINGS (Notes 1, 3) VIN Voltage.................................................. –0.3V to 16V VOUT Voltage............................................... –0.3V to 16V SW1 Voltage (Note 4).................... –0.3V to (VIN + 0.3V) SW2 Voltage (Note 4)..................–0.3V to (VOUT + 0.3V) BST1 Voltage.................... (VSW1 – 0.3V) to (VSW1 + 6V) BST2 Voltage....................(VSW2 – 0.3V) to (VSW2 + 6V) RUN Voltage............................................... –0.3V to 16V PWM/SYNC, VCC Voltage.............................. –0.3V to 6V FB, COMP, Voltage........................................ –0.3V to 6V Operating Junction Temperature Range (Notes 2, 5) LTC3111E, LTC3111I............................ –40°C to 125°C LTC3111H............................................ –40°C to 150°C LTC3111MP......................................... –55°C to 150°C Maximum Junction Temperature (Note 3)............. 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10sec) MSOP................................................................ 300°C PIN CONFIGURATION TOP VIEW TOP VIEW COMP 1 14 SGND FB 2 13 PWM/SYNC SNSGND 3 RUN 4 15 PGND COMP FB SNSGND RUN VIN SW1 BST1 PGND 12 VCC 11 NC VIN 5 SW1 6 10 VOUT 9 SW2 BST1 7 8 BST2 1 2 3 4 5 6 7 8 17 PGND 16 15 14 13 12 11 10 9 SGND PWM/SYNC VCC NC VOUT SW2 BST2 PGND MSE PACKAGE 16-LEAD PLASTIC MSOP DE PACKAGE 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W, θJC = 5°C/W EXPOSED PAD (PIN 15) IS PGND, MUST BE SOLDERED TO PCB TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3111EDE#PBF LTC3111EDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LTC3111IDE#PBF LTC3111IDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LTC3111HDE#PBF LTC3111HDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 150°C LTC3111MPDE#PBF LTC3111MPDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –55°C to 150°C LTC3111EMSE#PBF LTC3111EMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C LTC3111IMSE#PBF LTC3111IMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C LTC3111HMSE#PBF LTC3111HMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 150°C LTC3111MPMSE#PBF LTC3111MPMSE#TRPBF 3111 16-Lead Plastic MSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3111fa 2 For more information www.linear.com/LTC3111 LTC3111 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = PWM/SYNC = RUN = 5V unless otherwise noted. PARAMETER CONDITION MIN Input Operating Range VIN UVLO Threshold Rising l 2.5 l 1.9 VIN UVLO Hysteresis VCC UVLO Threshold TYP MAX 15 2.1 2.3 200 Rising l 2.2 VCC UVLO Hysteresis 2.35 INTVCC Clamp Voltage VIN = 5V or 15V Quiescent Current—Burst Mode Operation FB = 1V, PWM/SYNC = 0V Quiescent Current—Shutdown RUN = VOUT = VCC = 0V, Not Including Switch Leakage Feedback Voltage PWM Operation Feedback Leakage FB = 0.8V NMOS Switch Leakage NMOS Switch On-Resistance l 2.5 l 3.9 V V mV 2.5 190 Output Voltage Adjust Range UNITS V mV 15 V 4.2 4.5 V 55 80 µA 0 1 µA 0.8 0.82 V 0 50 nA Switches A, B, C, D, VIN = VOUT = 15V 0.5 5 Switch A 90 mΩ 105 mΩ l 0.78 Switch B, C, D Input Current Limit l 2.3 Peak Current Limit 3 3.7 µA A 5.8 A Burst Current Limit PWM/SYNC = 0V 0.8 A Burst Zero Current Threshold PWM/SYNC = 0V 0.1 A –1 A 90 % Reverse Current Limit Maximum Duty Cycle Percentage of the Period SW2 is Low in Boost Mode (Note 7) l Minimum Duty Cycle Percentage of the Period SW1 is Low in Buck Mode (Note 7) l SW1, SW2 Minimum Low Time (Note 7) Frequency SYNC Frequency Range 85 0 160 PWM/SYNC = 5V l 700 (Note 6) l 600 800 % ns 900 kHz 1500 kHz l 0.5 0.9 1.5 V RUN Threshold to Enable VCC Rising l 0.35 0.8 1.15 V RUN Threshold to Disable VCC Falling l 0.3 RUN Threshold to Enable Switching Rising l 1.15 PWM/SYNC Threshold RUN Hysteresis V 1.18 120 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetimes. Note 2: The LTC3111 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3111E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3111I is guaranteed to meet performance specifications from –40°C 1.23 V mV to 125°C junction temperature, the LTC3111H is guaranteed to meet performance specifications from –40°C to 150°C junction temperature and the LTC3111MP is guaranteed and tested to meet performance specifications from –55°C to 150°C junction temperature. High junction temperatures degrade operating lifetimes: operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 3111fa For more information www.linear.com/LTC3111 3 LTC3111 ELECTRICAL CHARACTERISTICS Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Voltage transients on the switch pins beyond the DC limit specified in the Absolute Maximum Ratings, are non-disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. Note 5: The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance. Note 6: SYNC frequency range is tested with a square wave. Operation with 100ns minimum high or low time is assured by design. Note 7: Switch timing measurements are made in an open-loop test configuration. Timing in the application may vary somewhat from these values due to differences in the switch pin voltage during the non-overlap durations when the switch pin voltage is influenced by the magnitude and direction of the inductor current. TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified Maximum Output Current in PWM Mode vs VIN Maximum Load Current in Burst Mode Operation vs VIN 2.0 1.4 1.2 1.0 0.8 0.6 INPUT CURRENT LIMIT = 2.3A VOUT = 3.3V, L = 4.7µH VOUT = 5V, L = 6.8µH VOUT = 12V, L = 10µH 0.4 0.2 0 600 400 300 90 80 EFFICIENCY (%) POWER LOSS (W) 0.0001 0.0001 0.01 0.1 LOAD CURRENT (A) 1 VIN = 2.7V VIN = 5V VIN = 12V 3111 G04 0.01 0.1 LOAD CURRENT (A) 10 3111 G03 10 1 BURST 70 60 30 0.0001 1 PWM PWM 0.1 0.01 BURST 0.001 40 10 0.001 Wide VIN to 3.3VOUT Power Loss 50 VIN = 2.7V VIN = 5V VIN = 12V 0.001 30 0.0001 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) Wide VIN to 3.3VOUT Efficiency 1 0.001 VIN = 2.7V VIN = 5V VIN = 12V 40 100 100 BURST 60 50 200 Wide VIN to 5VOUT Power Loss 0.01 70 3111 G02 10 0.1 BURST 80 3111 G01 PWM PWM 90 500 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) VOUT = 3.3V VOUT = 5V VOUT = 12V 700 EFFICIENCY (%) 1.6 Wide VIN to 5VOUT Efficiency 100 POWER LOSS (W) MAXIMUM OUTPUT CURRENT (A) 1.8 MAXIMUM OUTPUT CURRENT (mA) 800 0.01 0.1 0.001 LOAD CURRENT (A) 1 3111 G05 0.0001 0.0001 VIN = 2.7V VIN = 5V VIN = 12V 0.001 0.01 0.1 LOAD CURRENT (A) 1 3111 G06 3111fa 4 For more information www.linear.com/LTC3111 LTC3111 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified Wide VIN to 12VOUT Efficiency 10 PWM 90 BURST PWM 60 50 VIN = 2.7V VIN = 5V VIN = 12V 0.01 0.1 0.001 LOAD CURRENT (A) 1 90 80 POWER LOSS (W) EFFICIENCY (%) 70 30 0.0001 100 1 80 40 Wide VIN to 12VOUT Power Loss EFFICIENCY (%) 100 0.1 BURST 0.01 0.0001 0.0001 VIN = 2.7V VIN = 5V VIN = 12V 0.001 0.01 0.1 LOAD CURRENT (A) 1 450 400 16 350 6 50 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) 4.1 150 0 VCC FROM VIN 3.6 0 10 20 30 40 50 60 CURRENT FROM VCC (mA) 70 80 3111 G13 VCC (V) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) 3111 G12 Normalized N-Channel MOSFET Resistance vs Temperature 1.6 1.25 NORMALIZED MOSFET RESISTANCE NORMALIZED MOSFET RESISTANCE 3.7 3.1 2.5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) 1.30 3.8 3.3 2.7 VCC FROM VOUT Normalized N-Channel MOSFET Resistance vs VCC 3.9 3.7 3.5 3111 G11 VCC Voltage vs VCC Current 4.0 3.9 2.9 31111 G10 3.5 VCC Voltage vs VIN PWM Mode No Load 4.5 200 2 1 4.3 250 100 4.1 0.1 LOAD CURRENT (A) 3111 G09 VOUT = 5V 300 4 4.2 30 0.01 10 VCC VOLTAGE (V) VIN CURRENT (µA) VIN CURRENT (mA) 20 8 f = 600kHz f = 800kHz f = 1MHz f = 1.5MHz 40 Burst Mode No-Load Current with VCC from VIN or Back-Fed from VOUT with an Optional Diode 18 10 60 3111 G08 800kHz PWM Mode No-Load Input Current 12 70 50 0.001 3111 G07 14 12VIN to 12VOUT Efficiency at f = 600kHz, 800kHz, 1MHz and 1.5MHz with L = 10µH 1.20 1.15 1.10 1.05 1.00 0.95 0.90 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 3111 G14 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 –50 0 50 100 TEMPERATURE (°C) 150 3111 G15 3111fa For more information www.linear.com/LTC3111 5 LTC3111 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified VCC and VIN UVLO Voltage Thresholds vs Temperature Feedback Pin Program Voltage vs Temperature 800.0 799.5 799.0 798.5 798.0 797.5 797.0 0 50 100 TEMPERATURE (°C) 1.00 2.3 0.95 VCC UVLO RISING 2.2 VCC UVLO FALLING 2.1 2.0 VIN UVLO RISING 1.9 VIN UVLO FALLING 1.8 1.7 1.6 1.5 –50 150 0 50 3111 G16 0.90 0.85 0.80 0.75 RISING FALLING 0.70 0.65 0.60 0.55 0.50 –50 0 50 100 TEMPERATURE (°C) 150 1.30 1.25 RISING 1.20 1.15 1.10 FALLING 1.05 1.00 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) PWM Mode Input, Peak and Reverse Current Limits vs Temperature ILMIT, IPEAK, AND IREVERSE (A) ILIMIT, IPEAK AND IREVERSE (A) 0.9 INPUT CURRENT LIMIT 2 1 0 –2 –50 0.65 0.60 0.55 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VIN (V) RUN Threshold to Enable/Disable Switching vs Temperature 1.30 1.25 RISING 1.20 1.15 1.10 FALLING 1.05 1.00 –50 0 100 50 TEMPERATURE (°C) 150 3111 G21 1.0 PEAK CURRENT LIMIT 4 –1 0.70 Burst Mode Peak Current, IZERO Limits vs Temperature 6 3 FALLING 0.75 3111 G20 3111 G19 5 0.80 3111 G18 RUN Threshold to Enable/Disable Switching vs VIN RUN Threshold to Enable/Disable VCC vs Temperature 0.95 RISING 3111 G17 RUN THRESHOLD TO ENABLE SWITCHING (V) RUN THRESHOLDS TO ENABLE VCC (V) 1.00 0.90 0.85 0.50 150 100 TEMPERATURE (°C) RUN PIN THRESHOLD TO ENABLE SWITCHING (V) 796.5 –50 2.4 RUN THRESHOLD TO ENABLE VCC (V) VCC AND VIN UVLO THRESHOLDS (V) FEEDBACK PIN PROGRAM VOLTAGE (mV) 800.5 RUN Threshold to Enable/Disable VCC vs VIN REVERSE CURRENT LIMIT 0 50 100 TEMPERATURE (°C) PEAK CURRENT LIMIT 0.8 0.7 0.6 0.5 0.4 0.3 0.2 IZERO 0.1 150 0 –50 3111 G22 0 50 100 TEMPERATURE (°C) 150 3111 G23 3111fa 6 For more information www.linear.com/LTC3111 LTC3111 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified 3VIN to 5VOUT 0.05A to 0.25A Load Response 5VIN to 5VOUT 0.05A to 0.5A Load Response 12VIN to 5VOUT 0.05A to 0.5A Load Response VOUT 200mV/DIV VOUT 200mV/DIV INDUCTOR CURRENT 500mA/DIV LOAD CURRENT 200mA/DIV VOUT 500mV/DIV INDUCTOR CURRENT 500mA/DIV INDUCTOR CURRENT 1A/DIV LOAD CURRENT 500mA/DIV LOAD CURRENT 500mA/DIV 500µs/DIV FRONT PAGE APPLICATION 3111 G24 500µs/DIV FRONT PAGE APPLICATION 5VIN to 5VOUT Burst to PWM Response 12VIN to 5VOUT Burst Mode VOUT Ripple VOUT 200mV/DIV VOUT 200mV/DIV INDUCTOR CURRENT 500mA/DIV ILOAD = 10mA L = 4.7µH COUT = 22µF 500µs/DIV 7.5VIN to 5VOUT Start-Up Response 20µs/DIV 1.5MHz SYNC Signal Capture and Release RUN 5V/DIV 3111 G29 12VIN to 5VOUT SW1 and SW2 Waveforms SW1 10V/DIV INDUCTOR CURRENT 500mA/DIV INDUCTOR CURRENT 500mA/DIV 3111 G30 1µs/DIV SW2 5V/DIV PWM/SYNC 5V/DIV VOUT 2V/DIV INDUCTOR CURRENT 1A/DIV 500µs/DIV ILOAD = 500mA L = 4.7µH COUT = 22µF 3111 G28 VOUT 200mV/DIV ILOAD = 500mA L = 4.7µH COUT = 22µF 12VIN to 5VOUT PWM VOUT Ripple INDUCTOR CURRENT 500mA/DIV ILOAD = 50mA L = 4.7µH COUT = 22µF 3111 G27 3111 G26 VOUT 50mV/DIV PWM/SYNC 5V/DIV INDUCTOR CURRENT 500mA/DIV 500µs/DIV FRONT PAGE APPLICATION 3111 G25 100µs/DIV 3111 G31 1µs/DIV 3111 G32 3111fa For more information www.linear.com/LTC3111 7 LTC3111 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified VOUT Short-Circuit Response and Recovery 3.3VOUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C VCC Short-Circuit Response and Recovery 50 VCC 5V/DIV 45 SOFT-START VOUT 2V/DIV INDUCTOR CURRENT 1A/DIV 1ms/DIV INDUCTOR CURRENT 1A/DIV 3111 G33 DIE TEMPERATURE RISE (°C) VOUT 2V/DIV 1ms/DIV 3111 G34 VIN = 2.7V 40 VIN = 12V 35 30 25 VIN = 5V 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 3111 G35 5VOUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C 12VOUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C 60 80 DIE TEMPERATURE (°C) DIE TEMPERATURE RISE (°C) 70 50 VIN = 12V 40 VIN = 2.7V 30 VIN = 5V 20 10 0 60 50 VIN = 12V 40 VIN = 2.7V VIN = 5V 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 0 3111 G37 3111 G36 SW1, SW2 Minimum Low Time vs Temperature SW1, SW2 Minimum Low Time vs VCC 250 ILOAD = 300mA SW1, SW2 MINIMUM LOW TIME (ns) SW1, SW2 MINIMUM LOW TIME (ns) 300 250 SW1, VIN = 4V 200 150 SW2, VIN = 6V 100 50 0 2 2.5 3 3.5 VCC (V) 4 4.5 5 230 ILOAD = 300mA 210 SW1, VIN = 4V 190 SW2, VIN = 6V 170 150 130 110 90 70 50 –50 3111 G38 0 50 100 TEMPERATURE (°C) 150 3111 G39 3111fa 8 For more information www.linear.com/LTC3111 LTC3111 PIN FUNCTIONS (DFN/MSOP) COMP (Pin 1/Pin 1): Error Amp Output. An R-C network connected from this pin to FB sets the loop compensation for the voltage converter. Refer to the Applications Information section for component selection details. FB (Pin 2/Pin 2): Feedback Voltage Input. Connect the VOUT resistor divider tap to this pin. The output voltage can be adjusted from 2.5V to 15V by the following equation: R1 VOUT = 0.8V • 1+ R2 where R1 is the resistor between VOUT and FB and R2 is the resistor between FB and GND SNSGND (Pin 3/Pin 3): This pin must be connected to ground. RUN (Pin 4/Pin 4): Input to Enable or Disable the IC and Set Custom Input Undervoltage Lockout (UVLO) Thresholds. The RUN pin can be driven by an external logic signal to enable and disable the IC. In addition, the voltage on this pin can be set by a resistive voltage divider connected to the input supply in order to provide accurate turn-on and turn-off (UVLO) thresholds determined by: R5 VIN(RUN) = 1.2V • 1+ R6 The IC is enabled if RUN exceeds 1.2V nominally. Once enabled, the UVLO threshold has a built-in hysteresis of approximately 120mV, turn-off will occur when the voltage on RUN drops to below 1.08V nominally. To continuously enable the IC, RUN can be tied directly to the input voltage up to the absolute maximum rating. This pin should not be left unconnected. VIN (Pin 5/Pin 5): Input Supply Voltage. This pin should be bypassed to the ground plane with at least 10µF of low ESR, low ESL ceramic capacitance. Place this capacitor as close to the pin as possible and provide as short a return path to the ground plane as possible. SW1 (Pin 6/Pin 6): The external inductor and internal switches A and B are connected here. BST1 (Pin 7/Pin 7): Boosted Floating Driver Supply for A-Switch Driver. Connect a 0.1µF capacitor from this pin to SW1. BST2 (Pin 8/Pin 10): Boosted Floating Driver Supply for D-Switch Driver. Connect a 0.1µF capacitor from this pin to SW2. SW2 (Pin 9/Pin 11): The external inductor and internal switches C and D are connected here. VOUT (Pin 10/Pin 12): Regulated Output Voltage. This pin should be connected to a low ESR ceramic capacitor. The capacitor should be placed as close to the pin as possible and have a short return to the ground plane. NC (Pin 11/Pin 13): Not Connected. This pin should be connected to ground. VCC (Pin 12/Pin 14): External Capacitor Connection for the Regulated VCC Supply. This supply is used to operate internal circuitry and switch drivers. VCC will track VIN up to 4.2V typical, but will maintain this voltage when VIN > 4.2V. Connect a 1µF ceramic capacitor from this pin to GND. This pin can be tied to an external supply up to 5.5V. Refer to the Operation section of this data sheet under Power VCC from an External Source for more details. PWM/SYNC (Pin 13/Pin 15): Burst Mode Control and Synchronization Input. A DC voltage < 0.5V commands Burst Mode operation independent of load current, >1.5V commands 800kHz fixed frequency mode. A digital pulse train between 600kHz and 1.5MHz applied to this pin will override the internal oscillator and set the operating frequency. The pulse train should have a minimum high time or low time greater than 100ns (Note 6). Note the LTC3111 has reduced power capability when operating in Burst Mode operation. This pin should not be left unconnected. SGND (Pin 14/Pin 16): Signal Ground. Terminate the RUN input voltage divider and output voltage divider to SGND. PGND (Exposed Pad Pin 15/Pin 8, 9, Exposed Pad Pin 17) Power Ground. The exposed pad must be soldered to the PCB and electrically connected to ground through the shortest and lowest impedance connection possible. 3111fa For more information www.linear.com/LTC3111 9 LTC3111 SIMPLIFIED BLOCK DIAGRAM 4.7µH BST1 VIN SW1 SW2 VOUT BST2 VCC CIN VCC COUT DDRV ADRV VCC VCC BDRV CDRV GND GND ADRV BDRV CDRV DDRV DRIVERS RUN STOP VCC + – IPEAK 5.8A ILIMIT 3A + – 1.2V + – 0.8V + – 2.1V + – 2.35V + – VIN IZERO LOGIC VCC + – START VIN UVLO VCC UVLO –1A + – VIN VOUT + + – RUN REVERSE ILIM + – 0.1A – + VCC ÷ ERROR AMP START REFERENCE 1.2V SOFT-START RAMP COMP 800k OSCILLATOR PLL PWM/SYNC Burst Mode OPERATION 4.2V REGULATOR/ CLAMP FB 0.8V 3111 BD 3111fa 10 For more information www.linear.com/LTC3111 LTC3111 OPERATION INTRODUCTION VOUT The LTC3111 is an extended input and output range, synchronous 1.5A buck-boost DC/DC converter optimized for a variety of applications. The LTC3111 utilizes a proprietary switching algorithm, which allows its output voltage to be regulated above, below or equal to the input voltage. The error amplifier output on COMP determines the output duty cycle of the switches. The low RDS(ON), low gate charge synchronous switches provide high efficiency pulse width modulation control. High efficiency is achieved at light loads when Burst Mode operation is commanded. LTC3111 R1 RFF 0.8V FB CFF R2 RFB CFB VIN VOUT + – ÷ PWM COMPARATORS SW1 SW2 COMP CPOLE SGND 3111 F01 Figure 1. Error Amplifier and Compensation Network LOW NOISE FIXED FREQUENCY OPERATION on designing the compensation network for the LTC3111 applications can be found in the Applications Information section of this data sheet. Oscillator, Phase Lock Loop Current Limit Operation An internal oscillator circuit sets the normal frequency of operation to 800kHz. A pulse train applied to the PWM/ SYNC pin allows the operating frequency to be programmed between 600kHz to 1.5MHz via an internal phase-lock-loop circuit. The pulse train must have a minimum high or low state of at least 100ns to guarantee operation (see Note 6 of the Electrical Characteristics). The buck-boost converter has two current limit circuits. The input current limit sources current into the feedback divider network whenever the current in switch A exceeds 3A typical. Due to the high gain of the feedback loop, the injected current forces the error amplifier output to decrease until the average current through switch A decreases approximately to the current limit value. The input current limit utilizes the error amplifier in an active state and thereby provides a smooth recovery with little overshoot once the current limit fault condition is removed. Since the current limit is based on the average current through switch A, the peak inductor current in current limit will have a dependency on the duty cycle (i.e., on the input and output voltages) in the overcurrent condition. For this current limit feature to be most effective, the Thevenin resistance from the FB to ground should exceed 100kΩ. Error Amplifier The LTC3111 contains a high gain operational amplifier which provides frequency compensation of the control loop to maintain output voltage regulation. To ensure loop stability, an external compensation network must be installed in the application circuit. A Type III compensation network, as shown in Figure 1, is recommended for most applications since it provides the flexibility to optimize the converter’s transient response while simultaneously minimizing any DC error in the output voltage. As shown in Figure 1, the error amplifier is followed by an internal analog divider which adjusts the loop gain by the reciprocal of the input voltage when the converter is in buck mode and by the output voltage when the converter is in boost mode which minimizes loop-gain variation over changes in the input voltage. This simplifies design of the compensation network and optimizes the transient response over the entire range of input voltages. Details The speed of the input current limit circuit is limited by the dynamics of the converter loop. On a hard output short, it is possible for the inductor current to increase substantially beyond the input current limit before the input current limit circuit can react. For this reason, there is a peak current limit circuit which turns off switch A if the current in switch A exceeds approximately 190% of the input current limit value. This provides additional protection in the case of an instantaneous hard output short. 3111fa For more information www.linear.com/LTC3111 11 LTC3111 OPERATION Should the output voltage become shorted, the input current limit is reduced to approximately one half of the normal operating current limit. Reverse Current Limit During fixed frequency operation, a reverse current comparator on switch D monitors the current entering the VOUT pin. When this current exceeds 1A (typical) switch D will be turned off for the remainder of the switching cycle. This feature protects the buck-boost converter from excessive reverse current if the buck-boost output is held above the regulation voltage. Internal Soft-Start The LTC3111 buck-boost converter has an independent internal soft-start circuit with a nominal duration of 2ms. The converter remains in regulation during soft-start and will therefore respond to output load transients which occur during this time. In addition, the output voltage rise time has minimal dependency on the size of the output capacitor or load current during start-up. Soft-start is reset during a thermal shutdown. THERMAL CONSIDERATIONS For the LTC3111 to provide maximum output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. This can be accomplished by taking advantage of the large thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct the heat away from the IC and into a copper plane with as much area as possible. The efficiency and maximum output current capability of the LTC3111 will be reduced if the converter is required to continuously deliver large amounts of power or operate at high temperatures. The amount of output current derated is dependent upon factors such as board ground plane or heat sink area, ambient operating temperature and the input/output voltages of the application. A poor thermal design can cause excessive heating, resulting in impaired performance or reliability. The temperature rise curves given in the Typical Performance Characteristics section can be used as a guide to predict junction temperature rise from ambient. These curves were generated by mounting the LTC3111 to the 4-layer FR-4 demo printed circuit board layout shown in Figure 4. The curves were taken at room temperature, elevated ambient temperature will result in greater thermal rise rates due to increased RDS(ON) of the N-channel MOSFETs with temperature. The die temperature of the LTC3111 should be kept below the maximum junction rating of 125°C for E- and I-grades and 150°C for H- and MP-grades. In the event that the junction temperature gets too high (approximately 170°C), the input current limit will be linearly decreased from its typical value. If the junction temperature continues to rise and exceeds approximately 175°C the LTC3111 will be disabled. All power devices are turned off and all switch nodes put to a high impedance state. The soft-start circuit for the converter is reset during thermal shutdown to provide a smooth recovery once the overtemperature condition is eliminated. When the die temperature drops to approximately 170°C the LTC3111 will restart. UNDERVOLTAGE LOCKOUTS The LTC3111 buck-boost converter is disabled and all power devices are turned off until the VCC supply reaches 2.35V (typical). The soft-start circuit is reset during undervoltage lockout to provide a smooth restart once the input voltage rises above the undervoltage lockout threshold. A second UVLO circuit disables all power devices if VIN is below 2.1V rising, 1.9V falling (typical). This can provide a lower VIN operating range in applications where VCC is powered from an alternate source or VOUT after start-up. INDUCTOR DAMPING When the LTC3111 is disabled (RUN = 0V) or sleeping during Burst Mode operation (PWM/SYNC = 0V), active circuits “damp” the inductor voltage through 1kΩ (typical) impedance between SW1 and SW2 and GND to reduce ringing and EMI. 3111fa 12 For more information www.linear.com/LTC3111 LTC3111 OPERATION PWM MODE OPERATION When the PWM/SYNC pin is held high, the LTC3111 buckboost converter operates in a fixed-frequency pulse-width modulation (PWM) mode using voltage mode control. Full output current is only available in PWM mode. A proprietary switching algorithm allows the converter to transition between buck, buck-boost, and boost modes without discontinuity in inductor current. The switch topology for the buck-boost converter is shown in Figure 2. VIN A B OUTPUT VOLTAGE PROGRAMMING The output voltage is set via the external resistor divider comprised of resistors R1 and R2 as show in Figures 1. The resistor divider values determine the output regulation voltage according to: VOUT L This switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple, and loop transfer function throughout the operational modes. These advantages result in increased efficiency and stability in comparison to the traditional 4-switch buck-boost converter. D C 3111 F02 Figure 2. Buck-Boost Switch Topology When the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. Switch D turns on at maximum duty cycle and switch C turns on just long enough to refresh the voltage on the BST2 capacitor used to drive switch D. Switches A and B are pulse-width modulated to produce the required duty cycle to support the output regulation voltage. As the input voltage nears the output voltage, switches A and D are on for a greater portion of the switching period, providing a direct current path from VIN to VOUT. Switches B and C are turned on only enough to ensure proper regulation and/or provide charging of the BST1 and BST2 capacitors. The internal control circuitry will determine the proper duty cycle in all modes of operation, which will vary with load current. As the input voltage drops well below the output voltage, the converter operates solely in boost mode. Switch A turns on at maximum duty cycle and switch B turns on just long enough to refresh the voltage on the BST1 capacitor used to drive A. Switches C and D are pulse-width modulated to produce the required duty cycle to regulate the output voltage. R1 VOUT = 0.8V • 1+ R2 In addition to setting the output voltage, the value of R1 is instrumental in controlling the dynamics of the compensation network. When changing the value of this resistor, care must be taken to understand the impact this will have on the compensation network. In addition, the Thevenin equivalent resistance of the resistor divider controls the gain of the input current limit. To maintain sufficient gain in this loop, it is recommended that the Thevenin resistance be greater than 100kΩ. RUN Comparator In addition to serving as a logic-level input to enable the IC, the RUN pin includes an accurate internal comparator that allows it to be used to set custom rising and falling on/off thresholds with the addition of an external resistor divider. When RUN is driven above its logic threshold (0.8V typical), the LDO regulator is enabled, which provides power to the internal control circuitry of the IC. If the voltage on RUN is increased further so that it exceeds the RUN comparator accurate analog threshold (1.2V typical), all functions of the buck-boost converter will be enabled and a start-up sequence will ensue. If RUN is brought below the accurate comparator threshold, the buck-boost converter will inhibit switching, but the 3111fa For more information www.linear.com/LTC3111 13 LTC3111 OPERATION LDO regulator and control circuitry will remain powered unless RUN is brought below its logic threshold. Therefore, in order to completely shut down the IC, it is necessary to ensure that RUN is brought below its worst-case low logic threshold of 0.3V. RUN is a high voltage input and can be tied directly to VIN to continuously enable the IC when the input supply is present. The RUN pin can be driven above VIN or VOUT as long as it stays within the operating range of 15V. With the addition of an optional resistor divider as shown in Figure 3, the RUN pin can be used to establish a userprogrammable turn on and turn off threshold. VIN R5 1.2V RUN R6 – + LTC3111 ENABLE SWITCHING ACCURATE THRESHOLD 0.8V – + ENABLE SWITCHING LDO AND CONTROL CIRCUITS LOGIC THRESHOLD 3111 F03 Figure 3. Accurate RUN Comparator The buck-boost converter is enabled when the voltage on RUN reaches 1.2V (nominal). Therefore, the turn-on voltage threshold on VIN is given by: R5 VIN(RUN) = 1.2V • 1+ R6 Once the converter is enabled, the RUN comparator includes a built-in hysteresis of approximately 120mV, so that the turn-off threshold will be approximately 10% lower than the turn-on threshold. Put another way, the internal threshold level for the RUN comparator looks like 1.08V after the IC is enabled. The RUN comparator is relatively noise insensitive, but there may be cases due to PCB layout, very large value resistors for R5 and R6 or proximity to noisy components where noise pickup is unavoidable and may cause the turn-on or turn-off of the IC to be intermittent. In these cases, a filter capacitor can be added across R6 to ensure proper operation. Powering VCC from an External Source The LTC3111’s VCC regulator can be powered or back-fed from an external source up to 5.5V. The advantage of back feeding VCC from a voltage above 4.2V is higher efficiency. For 5VOUT applications, VCC can be easily powered from VOUT using an external low current Schottky as shown in several applications circuits in the Typical Applications section. Back feeding VCC also improves a light load PWM mode output voltage ripple that occurs when the inductor passes through zero current by reducing the switch pin anti-cross conduction times. A disadvantage of powering VCC from VOUT is that no-load quiescent current increases at lower input voltage in Burst Mode operation as shown in the Typical Performance Characteristics (compared to VCC powered from VIN). Burst Mode OPERATION When the PWM/SYNC pin is held low, the buck-boost converter operates utilizing a variable frequency switching algorithm designed to improve efficiency at light load and reduce the standby current at zero load. In Burst Mode operation, the inductor is charged with fixed peak amplitude current pulses and as a result only a fraction of the maximum output current can be delivered when in Burst Mode operation. These current pulses are repeated as often as necessary to maintain the output regulation voltage. The maximum output current, IMAX, which can be supplied in Burst Mode operation is dependent upon the input and output voltage as approximated by the following formula: IMAX = IPK VIN • η• A 2 VIN + VOUT where IPK is the Burst Mode peak current limit (0.8A typical) in amps and η is the efficiency. If the buck-boost load exceeds the maximum Burst Mode current capability, the output rail will lose regulation. In Burst Mode operation, the error amplifier is configured for low power operation and used to hold the compensation pin, COMP, to reduce transients that may occur during transitions from and to burst and PWM mode operation. 3111fa 14 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION The basic LTC3111 application circuit is shown on the front page of this data sheet. The external component selection is dependent upon the required performance of the IC in each particular application given trade-offs such as PCB area, output voltages, output currents, ripple voltages, and efficiency. This section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the application circuit. Inductor Selection To achieve high efficiency, a low ESR inductor should be utilized for the buck-boost converter. In addition, the buckboost inductor must have a saturation current rating that is greater than the worst-case average inductor current plus half the ripple current. The peak-to-peak inductor current ripple for buck or boost mode operation can be calculated from the following formulas: ∆IL(P-P_BUCK) = VOUT L ∆IL(P-P_BOOST) = VIN L V –V 1 • IN OUT • – tLOW VIN f V –V 1 • OUT IN • – tLOW VOUT f where f is the frequency in Hz and L is the inductance in Henries and tLOW is the switch pin minimum low time in seconds, which is typically 160ns. In addition to affecting output current ripple, the inductor value can also impact the stability of the feedback loop. In boost mode, the converter transfer function has a righthalf-plane zero at a frequency that is inversely proportional to the value of the inductor. As a result, a large inductance can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. It is recommended that the inductor value be chosen less than 15μH if the converter is to be used in the boost region. For 800kHz operation, a 4.7μH inductor is recommended for 5VOUT and 10μH for 12VOUT. The inductor DC resistance can impact the efficiency of the buck-boost converter as well as the maximum output current capability at low input voltage. In buck mode, the output current is limited only by the inductor current reaching the current limit value. However, in boost mode, especially at large step-up ratios, the output current capability can also be limited by the total resistive losses in the power stage. These include switch resistances, inductor resistance, and PCB trace resistance. Use of an inductor with high DC resistance can degrade the output current capability from that shown in the graph in the Typical Performance Characteristics section of this data sheet. Different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. Shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. The choice of inductor style depends upon the price, sizing, and EMI requirements of a particular application. Table 1 provides a small sampling of inductors that are well suited to many LTC3111 buck-boost converter applications. Within each family (i.e., at a fixed size), the DC resistance generally increases and the maximum current generally decreases with increased inductance. Table 1. Representative Buck-Boost Surface Mount Inductors VALUE (μH) DCR (mΩ) MAX DC CURRENT (A) SIZE (mm) W×L×H Coilcraft LPS6225 LPS6235 4.7 6.8 65 75 3.2 2.8 6.2 × 6.2 × 2.5 6.2 × 6.2 × 3.5 Cooper-Bussmann FP3-8R2-R CD1-150-R 8.2 15 74 50 3.4 3.6 7.3 × 6.7 × 3.0 10.5 × 10.4 × 4.0 Sumida CDRH8D28/HP CDRH8D28NP 10 4.7 78 24.7 3.0 3.4 8.3 × 8.3 × 3.0 8.3 × 8.3 × 3.0 TOKO B1047AS-6R8N B1179BS-150M 6.8 15 36 56 2.9 2.7 7.6 × 7.6 × 5.0 12.0 × 12.0 × 6.0 Würth 7447789004 744311470 4.7 4.7 33 19.5 2.9 6 7.3 × 7.3 × 3.2 6.9 × 6.9 × 3.8 PART NUMBER Output Capacitor Selection A low ESR output capacitor should be utilized at the buck-boost converter output in order to minimize output voltage ripple. Multilayer X5R and X7R dielectric ceramic capacitors are an excellent choice as they have low ESR and are available in small footprints. The capacitor should be 3111fa For more information www.linear.com/LTC3111 15 LTC3111 APPLICATIONS INFORMATION chosen large enough to reduce the output voltage ripple to acceptable levels. The minimum output capacitor needed for a given output voltage ripple (neglecting the capacitor ESR and ESL) can be calculated by the following formulas: ∆VP-P(BUCK ) = ILOAD • tLOW COUT ∆VP-P(BOOST ) = ILOAD f •COUT V –V +t • f • VIN • OUT IN LOW VOUT where f is the frequency in Hz, COUT is the output capacitance in μF, ILOAD is the output current in amps and tLOW is the switch pin minimum low time in seconds, which is typically 160ns. In addition to output ripple generated across the output capacitor, there is also output ripple produced across the internal resistance of the output capacitor. The ESRgenerated output voltage ripple is proportional to the series resistance of the output capacitor and is given by the following expression: ∆VP-P(BUCK ) = ILOAD •RESR ≅I •R 1– tLOW • f LOAD ESR ∆VP-P(BOOST ) = Capacitor Vendor Information Both the input bypass capacitors and output capacitors used with the LTC3111 must be low ESR and designed to handle the large AC currents generated by switching converters. This is important to maintain proper functioning of the IC and to reduce input/output ripple. Many modern low voltage ceramic capacitors experience significant loss in capacitance from their rated value with increased DC bias voltages. For example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. As a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a larger case size than required in order to actually realize the intended capacitance at the full operating voltage. For details, consult the capacitor vendor’s curve of capacitance versus DC bias voltage. The capacitors listed in Table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to LTC3111 application circuits. All listed capacitors are either X5R or X7R dielectric in order to ensure that capacitance loss over temperature is minimized. Table 2. Representative Bypass and Output Capacitors ILOAD •RESR • VOUT ILOAD •RESR • VOUT ≅ VIN (1– tLOW • f ) VIN where RESR is the series resistor of the output capacitor and all other terms are as previously defined. Input Capacitor Selection It is recommended that a low ESR ceramic capacitor with a value of at least 10μF be located as close to the VIN pin as possible. In addition, the return trace from the pin to the ground plane should be made as short as possible. It is important to minimize any stray resistance from the converter to the battery or power source. If cabling is required to connect the LTC3111 to the battery or power supply, a higher ESR capacitor or a series resistor with a low ESR capacitor in parallel with the low ESR capacitor may be required to damp out ringing caused by the cable inductance. VALUE (μF) VOLTAGE (V) SIZE (mm) L × W × H (FOOTPRINT) AVX 12103D226MAT2A 22 25 3.2 × 2.5 × 2.79 X5R Ceramic Kemet C220X226K3RACTU 22 25 A700D226M016ATE030 22 16 5.7 × 5.0 × 2.4 X7R Ceramic 7.3 × 4.3 × 2.8 Al Poly, 25mΩ Murata GRM32ER71E226KE15L 22 25 3.2 × 2.5 × 2.5 X7R Ceramic Panasonic ECJ-4YB1E226M 22 25 3.2 × 2.5 × 2.5 X5R Ceramic Sanyo 25SVPF47M 47 25 6.6 × 6.6 × 5.9 OS-CON, 30mΩ Vishay 94SVPD476X0035F12 47 35 10.3 × 10.3 × 12.6 OS-CON, 30mΩ PART NUMBER 3111fa 16 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION PCB Layout Considerations The LTC3111 switches large currents at high frequencies. Special attention should be paid to the PCB layout to ensure a stable, noise-free and efficient application circuit. Figure 4 presents a representative PCB layout to outline some of the primary considerations. A few key guidelines are outlined below: 1.All circulating high current paths should be kept as short as possible. This can be accomplished by keeping the routes to all circled components in the figure below as short and as wide as possible. Capacitor ground connections should via down to the ground plane in the shortest route possible. The bypass capacitors on VIN should be placed as close to the IC as possible and should have the shortest possible paths to ground. 2.The exposed pad is the power ground connection for the LTC3111. Multiple vias should connect the back pad directly to the ground plane. In addition maximization of the metallization connected to the back pad will improve the thermal environment and improve the power handling capabilities of the IC. 3.The circled components and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. This minimizes EMI and reduces inductive drops. 4.Connections to all of the circled components should be made as wide as possible to reduce the series resistance. This will improve efficiency and maximize the output current capability of the buck-boost converter. THERMAL AND PGND VIAS CIN COUT CBST1 CBST2 Figure 4a. Top and Fabrication Layer of Example PCB Figure 4b. Bottom and Fabrication Layer of Example PCB 3111fa For more information www.linear.com/LTC3111 17 LTC3111 APPLICATIONS INFORMATION 5.To prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned to the ground plane using a via placed close to the IC and away from the power connections. mum low time, which is typically 160ns. The parameter RS represents the average series resistance of the power stage and can be approximated as twice the average power switch resistance plus the DC resistance of the inductor. GBUCK = GDIVIDER •GPWM •GPOWER 6.Keep the connection from the resistor dividers to the feedback pins (FB pin) as short as possible and away from the switch pin connections. 7. Crossover connections should be made on inner copper layers if available. If it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane. Buck Mode Small-Signal Model The LTC3111 uses a voltage mode control loop to maintain regulation of the output voltage. An externally compensated error amplifier drives the COMP pin to generate the appropriate duty cycle of the power switches. Use of an external compensation network provides the flexibility for optimization of closed-loop performance over the wide variety of output voltages, switching frequencies, and external component values supported by the LTC3111. The small-signal transfer function of the buck-boost converter is different in the buck and boost modes of operation and care must be taken to ensure stability in both operating regions. When stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small-signal transfer function from the error amplifier output COMP, to the converter output voltage is given by the following equation: VO =G VCOMP BUCK BUCK 1+ s 2 • π • fZ s s 1+ + 2 • π • fO •Q 2 • π • fO 2 The gain term, GBUCK, is comprised of three different components: the gain of the analog divider, the gain of the pulse-width modulator, and the gain of the power stage as given by the following expressions where VIN is the input voltage to the converter, f is the switching frequency, R is the load resistance, and tLOW is the switch pin mini- GDIVIDER = 18 VIN GPWM = 2.5 • (1– tLOW • f ) GPOWER = VIN •R (1– tLOW • f ) • (R+RS ) Notice that the gain of the analog divider cancels the input voltage dependence of the power stage. As a result, the buck mode gain is approximated by a constant as given by the following equation: GBUCK = 45 • R ≅ 45 = 33dB R+RS The buck mode transfer function has a single zero which is generated by the ESR of the output capacitor. The zero frequency, fZ, is given by the following expression where RC and CO are the ESR and value of the output filter capacitor respectively. fZ = 1 2 • π •RC •CO In most applications, an output capacitor with a very low ESR is utilized in order to reduce the output voltage ripple to acceptable levels. Such low values of capacitor ESR result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. The denominator of the buck mode transfer function exhibits a pair of resonant poles generated by the LC filtering of the power stage. The resonant frequency of the power stage, fO, is given by the following expression where L is the value of the inductor: fO = R +RS 1 1 • ≅ 2 • π L •CO (R+RC ) 2 • π • L •CO 3111fa 18 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION The quality factor, Q, has a significant impact on compensation of the voltage loop since a higher Q factor produces a sharper loss of phase near the resonant frequency. The quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, RS. Lower values of RS will increase the Q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. Q= ≅ L •CO (R+RC ) • (R+RS ) R •RC •CO +L +CO •RS • (R +RC ) GDIVIDER = L +C •R R O S When stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small-signal transfer function from control voltage, VCOMP, to the output voltage is given by the following expression: VCOMP BOOST = GBOOST s s 1+ 2 • π • f • 1– 2 • π • f Z RHPZ s s + 1+ 2 • π • fO •Q 2 • π • fO 2 In boost mode operation, the transfer function is characterized by a pair of resonant poles and a zero generated by the ESR of the output capacitor as in buck mode. However, in addition there is a right-half-plane zero which generates increasing gain and decreasing phase at higher frequencies. As a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. The boost mode gain, GBOOST, is comprised of three components: the analog divider, the pulse width modulator and the power stage. The gain of the PWM remains GPOWER = 18 VOUT VOUT 2 (1– tLOW • f ) • VIN By combining the individual terms, the total gain in boost mode can be reduced to the following expression. Notice that unlike in buck mode, the gain in boost mode is a function of both the input and output voltage: L •CO Boost Mode Small-Signal Model VO the same as in buck mode operation, but the gain of the analog divider and power stage in boost mode are given by the following equation: GBOOST = 45 • VOUT VIN In boost mode operation, the frequency of the right-halfplane zero, fRHPZ, is given by the following expression. The frequency of the right-half-plane zero decreases at higher loads and with larger inductors: R • (1– tLOW • f ) • VIN 2 • π •L • VOUT 2 2 fRHPZ − 2 In boost mode, the resonant frequency of the power stage has a dependence on the input and outputvoltage as shown by the following equation: R • VIN2 VOUT 2 1 1 V 1 fO = • ≅ • IN • 2 • π L •CO • (R+RC ) 2 • π VOUT L •CO RS + Finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression: R • VIN2 L •CO •R • RS + VOUT 2 Q= L +CO •RS •R 3111fa For more information www.linear.com/LTC3111 19 LTC3111 APPLICATIONS INFORMATION Compensation Of The Voltage Loop The small-signal models of the LTC3111 reveal that the transfer function from the error amplifier output, COMP, to the output voltage is characterized by a set of resonant poles and a possible zero generated by the ESR of the output capacitor as shown in the Bode plot of Figure 5. In boost mode operation, there is an additional right-halfplane zero that produces phase lag and increasing gain at higher frequencies. Typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right-half-plane zero is minimized. The low frequency gain in buck mode is a constant, but varies with both VIN and VOUT in boost mode. For charging or other applications that do not require an optimized output voltage transient response, a simple Type I compensation network as shown in Figure 6 can be used to stabilize the voltage loop. To ensure sufficient phase margin, the gain of the error amplifier must be low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. In most applications, the low bandwidth of the Type I compensated loop will not provide sufficient transient response performance. To obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a Type III compensation network as shown in Figure 7 is required. A Bode plot of the typical Type III compensation network is shown in Figure 8. The Type III compensation network provides a pole near the origin which produces a very high loop gain at DC to minimize any steady-state error in the regulation voltage. Two zeros located at fZERO1 and fZERO2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, fO, of the power stage. The Type III compensation network also introduces a second and third pole. The second pole, at frequency fPOLE2, reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending GAIN –40dB/DEC –20dB/DEC PHASE BUCK MODE BOOST MODE fO fRHPZ 3111 F05 Figure 5: Buck-Boost Converter Bode Plot VOUT LTC3111 R1 0.8V FB C1 R2 + – COMP SGND 3111 F06 Figure 6: Error Amplifier with Type I Compensation VOUT R1 LTC3111 RFF 0.8V FB CFF R2 RFB CPOLE CFB + – COMP SGND 3111 F07 Figure 7: Error Amplifier with Type III Compensation 3111fa 20 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION where all frequencies are in Hz, resistances are in ohms, and capacitances are in farads. GAIN –20dB/DEC –20dB/DEC fZERO1 = 1 2 • π •RFB •CFB fZERO2 = 1 1 ≅ 2 • π (R1+RFF ) •CFF 2 • π •R1•CFF fPOLE2 = PHASE fZERO1 fPOLE2 fPOLE3 f 3111 F08 fZERO2 Figure 8: Type III Compensation Bode Plot too high in frequency. The third pole at frequency fPOLE3 provides attenuation of high frequency switching noise. The transfer function of the compensated Type III error amplifier from the input of the resistor divider to the output of the error amplifier, COMP, is: VCOMP = GCOMP • VO s 1+ 2 • π • f ZERO1 s • 1+ 2 • π • f s s • 1+ 2 • π • f POLE2 ZERO2 s • 1+ 2 • π • f POLE3 The compensation gain is given by the following equation. The simpler approximate value is sufficiently accurate in most cases since CFB is typically much larger in value than CPOLE. GCOMP ≅ 1 1 ≅ R1• (CFB +CPOLE ) R1•CFB The pole and zero frequencies of the Type III compensation network can be calculated from the following equations fPOLE3 = 1 1 ≅ C •C 2 • π • FB POLE •RFB 2 • π •RFB •CPOLE CFB +CPOLE 1 2 • π •RFF •CFF In most applications the compensation network is designed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right-half-plane zero to minimize the additional phase loss. Once the crossover frequency is decided upon, the phase boost provided by the compensation network is centered at that point in order to maximize the phase margin. A larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. The Q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180° of phase loss in the power stage occurs. For very low values of series resistance, RS, the Q will be higher and the phase loss will occur sharply. In such cases, the phase of the power stage will fall rapidly to –180° above the resonant frequency and the total phase margin must be provided by the compensation network. 3111fa For more information www.linear.com/LTC3111 21 LTC3111 APPLICATIONS INFORMATION However, with higher losses in the power stage (larger RS) the Q factor will be lower and the phase loss will occur more gradually. As a result, the power stage phase will not be as close to –180° at the crossover frequency and less phase boost is required of the compensation network. The LTC3111 error amplifier is designed to have a fixed maximum bandwidth in order to provide rejection of switching noise to prevent it from interfering with the control loop. From a frequency domain perspective, this can be viewed as an additional single pole as illustrated in Figure 9. The nominal frequency of this pole is 400kHz. For typical loop crossover frequencies below about 60kHz the phase contributed by this additional pole is negligible. However, for loops with higher crossover frequencies this additional phase loss should be taken into account when designing the compensation network. LTC3111 0.8V FB + – RFILT CFILT COMP 3111 F09 Figure 9. Internal Loop Filter Loop Compensation Example This section provides an example illustrating the design of a compensation network for a typical LTC3111 application circuit. In this example a 5V regulated output voltage is generated with the ability to supply a 500mA load from an input power source ranging from 3.5V to 15V. To reduce switching losses a 800kHz switching frequency has been chosen for this example. In this application the maximum inductor current ripple will occur at the highest input voltage. An inductor value of 4.7µH has been chosen to limit the worst-case inductor current ripple to less than 1A peak to peak. A low ESR output capacitor with a value of 22µF is specified to yield a worst-case output voltage ripple (occurring at the worst-case step-up ratio and maximum load current) of approximately 20mV. In summary, the key power stage specifications for this LTC3111 example application are given below. f = 0.8MHz, tLOW = 160ns VIN = 3.5V to 15V VOUT = 5V at R = 10Ω COUT = 22µF, RC = 10mΩ L = 4.7µH, RL = 25mΩ RS = 200mΩ With the power stage parameters specified, the compensation network can be designed. In most applications, the most challenging compensation corner is boost mode operation at the greatest step-up ratio and highest load current since this generates the lowest frequency right-half-plane zero and results in the greatest phase loss. Therefore, a reasonable approach is to design the compensation network at this worst-case corner and then verify that sufficient phase margin exists across all other operating conditions. In this example application, at VIN = 3.5V and the full 500mA load current, the right-half-plane zero will be located at 136kHz and this will be a dominant factor in determining the bandwidth of the control loop. The first step in designing the compensation network is to determine the target crossover frequency for the compensated loop. A reasonable starting point is to assume that the compensation network will generate a peak phase boost of approximately 60°. Therefore, in order to obtain a phase margin of 60°, the loop crossover frequency, fC, should be selected as the frequency at which the phase 3111fa 22 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION of the buck-boost converter reaches –180°. As a result, at the loop crossover frequency the total phase will be simply the 60° of phase provided by the error amplifier as shown: model equations using LTspice® software. In this case, the phase reaches –180° at 40kHz making fC = 40kHz the target crossover frequency for the compensated loop. Phase Margin = ϕBUCK-BOOST + ϕERRORAMPLIFIER + 180° From the Bode plot of Figure 10 the gain of the power stage at the target crossover frequency is 13.5dB. Therefore, in order to make this frequency the crossover frequency in the compensated loop, the total loop gain at fC must be adjusted to 0dB. To achieve this, the gain of the compensation network must be designed to be –13.5dB at the crossover frequency. = –180° + 60° + 180° = 60° Similarly, if a phase margin of 45° is required, the target crossover frequency should be picked as the frequency at which the buck-boost converter phase reaches –195° so that the combined phase at the crossover frequency yields the desired 45° of phase margin. This example will be designed for a 60° phase margin to ensure adequate performance over parametric variations and varying operating conditions. As a result, the target crossover frequency, fC, will be the point at which the phase of the buck-boost converter reaches –180°. It is generally difficult to determine this frequency analytically given that it is significantly impacted by the Q factor of the resonance in the power stage. As a result, it is best determined from a Bode plot of the buck-boost converter as shown in Figure 10. This Bode plot is for the LTC3111 buck-boost converter using the previously specified power stage parameters and was generated from the small-signal 40 90 30 45 GAIN 20 –45 PHASE 0 –90 –10 –135 –20 –180 –30 –40 –255 fC = 40kHz 10 100 1k 10k (DEG) (dB) 10 0 100k –270 1M (Hz) 3111 F10 Figure 10. Converter Bode Plot VIN = 3.5V, VOUT = 5V, R = 10Ω At this point in the design process, there are three constraints that have been established for the compensation network. It must have –13.5dB of gain at fC = 40kHz, a peak phase boost of 60° that is centered at fC = 40kHz. One way to design a compensation network to meet these targets is to simulate the compensation error amplifier Bode plot in LTspice for the typical compensation network shown on the front page of this data sheet. Then, the gain, pole and zero frequencies can be iteratively adjusted until the required constraints are met. Alternatively, an analytical approach can be used to design a compensation network with the desired phase boost, center frequency and gain. In general, this procedure can be cumbersome due to the large number of degrees of freedom in the Type III compensation network. However the design process can be simplified by assuming that both the compensation zeros occur at the same frequency, fZ, and both higher order poles (fPOLE2 and fPOLE3) occur at the common frequency, fP. In most cases this is a reasonable assumption since the zeros are typically located between 1kHz and 10kHz and the poles are typically located near each other at much higher frequencies. Given this assumption, the maximum phase boost, provided by the compensation error amplifier is determined simply by the amount of separation between the poles and zeros as shown by the following equation: φMAX = 4 • arctan fP – 270° fZ 3111fa For more information www.linear.com/LTC3111 23 LTC3111 APPLICATIONS INFORMATION A reasonable choice is to pick the frequency of the poles, fP, to be 50 times higher than the frequency of the zeros, fZ, which provides a peak phase boost of approximately 60° as was assumed previously. Next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. The frequency of the maximum phase boost, fCENTER, is the geometric mean of the pole and zero frequency as: fCENTER = fP • fZ = 50 • fZ ≅ 7 • fZ Therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zero should be located at one-seventh of the crossover frequency and the poles should be located at seventh times the crossover frequency as given by the following equation: fZ = fC 40kHz = = 5.71kHz 7 7 This equation completes the set of constraints needed to determine the compensation component values. Specifically, the two zeros, fZERO1 and fZERO2, should be located near 5.71kHz. The two poles, fPOLE2 and fPOLE3, should be located near 280kHz and the gain should be set to provide a gain at the crossover frequency of GCENTER = –13.5dB. The first step in defining the compensation component values is to pick a value for R1 that provides an acceptably low quiescent current through the resistor divider. A value of R1 = 1MΩ is a reasonable choice. Next, the value of CFB can be found in order to set the error amplifier gain at the crossover frequency to –13.5dB as follows: 50 GCENTER = –13.5dB = 20 •log 2 • π • 40kHz •1MΩ•CFB 50 CFB = 2 • π • 40kHz •1MΩ •10 fP = 7 • fC = 7 • 40kHz = 280kHz This placement of the poles and zeros will yield a peak phase boost of 60° that is centered at the crossover frequency, fC. Next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, GCENTER, must be set to –13.5dB. The gain of the compensated error amplifier at the point of the phase gain is given by: – 13.5 20 ≅ 1000pF The compensation poles can be set at 280kHz and the zeros at 5.71kHz by using the expressions for the pole and zero frequencies given in the previous sections. Setting the frequency of the first zero, fZERO1, to 5.71kHz results in the following value for RFB: RFB = 1 ≅ 28.0kΩ 2 • π • 5.71kHz•1000pF 2 • π • fP dB GCENTER = 10 •log ( 2 • π • fZ )3 • (R1•CFB )2 This leaves the free parameter, CPOLE, to set frequency fPOLE1 to the common pole frequency of 280kHz as given: Assuming a multiple of 50 separation between the pole and zero frequencies this can be simplified to the following expression: CPOLE = 1 ≅ 22pF 2 • π • 280kHz • 28kΩ 50 GCENTER = 20 •log dB 2 • π • fC •R1•CFB 3111fa 24 For more information www.linear.com/LTC3111 LTC3111 APPLICATIONS INFORMATION Next, CFF can be chosen to set the second zero, fZERO2, to the common zero frequency of 5.71kHz. 30 1 ≅ 27pF 2 • π • 5.71kHz •1MΩ 40kHz, 57° 20 (dB) 10 Finally, the resistor value RFF can be chosen to place the second pole at 280kHz. 45 40kHz, –14dB PHASE GAIN 0 0 (DEG) C FF = 90 40 –10 –45 –20 1 RFF = ≅ 20kΩ 2 • π • 280kHz • 27pF –30 –40 The final step in the design process is to compute the Bode plot for the entire designed compensation network and confirm its phase margin and crossover frequency. The complete loop Bode plot for this example is shown in Figure 12. The loop crossover frequency is 40kHz and the phase margin is approximately 59°. The Bode plot for the complete loop should be checked over all operating conditions and for variations in component values to ensure that sufficient phase margin exist in all cases. The stability of the loop should also be confirmed via time domain simulation and by the transient response of the converter in the actual circuit. 100 1k 10k 100k –90 1M (Hz) 3111 F11 Figure 11: Compensation Error Amplifier Bode Plot 60 180 50 135 PHASE (dB) 40 40kHz, 59° 90 30 45 20 0 10 –45 GAIN 0 –90 –10 –135 –20 –180 –30 –225 –40 10 100 1k (DEG) Now that the pole frequencies, zero frequencies and gain of the compensation network have been established, the next step is to generate a Bode plot for the compensated error amplifier to confirm its gain and phase properties. A Bode plot of the error amplifier with the designed compensation component values is shown in Figure 11. The Bode plot confirms that the peak phase occurs at 40kHz and the phase boost at that point is 57°. In addition, the gain at the peak phase frequency is –14dB which is close to the design target. 10 10k 100k 1M –270 (Hz) 3111 F12 Figure 12: Complete Loop Bode Plot 3111fa For more information www.linear.com/LTC3111 25 LTC3111 TYPICAL APPLICATIONS 1, 2, 3 Li-Ion to 5V 4.7µH 0.1µF VIN 3V TO 12.6V 1 TO 3-CELL Li-Ion + NUMBER OF CELLS R 1 274k 2 698k 3 1.13M SW1 SW2 BST1 BST2 VIN VOUT 10µF 0.1µF 680pF LTC3111 COMP BURST PWM PWM/SYNC RUN R SNSGND SGND 26.1k 1M 20k VOUT 5V 750mA 22µF VIN > 4V 33pF 27pF FB 191k VCC PGND 1µF 3111 TA02a 154k Wide VIN to 5VOUT Efficiency 100 90 EFFICIENCY (%) 80 70 60 50 VIN = 3.6V VIN = 7.2V VIN = 10.8V 40 30 0.0001 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 3111 TA02b 3111fa 26 For more information www.linear.com/LTC3111 LTC3111 TYPICAL APPLICATIONS LTC3111 Synchronized to a 1.5MHz Clock, 5V/1A Output 2.2µH 0.1µF VIN 2.5V TO 15V SW1 SW2 BST1 BST2 VIN VOUT 10µF 0.1µF 270pF LTC3111 COMP 1.5MHz CLOCK 22µF 57.6k 1M 15pF PWM/SYNC OFF ON RUN MBR0520L OPTIONAL FB SNSGND 191k VCC SGND VOUT 5V 1A VIN > 5V 1µF PGND 3111 TA03a PWM/SYNC 5V/DIV SW1 10V/DIV SW2 5V/DIV INDUCTOR CURRENT 1A/DIV 500ns/DIV 3111 TA03b 3.3V Backup from a High Voltage Capacitor Bank Runs Down to VIN = 2V with 500mA Load 4.7µH 0.1µF VIN 2V TO 15V CIN 214mF 100µF SW1 SW2 BST1 BST2 VIN VOUT LTC3111 VCC 0.1µF 1600pF COMP PWM/SYNC SGND 1M FB VCC PGND 20k 33µF 36pF 33pF RUN SNSGND 24.3k VCC VOUT 3.3V 500mA MBR0520L OPTIONAL 316k 1µF 3111 TA04a VIN 5V/DIV VOUT 2V/DIV POWER SUPPLY REMOVED IOUT 500mA/DIV 2 SEC/DIV 3111 TA04b 3111fa For more information www.linear.com/LTC3111 27 LTC3111 TYPICAL APPLICATIONS Stepped Response from 1 or 2 Li-Ion to 12V Adapter Source VOUT = 5V 1- OR 2-SERIES Li-Ion CELLS LT®4352 IDEAL DIODE 4.7µH 0.1µF B520C 12V ADAPTER SW1 SW2 BST1 BST2 VIN VOUT 47µF 0.1µF 680pF LTC3111 COMP PWM/SYNC BURST PWM OFF ON 26.1k 20k 1M 33pF 27pF RUN 22µF VOUT 5V 1.5A VIN > 5V FB 191k VCC SNSGND SGND 1µF PGND 3111 TA05a VOUT 500mV/DIV VIN 2V/DIV TWO Li-Ion CELLS INDUCTOR CURRENT 1A/DIV IOUT = 500mA 1ms/DIV 3111 TA05b Custom Input Undervoltage Lockout Thresholds 4.7µH 0.1µF VIN 5V TO 15V 10µF ENABLED WHEN VIN REACHED 5V DISABLED WHEN VIN FALLS BELOW 4.5V SW1 SW2 BST1 BST2 VIN VOUT 680pF LTC3111 VCC COMP 1M PWM/SYNC 316k SNSGND 26.1k 20k 1M FB VCC VCC PGND VOUT 5V 22µF 1.5A 33pF 27pF RUN SGND 191k 1µF 3111 TA08a VIN 10V/DIV VIN 10V/DIV VOUT 5V/DIV VOUT 5V/DIV INDUCTOR CURRENT 1A/DIV INDUCTOR CURRENT 1A/DIV RLOAD = 3.3Ω 28 0.1µF 2ms/DIV 3111 TA08b RLOAD = 3.3Ω For more information www.linear.com/LTC3111 2ms/DIV 3111 TA08c 3111fa LTC3111 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 3.00 ±0.10 (2 SIDES) R = 0.115 TYP 8 0.40 ±0.10 14 3.30 ±0.10 1.70 ±0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 (DE14) DFN 0806 REV B 7 1 0.25 ±0.05 0.50 BSC 3.00 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3111fa For more information www.linear.com/LTC3111 29 LTC3111 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 5.10 (.201) MIN 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 8 1 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 3.20 – 3.45 (.065 ±.004) (.126 – .136) 0.305 ±0.038 (.0120 ±.0015) TYP 16 0.50 (.0197) BSC 4.039 ±0.102 (.159 ±.004) (NOTE 3) RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 ±0.076 (.011 ±.003) REF 16151413121110 9 DETAIL “A” 0° – 6° TYP 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 1234567 8 0.17 – 0.27 (.007 – .011) TYP 0.50 NOTE: (.0197) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MSE16) 0213 REV F 3111fa 30 For more information www.linear.com/LTC3111 LTC3111 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 1/14 Clarified graphs 1, 4, 5, 6 3111fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC3111 31 LTC3111 TYPICAL APPLICATION Regulated 12V Output from Wide Range Input Supply Wide VIN to 12VOUT Efficiency 100 10µH PWM 90 VIN 2.5V TO 15V SW1 SW2 BST1 BST2 VIN VOUT 10µF OFF ON 1000pF LTC3111 VCC BURST PWM 0.1µF COMP PWM/SYNC SGND 2.21M 20k VOUT 12V 0.5A, VIN > 5V 22µF 1.0A, VIN > 9V 18pF 39pF RUN SNSGND 44.2k FB 1µF PGND 70 60 50 40 158k VCC BURST 80 EFFICIENCY (%) 0.1µF 3111 TA06a 30 0.0001 VIN = 5V VIN = 12V 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 3111 TA06b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3533 2A (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40μA, ISD < 1μA, DFN Package LTC3113 3A (IOUT), 2MHz Low Noise Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 40μA, ISD < 1μA, DFN and TSSOP Packages LTC3534 7V, 500mA (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 7V, VOUT: 1.8V to 7V, IQ = 25μA, ISD < 1μA, DFN and GN Packages LTC3129/ LTC3129-1 15V, 200mA (IOUT), Synchronous Buck-Boost DC/DC VIN: 2.42V to 15V, VOUT: 1.4V to 15.75V, IQ = 1.3μA, ISD < 100nA, QFN and Converter with 1.3µA Quiescent Current MSOP Packages LTC3112 15V, 2.5A (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 15V, VOUT = 5V, IQ = 50μA, ISD < 1μA, DFN and TSSOP Packages LTC3785 10V, High Efficiency, Synchronous, No RSENSE™ Buck-Boost Controller VIN: 2.7V to 10V, VOUT: 2.7V to 10V, IQ = 86μA, ISD < 15μA, QFN Package LTC3115-1/ LTC3115-2 40V, 2A (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 40V, VOUT = 2.7V to 40V, IQ = 30μA, ISD < 1μA, DFN and TSSOP Packages LTC3789 High Efficiency, Synchronous, 4-Switch Buck-Boost Converter VIN: 4V to 38V, VOUT: 0.8V to 38V, IQ = 3mA, ISD < 60μA, QFN and SSOP Packages LTC3122 15V, 2.5A (IOUT), Synchronous Step-Up DC/DC Converter with Output Disconnect VIN:1.8V to 5.5V, VOUT: 2.2V to 15V. IQ = 25µA, ISD < 1µA, DFN and MSOP Packages 3111fa 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3111 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3111 LT 0114 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013