8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED VDD_UP VCC_ARROW 2 3 4 RESETB_C 6 5 8 RESETB RESETB_C TSW-102-08-G-S 16 C104 PULL UP IN S100 2A 1A 1B 2B 7914J-1-000E GND CLKIN 1 PULL DOWN IN D RESETB CLKIN_B P124 R130 10K IN 8.2K DNI 3.6K 0.1UF 1.8K 1 2 820 DIVIDER RATIO DEFAULT CONNECTED PPR MODE DISCONNECTED D DIVIDER RATIO TABLE FOR S0/S1/S2/S3 PINS 8.2K VDD_UP D/D SYNCB_C DRIVER MODE TABLE FOR S4,S5 PINS H=HSTL L=LVDS D=DISABLE S4=>CH1/CH0 S5=>CH3/CH2 IN SYNCB_C S101 2A 1A 1B 2B 7914J-1-000E SYNCB TSW-102-08-G-S C105 GND OUT_0 OUT OUT_0B OUT S2 OUT_0 OUT_0B S3 EXTCAP1 VDD_PIN6 1 2 3 4 5 6 S2 OUT0 OUT0B S3 EXTCAP1 VDD GND VDD_UP VCC_ARROW S0->CH0 R126 DIVIDER RATIO CONTROL 10K R127 10K PULL UP SCLK/SCL IN INPUT SEL VDD_UP LVDS OUT_3 GND CMOS SAMTECTSW10608GS3PIN VDD_UP VDD_UP OUT VCC_ARROW PULL DOWN PULL DOWN R132 10K OUT IN_SEL OUT GND OUT R109 8.2K P109 1 2 3 OUT R108 1.8K R107 3.6K P108 1 S1_PPR 2 3 SAMTECTSW10608GS3PIN DEFAULT CONNECT 1,2 PPR MODE CONNECT 2,3 R106 820 P107 1 2 3 OUT_3B VCC_ARROW SAMTECTSW10608GS3PIN GND P106 SDIO/SDA 1 S1 2 S1_PPR 3 SAMTECTSW10608GS3PIN OUT AD9508 VDD_UP SAMTECTSW10608GS3PIN R105 8.2K P105 1 2 3 SAMTECTSW10608GS3PIN R104 1.8K R103 3.6K P104 1 S0_PPR 2 3 IO VCC_ARROW SAMTECTSW10608GS3PIN DEFAULT CONNECT 1,2 PPR MODE CONNECT 2,3 SAMTECTSW10608GS3PIN R102 820 P103 1 2 3 P102 SCLK/SCL 1 S0 2 S0_PPR 3 SAMTECTSW10608GS3PIN PULL UP SDIO/SDA VDD_UP RESETB OUT_3B OUT_3 PROG_SEL EXTCAP2 VDD_PIN13 C S1->CH1 DIVIDER RATIO CONTROL P100 1 2 3 C 18 17 16 15 14 13 AD9508BCPZ OUT_1 OUT_1B S4_PPR S5_PPR OUT_2 OUT_2B VCC_ARROW 7 8 9 10 11 12 VDD_UP RESETB OUT3B OUT3 PROG_SEL EXTCAP2 VDD OUT_2B D/H R131 10K OUT1 OUT1B S4 S5 OUT2 OUT2B L/D P125 U100 SYNCB PAD S1 IN_SEL CLKB CLK SYNCB S0 L/L L/H DNI PULL UP H/D 0.1UF H/L H/H VCC_ARROW 1 2 PULL DOWN DEFAULT CONNECTED PPR MODE DISCONNECTED OUT_2 3.6K OUT_1B 1.8K OUT_1 820 PAD 24 23 22 21 20 19 CH1/CH0 CH3/CH2 GND S1 IN_SEL CLKIN_B CLKIN SYNCB S0 GND DEFAULT LVDS VCC_ARROW VCC_ARROW S3->CH3 DIVIDER RATIO CONTROL PULL UP IN SDO VDD_UP VCC_ARROW R116 1.8K R117 8.2K VDD_UP VCC_ARROW VCC_ARROW P117 1 2 3 GND SAMTECTSW10608GS3PIN GND DEFAULT CONNECT 1,2 PPR MODE CONNECT 2,3 R115 3.6K P116 1 S3_PPR 2 3 SAMTECTSW10608GS3PIN P113 1 2 3 P114 SDO 1 S3 2 S3_PPR 3 SAMTECTSW10608GS3PIN R114 820 P115 1 2 3 SAMTECTSW10608GS3PIN S-PIN PULL UP GND I2C DEFAULT SPI BYPASS CAPACITORS VDD_CORE R125 8.2K R100 VDD_CORE 0 GND R101 VDD_CORE GND 0 VDD_PIN13 0.1UF C111 0.1UF C109 DNI 0.1UF C108 P123 1 2 3 A GND SCHEMATIC AN A LO G DE V CES PULL DOWN PULL DOWN VCC_CIRCLE VDD_PIN6 VCC_ARROW SAMTECTSW10608GS3PIN R124 1.8K R123 3.6K P122 1 S5_PPR 2 3 SAMTECTSW10608GS3PIN GND S5_PPR SAMTECTSW10608GS3PIN P120 1 2 3 R122 820 P121 1 2 3 VDD_UP VDD_CORE DNI VCC_ARROW SAMTECTSW10608GS3PIN R121 8.2K 1UF GND SAMTECTSW10608GS3PIN PULL UP VDD_UP SAMTECTSW10608GS3PIN R120 1.8K SAMTECTSW10608GS3PIN A GND B FLOAT=SPI VCC_CIRCLE S4_PPR 0.47UF C103 S5->CH3/CH2 DRIVER MODE CONTROL S4->CH1/CH0 DRIVER MODE CONTROL R119 3.6K P119 1 S4_PPR 2 3 0.47UF C101 PULL DOWN PULL DOWN R118 820 P118 1 2 3 C102 1UF 0.1UF R113 8.2K OUT VDD_UP SAMTECTSW10608GS3PIN R112 1.8K R111 3.6K P112 1 S2_PPR 2 3 SAMTECTSW10608GS3PIN DEFAULT CONNECT 1,2 PPR MODE CONNECT 2,3 SAMTECTSW10608GS3PIN P110 CSB 1 S2 2 S2_PPR 3 SAMTECTSW10608GS3PIN R110 820 P111 1 2 3 P101 1 2 3 CSB PULL UP C106 B PROG SEL C100 EXTCAP2 R129 10K EXTCAP1 S2->CH2 DIVIDER RATIO CONTROL PROG_SEL R128 10K THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, AD9508 CUSTOMER EVALUATION DESIGN VIEW BOARD REV DRAWING NO. 30-8-2012 B 9508CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 PTD ENGINEER SIZE SCALE L.Xu D NONE 2 SHEET 1 1 OF 4 8 6 7 5 2 3 4 1 REVISIONS REV DESCRIPTION DATE APPROVED D D CLOCK OUTPUTS GND GND J209 142-0701-851 OUT0 0 CLOCK INPUT 100 0.1UF C222 R202 J210 142-0701-851 OUT0B 0 0.1UF GND C224 OUT R201 OUT_0B DNI OUT_0B 10PF C223 LVDS/HSTL R249 OUT 10PF OUT_0 C221 OUT_0 GND DNI CMOS CMOS GND OUT1B 0 R210 DNI 0 GND 0.1UF J201 142-0701-201 2 3 4 5 GND 0 C230 10PF R206 OUT2B J214 142-0701-851 0 0.1UF GND DNI CLKIN CLKIN_B IN CLKIN_B 0.1UF C201 0.1UF DNI 49.9 R214 GND 100 0.1UF IN GND J213 142-0701-851 OUT2 CLKIN GND GND R205 OUT_2B C232 B OUT R251 LVDS/HSTL OUT_2B 10PF C231 DNI OUT C229 OUT_2 C200 1 GND CMOS 3 100 4 MABA-007159-000000 J212 142-0701-851 SEC DNI R204 CMOS OUT_2 PRI GND 1 R213 2 3 4 5 0 49.9 10PF C228 DNI R209 T200 5 R215 0.1UF OUT_1B DNI OUT J200 142-0701-201 0 C226 OUT_1B J211 142-0701-851 OUT1 0 10PF R203 R221 LVDS/HSTL 100 OUT C 1 C225 OUT_1 R250 OUT_1 C227 DNI CMOS GND 0 GND C DNI R222 GND CMOS B DEFAULT INPUT SETUP: SINGLE-ENDED TO DIFFERENTIAL BY BALUN FROM J200 IF YOU WANT TO INPUT DIFFERENTIAL SIGNAL, REMOVE T200 AND R221,SOLDER DOWN R209 AND R210 GND GND GND 10PF C234 R208 J216 142-0701-851 OUT3B 0 0.1UF GND C236 OUT J215 142-0701-851 OUT3 0 0.1UF OUT_3B DNI OUT_3B R207 100 LVDS/HSTL R252 OUT C233 OUT_3 10PF OUT_3 C235 DNI CMOS CMOS GND A A DEFAULT OUTPUT SETUP: LVDS AND HSTL DIFFERENTIAL MODE SCHEMATIC AN A LO G DE V CES IF YOU WANT TO OUTPUT CMOS MODE, REMOVE 100 OHM RESISTER AND SOLDER DOWN 10 PF LAOD CAPACITORS THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, AD9508 CUSTOMER EVALUATION DESIGN VIEW BOARD REV DRAWING NO. 30-8-2012 B 9508CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 PTD ENGINEER L.Xu 2 SIZE SCALE D NONE SHEET 1 2 OF 4 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED USB SECTION D 3.3V 3.3V VCC_BAR 1UF C304 0.1UF VCC_BAR C303 D VDD_UP 3.3V VCC_ARROW VCC_BAR GND 22 23 49 51 8 9 21 10UF C302 1UF C301 AVCC 3.3V C SCL SDA GND AGND 13 17 C317 0.1UF VCC_BAR SCL SDA RESET* WAKEUP RDY0/SLRD RDY1/SLWR RESERVED Y300 1 2 6 18 24 34 39 50 VCC USB CHIP GND XTALIN XTALOUT DPLUS DMINUS CLKOUT/T1OUT IFCLK/T0OUT CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC 4 7 19 33 35 48 10 14 VCC_BAR 100K R307 100K R306 3.3V 12 11 15 16 5 20 36 37 38 24.000MEGHZ VCC_BAR U300 C318 0.1UF C305 GND GND SCLK/SCL SDIO/SDA C306 CSB SDO D+ D- VCC_ARROW VCC_BAR SYNCB_C 12PF RESETB_C IN IO IN OUT IN IN SCLK/SCL SDIO/SDA CSB SDO SYNCB_C RESETB_C IN_SEL R310 R311 U301 1 20 VCCA VCCY 2 Y1 A1 3 Y2 A2 4 Y3 A3 5 Y4 A4 100 6 A5 Y5 100 7 A6 Y6 8 Y7 A7 9 10 EN C GND OFF GND SAMTECTSW10608GS3PIN DEFAULT ON 24LC00SN 2.2K R305 R304 2.2K VCC_BAR VCC NC4 SCL SDA SELECTS I2C OR SPI SERIAL_SDIO/SDA TSW-102-08-G-S PA0/INT0* PA1/INT1* PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/PKTEND PA7/FLAGD/SLCS* PB0/FD0 PB1/FD1 PB2/FD2 PB3/TXD1/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 USB CHIP B USB CONNECTOR R300 750 P300 1 4 5 2 3 6 DD+ 4-1734376-8 GND1 A C300 4700PF C R301 1MEG GND 40 41 42 43 44 45 46 47 25 26 27 28 29 30 31 32 52 53 54 55 56 1 2 3 USB_STATUS_U CSB_U RESETB_U SYNCB_U IN_SEL_U I2C_SDA R308 300 SDIO_U P306 1 2 3 DEFAULT CONNECTED VBUS SDA U300 SPI_SDIO SAMTECTSW10608GS3PIN DEFAULT SPI_SDIO B A SDIO_U SDO_U CR301 C SML-LX1206IW-TR (RED) SELECTS I2C OR SPI SERIAL_CLK GND SCL I2C_SCL SCLK_U P305 1 2 3 EEPROM ENA CR300 SML-LX1206IW-TR (RED) SDO_U SYNCB_U RESETB_U IN_SEL_U GND P301 1 2 3 ON P304 1 2 GND SERIAL_CLK SERIAL_SDIO/SDA CSB_U 3.3V U302 NC1 NC2 NC3 VSS 19 18 17 16 15 14 13 12 3.3V CY7C68013A-56PVXC VCC_BAR EEPROM GND 11 ADG3308BRUZ GND 3.3V Y8 A8 SCLK_U VCC_BAR GND C319 0.1UF VDD_UP 3.3V 12PF GND 3.3V SPI_SCLK SAMTECTSW10608GS3PIN DEFAULT SPI_SCLK CY7C68013A-56PVXC GND1 A A SCHEMATIC AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, AD9508 CUSTOMER EVALUATION DESIGN VIEW BOARD REV DRAWING NO. 30-8-2012 B 9508CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 PTD ENGINEER L.Xu 2 SIZE SCALE D NONE SHEET 1 3 OF 4 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION APPROVED DATE POWER SUPPLY SECTION D D DC TO DC STEP DOWN 6V TO 4V 6V WALL WART CONNECTION DEFAULT CONNECT PIN1 AND PIN2 YOU CAN USE EXTERNAL 4V POWER SUPPLY FROM PIN2 AND PIN3 L500 6VDC P508 6V_FILT SAMTECTSW10608GS3PIN L504 U500 5 GND VIN 1 BST 3 6 FB SW 4 R510 2 ADP2300AUJZ DNI GND 0 C GND 40.2K GND GND CR401 A C EN GND 10K 4.7UH R506 N R509 0 R507 C501 10UF C502 470UF B230A-13-F N P 0.1UF C500 470UF C504 1UF C515 P C503 10UF 1 2 3 1UH GND P500 1 2 3 PJ-102A C505 1UF 4VDC_IN C506 22UF GND C GND GND GND 3.3V/2.5V REGULATORS FOR AD9508 DEFAULT CONNECT PIN1 AND PIN2 YOU CAN USE EXTERNAL 3.3V/2.5V POWER SUPPLY FROM PIN2 AND PIN3 3.3V REGULATORS FOR USB P506 C523 10UF R525 0 EN ADP7104 GND GND R527 100K GND C524 10UF GND R402 23.7K 37.4K 1 4VDC_IN C522 1UF GND R401 3.3V GND U506 VCC_ARROW VDD_CORE VCC_CIRCLE 3 VDD_CORE C526 10UF P505 TSW-102-08-G-S VIN EN NC B 3.3V VOUT VCC_BAR L505 5 3V3_D 3.3V 1UH DEFAULT CONNECTED GND C527 10UF 4 2 ADP150AUJZ-3.3-R7 C525 10UF DEFAULT CONNECTED GND GND 0 P507 1 2 3 DNI TSW-102-08-G-S VDD_UP VDD_UP R526 GND P510 1 2 GND VDD_LDO 1 2 PAD 1 2 3 4 40.2K B VOUT SENSE GND NC PAD R400 8 VIN 7 PG 6 GND 5 4VDC_IN SAMTECTSW10608GS3PIN 1 2 3 U501 GND GND 2.5V SAMTECTSW10608GS3PIN ADJ MODE OF ADP7104 DEFAULT 2.5V A A SCHEMATIC AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, AD9508 CUSTOMER EVALUATION DESIGN VIEW BOARD REV DRAWING NO. 30-8-2012 B 9508CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 PTD ENGINEER SIZE SCALE L.Xu D NONE 2 SHEET 1 4 OF 4