8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED OUT0 D D OUT0_N R12 100 10K SI04 C11 .1UF 2 3 4 5 REF_SEL C8 GND 0.47UF C THIS SMA WILL SERVE AS DUAL USE FOR AN ALTERNATE CLK INPUT TP1 1 WHT R66 OUT1 OUT1_N 10K J2 1 GND 1.8V OUT 0-5 A OUT0 OUT0_N R16 C13 .1UF R13 3.3V_PLL1 3.3V REF C12 .1UF 1 2 3 P4 C P5 0 R3 49.9 .1UF VCXO_CTRL TBD0402 C5 TBD0402 R4 0 0.33UF R5 DNI .1UF DNI B C9 C10 3.3V_PLL2 R6 0 DNI 0.47UF C7 0.47UF VDD3_OUT_0_1 OUT1 OUT1_N VDD_1_8_OUT_0_1 OUT0 OUT0_N R21 10K 10K GND 1 STATUS0/SP0 36 35 34 33 32 31 30 29 28 27 26 25 STATUS0/SP0 STATUS1/SP1 1.8V OUT 0-5 OUT2 OUT2_N 3.3V OUT 0-3 OUT3 OUT3_N EEPROM_SEL PDB RESETB U1_J3 J7 1 STATUS1/SP1 STATUS_0_I2C_SP0 STATUS_1_I2C_SP1 VDD_1_8_OUT_2_3 OUT2 OUT2_N VDD3_OUT_2_3 OUT3 OUT3_N EEPROM_SEL PD_N RESET_N REF_TEST 5 4 3 2 J6 3.3V OUT 0-3 R19 R20 10K 10K 5 4 3 2 GND P6 3.3V OUT 0-3 R7 R8 10K 10K B P3 GND AD9524_PRELIM SYNCB 3.3V REF CSB_DUT SCLK/SCL_DUT SDIO/SDA_DUT SDO_DUT OUT5_N OUT5 3.3V OUT 4-5 OUT4_N OUT4 1.8V OUT 0-5 13 14 15 16 17 18 19 20 21 22 23 24 GND REFA REFA_N REFB REFB_N LF1_EXT_CAP OSC_CTRL OSC_IN OSC_IN_N LF2_EXT_CAP LDO_PLL2 VDD3_VCO LDO_VCO R18 1 2 3 C3 3.3V OUT 0-3 1 2 3 .1UF 1 2 3 4 5 6 7 8 9 10 11 12 U1 SYNC_N VDD3_REF CS_N_SDA SCLK_SCL SDIO SDO OUT5_N OUT5 VDD3_OUT_4_5 OUT4_N OUT4 VDD_1_8_OUT_4_5 60-800MHZ 3 C2 REFA REFA_N REFB REFB_N 1000PF 4 5 49.9 VC OUT+ OUTGND VCC R2 1 Y1 R1 GND 6 3.3V_PLL2 C4 49.9 0 DNI C22 0.33UF R11 .1UF C134 3.3V VCXO C6 TP2 1 WHT R17 1K 0 R9 3.3V_PLL1 PAD VDD3_CP LDO_PLL1 PLL1_OUT REF_SEL ZD_IN_N ZD_IN PAD 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 DNI 1 J3 2 3 4 5 GND A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC SCHEMATIC AD9524 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. 07/22/2009 C 9524EE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 RH 2 SCALE NONE SHEET 1 1 OF 5 8 6 7 2 3 4 5 1 REVISIONS REV PLACE TERMINATIONS CLOSE TO DUT 6 1 ADTT1-1 GND R24 2 J5 MABA-007159-000000 1 1 OUT1 REFB 100 3 5 2 3 4 5 5 C16 T1 4 49.9 SI02 R22 1 OUT1_N REFB_N PRI C17 4 3 2 3 GND 1 .1UF C31 4 3 2 OUT2_N -(NC) J25 1 O2N .1UF GND 6 1 ADTT1-1 C20 1 O5 REFA_N C32 J14 OUT5 .1UF C21 .1UF .1UF C33 4 3 2 OUT4_N J15 C J27 1 O5N 1 O4 4 3 2 OUT5_N J26 OUT4 100 2 R32 C 5 4 3 2 REFA 100 GND 3 R26 2 3 4 5 T2 4 49.9 SI01 R23 1 D J24 O2 SEC .1UF 4 2 C30 OUT2 .1UF J9 APPROVED ROUTE AS 50OHM SINGLE ENDED TRACES 100 T3 J8 DATE OUTPUT TERMINATIONS REFERENCE INPUTS R31 D DESCRIPTION 1 O4N .1UF 4 3 2 4 3 2 GND GND C27 GND .1UF 3.3V OUT 0-3 C18 100 R25 DNI .1UF C19 OUT3_N .1UF 16 15 1 2 PAD U11 J12 1 O3 VCC VT VREF D Q D_N Q_N PAD VEE 14 7 0 OUT3 C14 13 8 R35 .1UF 4 3 2 R30 220 12 11 GND GND C15 ADCLK905BCPZ-WP J13 O3N GND .1UF 1 4 3 2 R33 220 B B GND A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC SCHEMATIC AD9524 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. 07/22/2009 C 9524EE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 RH 2 SCALE NONE SHEET 2 1 OF 5 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED BYPASS CAPACITORS (FOR ONLY THE 9523) D DNI .1UF .1UF C53B C53 .1UF DNI .1UF C50B DNI 3.3V OUT 4-5 .1UF C50 .1UF C44B C44 3.3V OUT 0-3 D 1.8V OUT 0-5 A .1UF DNI C74B .1UF C74 .1UF DNI C72B .1UF C72 DNI .1UF .1UF C67B C67 DNI 1.8V OUT 0-5 .1UF C54B .1UF C54 DNI 3.3V REF .1UF C51B .1UF C51 DNI 3.3V_PLL2 .1UF .1UF C45B C45 3.3V_PLL1 GND C C DC TO DC STEP DOWN N P C46 470UF N C48 4.7UF C52 470UF CR2 1 3 BAT54 BAT54 C68 R47 10 6V_FILT B CR1 1 3 GND 17 28 1UF R41 4VDC 0 R82 DNI 28K 3 R37 Q2 1 0 PV IN FB2 GND 2 3 5 25 26 27 SYNC FREQ UV2 EN1 EN2 LDOSD 12 16 7 10 11 1000PF VREG R49 3 Q5 R27 10K 3 Q3 10 2 R52 C79 4.7UF A AN A LOG DEV CES C69 100NF 1 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR 2.0K IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC SCHEMATIC AD9524 ENGINEERING EVALUATION DESIGN VIEW 07/22/2009 OF ANALOG DEVICES. GND OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 6 C 9524EE01 SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS 7 REV DRAWING NO. OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS 2 MMBT3904 8 C81 1.0UF 1 1UF GND CR7 MMSZ4693T1G R28 28K R29 10K A 8.5V OVER PROTECTION CIRCUIT R50 GND VREG GND C 33UH C71 29 2.2VDC 10 100NF C70 L3 R54 DH2 DL2 COMP2 POK2 BST2 4 19 15 PAD GND 1UF C49 2 A 14 CSL2 13 SW2 9 SS2 6 R53 C78 C47 4.7UF C63 10000PF R55 4.99K C43 1.0UF GND 1000PF R43 22UF C42 100 2.21K C77 GND R39 R45 2 33PF 33UH C58 0 C76 4VDC R44 L1 1 1800PF DNI 13.3K Q4 15K DNI 0 2 GND R51 22 18 32 24 23 C75 R84 0 R42 DH1 DL1 COMP1 POK1 BST1 GND PGND1 PGND2 PAD R83 0 R38 4.99K 1 1800PF TRK1 TRK2 CSL1 SW1 SS1 FB1 3 .1UF 100 31 R46 VREG 8 2.21K 20 21 C64 30 10000PF 1 U7 C73 2.2VDC 3 100NF C60 R40 Q1 C1 1 2 R48 10 B 22UF GND P C80 1 2 3 6V_FILT 1UF 6VDC 6V_FILT L2 1UH P7 5 4 3 RH 2 SCALE NONE SHEET 3 1 OF 5 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED POWER TERMINALS D D 3.3V REGULATORS MAX I 300MA TP8 1 WHT L11 U5 ADP1713AUJZ-3.3-R7 1 IN 5 3 EN OUT 4 3.3V OUT 0-3 1UH 0 DNI BYP GND DNI C 3.3V OUT 4-5 C110 1UH 10UF 10UF C108 DNI TP9 1 WHT L12 10000PF C104 10UF C102 2 R68 10UF C114 C R15 0 R10 0 4VDC GND L8 TP10 1 WHT TP5 1 WHT 3.3V REF MAX I 150MA 0 DNI U4 ADP150AUJZ-3.3-R7 1 VIN 5 VOUT 3 1UH GND DNI DNI C113 1UH MAX I 150MA 4 10UF C84 EN NC 1.8V OUT 0-5 1UH MAX I 300MA GND 2 ADP1713AUJZ-3.3-R7 C97 Z5.530.3225.0 TP3 1 WHT L4 10UF GND 2.2VDC C23 1 2 B GND U2 ADP150AUJZ-1.8-R7 1 VIN 5 VOUT 3 P19 10UF DNI TP12 1 WHT 10UF DNI 3.3V_PLL1 C117 TP7 1 WHT R71 10UF L10 R67 C116 C107 10UF R14 10UF 2 10UF C99 B DNI 3.3V_PLL2 0 4 DNI 0 EN NC L9 TP11 1 WHT R73 TP6 1 WHT 0 1.8V REGULATOR R72 0 R70 0 1UH U3 1 IN 3 EN 4 GND L7 OUT 5 3.3V USB 1UH BYP GND 2 10UF C112 10UF A 1.8V OUT 0-5 A C26 GND 10UF 4 L5 1UH C25 EN NC 10UF C24 A TP4 1 WHT GND 10UF U12 ADP150AUJZ-1.8-R7 1 VIN 5 VOUT 3 C106 0 MAX I 150MA 10000PF R34 C101 C98 DNI 10UF 2 GND AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC SCHEMATIC AD9524 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. 07/22/2009 C 9524EE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 RH 2 SCALE NONE SHEET 4 1 OF 5 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED USB INTERFACE D D BYPASS CAPS FOR CY7C68013A 3.3V USB P11 SDIO/SDA_DUT 1 2 .1UF C129 .1UF C128 .1UF C126 .1UF C125 .1UF C124 .1UF C123 .1UF C122 C121 2.2UF SDIO/SDA P18 GND 1 2 3 (P10) (P10) (P14) (P18) (P6) (P34) (P24) (P39) SDO SDO_DUT 1 2 SDIO_U SDIO/SDA C131 12PF C118 P16 1M R64 EEPROM_SEL USB SCL GND CY7C68013A-56PVXC SDO STATUS1/SP1 CSB P13 RESETB C130 3.3V USB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 STATUS0/SP0 GND2 GND PDB .1UF 1 SDIO_U SDO SYNCB 3.3V USB P14 1 2 3 SAMTECTSW10608GS3PIN 19 P17 CSB CSB_DUT P15 GND GND B P20 TSW-113-23-L-D 1 GND R60 U10 200 R61 3 2 200 STATUS1/SP1 STATUS0/SP0 U10 CR3 A C CR4 GND LNJ312G8TRA (GREEN) A C LNJ312G8TRA (GREEN) 6 5 EEPROM_SEL R62 9 USB STATUS A SDIO/SDA SYNCB 10K 7914J-1-000E USB STATUS CSB_U RESETB_U SYNCB_U PDB_U REFSEL_U 4 PA0/INT0* PA1/INT1* PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/PKTEND PA7/FLAGD/SLCS* PB0/FD0 PB1/FD1 PB2/FD2 PB3/TXD1/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 40 41 42 43 44 45 46 47 25 26 27 28 29 30 31 32 52 53 54 55 56 1 2 3 VCC GND I0 O0 I1 O1 I2 O2 I3 O3 I4 O4 I5 O5 I6 O6 I7 O7 EN1_N EN2_N 10 B 2 3 4 5 6 7 8 9 10 74LVC541APW U9 18 17 16 CSB 15 14 13 PDB 12 REF_SEL 11 R65 20 U6 SCLK/SCL S2 GND 1 2 P2 REF_SEL GND SCLK/SCL SCLK/SCL_DUT 1 2 13 17 1 4 5 ROUTE TO A TEST POINT JUNK2 10UF C120 1UF 200 2 3 6 D+ D- GND C119 GND SCLK/SCL 1 2 AGND 100K R57 100K P12 C132 12PF GND A C LNJ312G8TRA (GREEN) 4700PF 1 2 3.3V USB XTALOUT DPLUS DMINUS CLKOUT/T1OUT IFCLK/T0OUT CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC SCL SDA RESET* WAKEUP RDY0/SLRD RDY1/SLWR RESERVED P1 C133 USB SDA 22 23 49 51 8 9 21 XTALIN CR6 R63 1 2 3 USB SCL VCC U6 12 11 15 16 5 20 36 37 38 C Y2 24.000MHZ 1 2 AVCC 24LC00SN R56 6 18 24 34 39 50 8 7 6 5 VCC NC4 SCL SDA 4 7 19 33 35 48 GND NC1 NC2 NC3 VSS 10 14 1 2 3 4 2.2K U8 2.2K R59 R58 S1 .1UF C 7914J-1-000E 3.3V USB U10 200 8 CR5 A C LNJ312G8TRA (GREEN) A CY7C68013A-56PVXC 13 GND U10 12 11 3.3V USB 14 AN A LOG DEV CES U10 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC SCHEMATIC AD9524 ENGINEERING EVALUATION DESIGN VIEW REV DRAWING NO. 07/22/2009 C 9524EE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS SN74LVC125APW 8 7 6 5 OF ANALOG DEVICES. 7 SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS GND OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 4 3 RH 2 SCALE NONE SHEET 5 1 OF 5