74ACT541 OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT541 is an advanced high-speed CMOS OCTAL BUS BUFFER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The 3 STATE control gate operates as two input AND such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the AC541 DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP 74ACT541B 74ACT541M T&R 74ACT541MTR 74ACT541TTR offers a pinout having inputs and outputs on opposite sides of the package. This device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levlels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS January 2001 1/9 74ACT541 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 19 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 10 20 G1, G2 A1 to A8 Output Enable Inputs Data Inputs Y1 to Y8 Data Outputs GND VCC NAME AND FUNCTION Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT G1 G2 An Yn H X L L X H L L X X H L Z Z H L X=Don’t care; Z=High Impedance ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 ± 20 V mA ± 20 mA IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) ± 50 mA ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -40 to 85 °C 8 ns/V V CC dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 1) VIN from 0.8V to 2.0V 2/9 Value 74ACT541 DC SPECIFICATIONS Test Condition Symbol VIH VIL V OH VOL Parameter 4.5 Low Level Input Voltage 5.5 4.5 High Level Output Voltage Low Level Output Voltage TA = 25 °C VCC (V) High Level Input Voltage Value VO = 0.1 V or VCC-0.1V -40 to 85 °C Min. Typ. 2.0 1.5 2.0 2.0 1.5 1.5 2.0 0.8 0.8 1.5 0.8 0.8 5.5 VO = 0.1 V or VCC-0.1V 4.5 IO=-50 µA 4.4 4.49 5.5 IO=-50 µA 5.4 5.49 4.5 IO =-24 mA 3.86 5.5 IO =-24 mA 4.86 4.5 IO=50 µA 0.001 5.5 IO=50 µA 0.001 4.5 IO =24 mA Max. Min. Unit Max. V V 4.4 5.4 V 3.76 4.76 0.1 0.1 0.1 0.1 0.36 0.44 V 5.5 IO =24 mA 0.36 0.44 Input Leakage Current 5.5 VI = VCC or GND ± 0.1 ±1 µA IOZ High Impedance Output Leakage Current 5.5 V I = VIH or VIL VO = VCC or GND ± 0.5 ±5 µA ICCT Max ICC/Input 5.5 1.5 mA ICC Quiescent Supply Current 5.5 VI = VCC - 2.1V VI = VCC or GND II IOLD IOHD Dynamic Output Current (note 1, 2) 5.5 0.6 80 µA VOLD = 1.65 V max 75 mA V OHD = 3.85 V min -75 mA 8 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Conditio n Symbol Parameter tPLH t PHL Propagation Delay Time tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time Value TA = 25 °C VCC (V) -40 to 85 °C Unit Min. Typ. Max. Min. Max. 5.0(*) 1.5 5.0 6.5 1.5 7.15 ns (*) 1.5 6.0 7.8 1.5 8.5 ns (*) 1.5 6.0 7.8 1.5 8.5 ns 5.0 5.0 (*) Voltage range is 5.0V ± 0.5V CAPACITANCE CHARACTERISTICS Test Conditio n Symbol Parameter VCC (V) Value TA = 25 °C Min. Typ. Max. -40 to 85 °C Min. Unit Max. Input Capacitance 5.0 4 pF C OUT Output Capacitance 5.0 8 pF CPD Power Dissipation Capacitance (note 1) 5.0 22 pF CIN 1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average current cqn be obtqined by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) 3/9 74ACT541 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZLH, tPLZ 2V CC tPZH, tPHZ Open C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 4/9 74ACT541 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 5/9 74ACT541 Plastic DIP-20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 6/9 74ACT541 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 7/9 74ACT541 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 8/9 MAX. 74ACT541 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom http://w ww.st.com 9/9