Evaluation Board User Guide UG-416 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADAU1962/ADAU1966 High Performance, Low Power, Multibit Sigma-Delta DACs PACKAGE CONTENTS On-board regulators derive 9 V, 5 V, and 3.3 V supplies for the ADAU1962/ADAU1966 and peripherals. The ADAU1962/ ADAU1966 can be controlled through either an I2C or SPI interface. A small external interface board, EVAL-ADUSB2EBZ, also called an USBi, connects to a PC USB port and provides either I2C or SPI access to the evaluation board through a ribbon cable. A graphical user interface (GUI) program, the Automated Register Window Builder, is provided for easy programming of the chip in a Microsoft® Windows® PC environment. The evaluation board allows demonstration and performance testing of most ADAU1962/ADAU1966 features, including high performance digital-to-analog converter (DAC) operation. ADAU1962/ADAU1966 evaluation board USBi control interface board USB cable D-sub 25-pin to (8) XLR male 12 V desktop supply OTHER SUPPORTING DOCUMENTATION ADAU1962 data sheet ADAU1966 data sheet EVALUATION BOARD OVERVIEW This user guide details the design and setup of the evaluation board for the ADAU1962/ADAU1966. Because the ADAU1962 is a 12-channel device and the ADAU1966 is a 16-channel device, the DAC 13 through DAC 16 outputs do not function on the ADAU1962 evaluation board. The evaluation board must be connected to an external 12 V dc power supply and ground; the board draws approximately 150 mA. The board has an S/PDIF receiver with RCA and optical connectors, as well as a discrete serial audio interface that is available on the Analog Devices, Inc. system development platform (SDP) interface. Analog outputs are accessible with two D-sub, 25-pin connectors using the professional audio standard. A single D-sub, 25-pin to XLR male cable is included with the board for connecting individual DAC channels to an audio system. EVALUATION BOARD DIAGRAM S/PDIF INTERFACE POWER SUPPLY DAC 9 TO DAC 16 CLOCK AND DATA ROUTING ADAU1966/ ADAU1962 DSP INTERFACE DAC 1 TO DAC 8 10717-001 CONTROL INTERFACE Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 28 UG-416 Evaluation Board User Guide TABLE OF CONTENTS Package Contents .............................................................................. 1 Powering the Board.......................................................................5 Other Supporting Documentation ................................................. 1 Reset for the Evaluation Board ....................................................5 Evaluation Board Overview ............................................................ 1 Setting Up the Master Clock (MCLK)........................................6 Evaluation Board Diagram .............................................................. 1 Crystal Operation ..........................................................................6 Revision History ............................................................................... 2 PLL Selection .................................................................................7 Setting Up the Evaluation Board .................................................... 3 Digital Audio Connections and Routing ...................................7 Standalone Mode .......................................................................... 3 Connecting Analog Audio Cables ..............................................8 I C and SPI Control ...................................................................... 4 Using the ADAU1962/ADAU1966 .............................................8 Automated Register Window Builder Software Installation .. 4 Schematics and Artwork ..................................................................9 2 Hardware Setup—USBi ............................................................... 4 REVISION HISTORY 1/14—Rev. 0 to Rev. A Added ADAU1962.............................................................. Universal Changes to Evaluation Board Overview Section and Figure 1 .. 1 5/12—Revision 0: Initial Version Rev. A | Page 2 of 28 Evaluation Board User Guide UG-416 SETTING UP THE EVALUATION BOARD STANDALONE MODE The ADAU1962/ADAU1966 have a standalone mode that allows the user to choose between a limited number of operation modes without the need for a control interface. Applying a jumper across JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high, enabling the standalone mode in the ADAU1962/ADAU1966. The SA_MODE selections are listed in Table 1. Table 1. Standalone Modes Pin(s) 42 43 44 45 32:31 Jumper Setting 0 1 0 1 0 1 0 1 00 01 10 11 Description Serial audio interface, master mode Serial audio interface, slave mode MCLK select: 256 × fS, PLL MCLK select: 384 × fS, PLL CM = 2.25 V (for AVDD = 5 V) CM = 1.50 V (for AVDD = 3.3 V) Serial audio interface, I2S mode Serial audio interface, TDM mode TDM4, pulse TDM8, pulse TDM16, pulse TDM8, 50% duty The ADAU1962/ADAU1966 evaluation board arrives configured for S/PDIF input. The S/PDIF receiver operates as a clock master, putting out an I2S stream at 256 × fS. For a quick startup, the ADAU1962/ADAU1966 are in standalone mode with the settings shown in Figure 2. Pin 42 is pulled high (1) and Pin 43 to Pin 45 are pulled low (0). According to Table 1, this puts the ADAU1962/ ADAU1966 in slave mode, running at 256 × fS, while common mode (CM) is set to 2.25 V and the audio serial port is in I2S mode. Notice in Figure 2 that the jumper for Pin 42 is assigned to 1 and that the other pins are assigned to 0. 10717-003 On the ADAU1962/ADAU1966 evaluation board, each of the four ADAU1962/ADAU1966 control port pins is brought to a block of jumpers, allowing each pin to be assigned to either the I2C port or the SPI port. In standalone mode, these jumpers can connect the individual pins to high or low to put the ADAU1962/ADAU1966 in the desired mode. Figure 3. SA_MODE—Master, 384 × fS, CM = 1.50 V, TDM 10717-002 Figure 3 shows the other options for each SA_MODE configuration pin; master mode, running at 384 × fS, CM set to 1.50 V, and the audio serial port in TDM mode. In the case where the ADAU1962/ADAU1966 are put in TDM mode, Pin 31 and Pin 32 can be pulled high or low to achieve the modes listed in Table 1. The correct pins are outlined in the top left corner of Figure 3, as DSD8 and DSD7. Figure 2. SA_MODE—Slave, 256 × fS, CM = 2.25 V, I2S Rev. A | Page 3 of 28 UG-416 Evaluation Board User Guide I2C AND SPI CONTROL The evaluation board can be configured for live control over the registers in the ADAU1962/ADAU1966. When the Automated Register Window Builder software is installed and the USBi control interface is plugged into the board, the software can control the ADAU1962/ADAU1966. For this configuration, the ADAU1962/ADAU1966 must be assigned to I2C mode using Address 00. See Figure 4 for the correct jumper positions. AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical interface for direct, live control of the ADAU1962/ADAU1966 registers. The GUI content for a specific part is defined in a part-specific .xml file; these files are included in the software installation. To install the Automated Register Window Builder software, follow these steps: 1. 2. 3. 4. Go to the ADAU1962 and ADAU1966 product pages and download the 64-Bit OS (ARWB_64BIT.zip) or 32-Bit OS (ARWB_32Bit.zip) file, which can be found under the Tools, Software, & Simulation Models section of the ADAU1962 and ADAU1966 product pages. Open the downloaded.zip file and extract the files to an empty folder on your PC. Install the Automated Register Window Builder by double-clicking setup.exe and following the prompts. A computer restart is not required. Copy the .xml file for the ADAU1962/ADAU1966 from the extraction folder into the C:\ProgramFiles\Analog Devices Inc\AutomatedRegWin folder, if it is not already installed. HARDWARE SETUP—USBi 10717-004 To set up the USBi hardware, follow these steps: Figure 4. ADAU1962/ADAU1966 I2C Control, Address 00 1. 2. 3. The Automated Register Window Builder controls the ADAU1962/ADAU1966 and is available for download under the Tools, Software, & Simulation Models section of the ADAU1962 and ADAU1966 product pages. In addition, the ADAU1962/ADAU1966 can be put into SPI mode for control by other means. See Figure 5 for the correct jumper positions. 10717-005 4. Figure 5. ADAU1962/ADAU1966 SPI Control Rev. A | Page 4 of 28 Plug the USBi ribbon cable into J12, the I2C/SPI port. Connect the USB cable to the PC and to the USBi. When prompted for drivers, follow these steps: a. Choose Install from a list or a specific location. b. Choose Search for the best driver in these locations. c. Check the box for Include this location in the search. d. Find the USBi driver C:\Program Files\Analog Devices Inc\AutomatedRegWin\USB drivers. e. Click Next. f. If prompted to choose a driver, select CyUSB.sys. g. If the PC is running Windows XP and a message appears saying that the software has not passed Windows logo testing, click Continue Anyway. Open the Automated Register Window Builder application and load the .xml file for the part on the evaluation board. Plug the 10-way ribbon cable on the USBi into the I2C/SPI port (J12) on the evaluation board. Evaluation Board User Guide UG-416 POWERING THE BOARD The ADAU1962/ADAU1966 evaluation board requires a power supply input of 12 V dc and ground to the power jack; 12 V draws ~150 mA at higher sample rates with all channels running. The on-board regulators provide 9.0 V, 5.0 V, and 3.3 V rails. The 9.0 V rail is derived from 12 V by a linear regulator; it provides voltage to the audio op amp in the active output filter for Channel 1 and Channel 2. The 5.0 V rail is derived from 12 V by a switching regulator; it can supply AVDD as well as IOVDD for the ADAU1962/ADAU1966 and other peripherals. The 3.3 V rail is derived from the 5.0 V supply by an LDO linear regulator; it provides voltage to AVDD and IOVDD as well as other active peripherals. Links are provided along each ADAU1962/ADAU1966 power rail to give access for current measurement (see Figure 8). These links also allow directly supplying voltage from an outside source. 10717-008 AVDD and IOVDD are selected on the board using 0 Ω, 0805 package resistors. Install only one resistor for each load, AVDD and IOVDD, as described in Figure 6. Figure 6 shows AVDD fed from 5.0 V and IOVDD fed from 3.3 V. Figure 8. ADAU1962/ADAU1966 Power Links RESET FOR THE EVALUATION BOARD 10717-006 The ADAU1962/ADAU1966 evaluation board has provision for resetting and powering down the ADAU1962/ADAU1966. S2 on the evaluation board, shown in Figure 9, is a momentary reset switch that pulls the master reset (MR) line low; this line controls the reset generator U10. MR is also connected to the USBi and SDP INTF connectors through steering diodes and protection resistors so that outside devices can control the reset state of the evaluation board, as shown in Figure 26. The power down jumper, JP5, allows the MR line to be tied low. The output of the reset generator drives the PU_/RST line. Figure 6. AVDD and IOVDD Selection Resistors The PU_/RST line is directly connected to two devices: the S/PDIF receiver and the ADAU1962/ADAU1966. A pull-down resistor holds the line low until the reset generator, U10, asserts the line high, as shown in Figure 26. The PU_/RST line is also connected to a pin on the SDP INTF through a steering diode and protection resistor, allowing external reset control. 10717-009 The ADAU1962/ADAU1966 have an internal voltage regulator that allows the user to derive DVDD and PLLVDD from the AVDD voltage source. The external PNP transistor, Q1, and passives, C36, C40 and R56, make the regulator circuit shown in Figure 7. Short both JP9 and JP11 to activate the circuit; JP9 supplies the emitter of the PNP, and JP11 powers the VSUPPLY pin (Pin 25) on the ADAU1962/ADAU1966. 10717-007 Figure 9. RESET Switch and Power-Down Jumper Figure 7. ADAU1962/ADAU1966 Internal Regulator Jumpers Rev. A | Page 5 of 28 UG-416 Evaluation Board User Guide SETTING UP THE MASTER CLOCK (MCLK) 10717-012 The MCLK routing on the evaluation board is handled by a block of jumpers, J5, allowing any one of four sources to be selected: SPDIF, SMA connector, active OSC, and INTF connector. The board comes with SPDIF selected, as shown in Figure 10. 10717-010 Figure 12. INTF Input Enabled and Selected Figure 10. SPDIF Selected as MCLK Source To route MCLK from the ADAU1962/ADAU1966 to the SDP interface, remove the shorting jumper from JP6 (MCLK_SEL); this changes the direction of the level translators and feeds a buffered version of the MCLKO signal from the ADAU1962/ADAU1966 to the EI3_MCLK pin on the SDP interface. CRYSTAL OPERATION The evaluation board has a 12.288 MHz active oscillator that can be selected by shorting the OSC_EN jumper, JP8, and selecting OSC on J5, as shown in Figure 11. 10717-011 The ADAU1962/ADAU1966 evaluation board is shipped without R49 on the board, effectively disabling the crystal circuit. For operation with a crystal, install a 150 Ω, 0402 resistor and remove any jumpers from J5. For permanent use of the crystal, remove the 0 Ω resistor, R39. 10717-013 Figure 11. Active OSC-Enabled and Selected as MCLK When using the SDP interface to add serial audio onto the evaluation board, MCLK can either be supplied by the SDP board, or it can be supplied by the MCLKO pin of the ADAU1962/ADAU1966. Figure 13. Crystal Circuit Near ADAU1962/ADAU1966 To route MCLK from the SDP interface to the ADAU1962/ ADAU1966, apply a shorting jumper across JP6 (MCLK_SEL), as shown in Figure 12; this sets the direction of the level translators on the board to receive an MCLK signal from the SDP interface, EI3 1A, Pin 119 (EI3_MCLK), as shown in Figure 28. Next, select INTF on JP5 to route the output of the MCLK level translator to the MCLKI pin of the ADAU1962/ADAU1966. Rev. A | Page 6 of 28 Evaluation Board User Guide UG-416 PLL SELECTION The PLL in the ADAU1962/ADAU1966 is very flexible, allowing the part to run from a wide range of either MCLK or LRCLK frequencies. It is also possible to shut the PLL off altogether and use the part in direct MCLK mode; functionality with no PLL is limited to 256 × fS. 10717-016 By default, the ADAU1962/ADAU1966 run from the PLL using MCLK as the clock source. The MCLK loop filter must be selected using JP2, as shown in Figure 14. Figure 16. S/PDIF Input Selector Switch, SW1 10717-014 A series of resistors is provided to set the functional mode of the S/PDIF receiver. By default, the S/PDIF receiver runs in master mode, 256 × fS, I2S format; consult the data sheet for the S/PDIF receiver to make changes to the hardware mode. Figure 14. MCLK Selection for PLL Loop Filter 10717-015 DLRCLK can be selected as the PLL clock source using the PLL and Clock Control Register 0, Register 0x00, Bits[7:6]. In this case, the LRCLK loop filter must be selected, as shown in Figure 15. If DLRCLK is selected as the PLL clock, there is no need for an MCLK signal. The jumpers shown in Figure 17 are set for the S/PDIF receiver to drive the DBCLK and DLRCLK clock ports and the eight DSDATAx lines of the ADAU1962/ADAU1966. JP22 selects the input to the buffer; the output of this buffer shows up on the righthand column of JP13 to JP20. The pins in the middle column of these jumpers are connected to the DSDATAx pins of the ADAU1962/ADAU1966 through the appropriate line termination. DBCLK and DLRCLK selections are made with JP10 and JP12, respectively, where the middle pins are connected to the DBCLK and DLRCLK pins of the ADAU1962/ADAU1966. Figure 15. LRCLK Selection for PLL Loop Filter DIGITAL AUDIO CONNECTIONS AND ROUTING The ADAU1962/ADAU1966 evaluation board has two separate inputs for digital audio signals: S/PDIF and SDP interface. 10717-017 The S/PDIF receiver can handle either of two options: COAX uses the RCA jack, J1, and OPT uses the Toslink jack, U1. The S/PDIF input is selected using S1, as shown in Figure 16. Figure 17. S/PDIF Data and Clock Routing The SDP interface, J6 and J8, make up a standard interconnect within Analog Devices. They provide for transfer of digital audio, clocks, and control between boards. For additional information, see the pinout included in the schematic in Figure 28. Rev. A | Page 7 of 28 UG-416 Evaluation Board User Guide Channel 1 and Channel 2 are also available as single-ended outputs on a stereo, 3.5 mm stereo jack, J14. The J9 and J10 jumpers assign the differential outputs of the DAC to either the passive differential output or the active single-ended filter. Figure 19 shows J9 and J10 set for the passive differential output available on the D-sub connector. 10717-019 Figure 18 shows the jumpers configuration for using the SDP interface connector as the digital audio source. JP22 is set so that the DSDATA1 source from the SDP interface is driving the buffer, and this buffer is connected to all eight/six DSDATAx inputs of the ADAU1962/ADAU1966. JP10 and JP12 are set for the ADAU1962/ADAU1966 to run in slave mode from clocks supplied by the SDP interface. 10717-020 Figure 19. Channel 1 and Channel 2 in Passive Differential Output Mode Figure 20. Channel 1 and Channel 2 in Active Single-Ended Output Mode 10717-018 Figure 20 shows J9 and J10 set for the active single-ended output available on the 3.5 mm TRS connector, J14. USING THE ADAU1962/ADAU1966 When the ADAU1962/ADAU1966 start in standalone mode, it is operational upon power up. Figure 18. SDP Interface DSDATA1 Distribution CONNECTING ANALOG AUDIO CABLES There are two forms of the analog outputs of the ADAU1962/ ADAU1966 evaluation board: differential outputs and singleended outputs. The differential outputs appear on through hole test points as well as on 25-way, female D-sub connectors. The pinout of these D-sub connectors follows the professional audio standard for eight differential signals on a single jack. A single 25-pin male D-sub to XLR male harness has been provided for testing and evaluation purposes. These cables are widely available on the open market. The differential outputs of the ADAU1962/ADAU1966 drive the connectors directly through a simple 1-pole RC filter and appropriate ac coupling. If the ADAU1962/ADAU1966 are not powered up in standalone mode, the USBi must be connected to set the appropriate registers to make the part operational. First, the ADAU1962/ADAU1966 must be activated using the PLL and Clock Control 0 register (Address 0x00) by setting the PUP bit (Bit 0) to 1 for master power-up. Next, using the DAC Control 0 register (Address 0x06) set the MMUTE bit (Bit 0) to 0 for normal operation. The ADAU1962/ADAU1966 now pass audio in its default mode: I2S, 256 × fS, slave mode, and CM = 2.25 V. If different settings are desired, it is recommended to program the custom settings before unmuting the part. Rev. A | Page 8 of 28 Rev. A | Page 9 of 28 DSP/FPGA Interface CLKs and DATA Control Jum pers Hardware Mode Optical and Coax In SPDIF Receiver IOVDD comes from DUT IOVDD CLKs OP AMP = 9v0 Linear Adjustable Connect to DUT Allows for Direct with Buffer SDATA Jumps BCLK, LRCLK Figure 21. ADAU1962/ADAU1966 Evaluation Board Block Diagram Schematic, Page 1 PD Jump Reset Switch COM Port Jumps SA_Mode Jumps Xistor PLLVDD DVDD 3v3 / 2v5 Int Reg AVDD = 5v0 / 3v3 IOVDD = 5v0 / 3v3 ADAU1966 EXT In DSP Intf CM Output on TP SE output on TRS Mini Jack DAC SE Out 1-2 Active Filter DAC Diff Out 1-2 Passive RC 1 Pole DAC Diff Out 3-8 Passive RC 1 pole Diff Outs on d-sub 25 DAC Diff Out 9-16 Passive RC 1 pole Buffered MCLKO 1 Pole Passive 1 Pole Active Active OSC Crystal for current measurement SPDIF MCLK Sources Single jumpers for each supply USBi Control port IOVDD and AVDD select using 0R00 3v3 = Linear Supply derived from 5v0 5v0 = Switching Supply Power Supply Regulators 3v3 for SPDIF Core Desktop Supply 24 VDC Input MAX! Input 12 VDC Evaluation Board User Guide UG-416 SCHEMATICS AND ARTWORK 10717-021 JP9 + C40 E TP53 ADAU1966 Voltage Regulator 1k50 R56 B Pins 32:31 Pin 45 Pin 44 Pin 43 Pin 42 VDRIVE [2] C36 [6,7] USBI_CLATCH_A [6,7] USBI_CCLK [6,7] USBI_SCL USBI_COUT [6,7] USBI_SDA [6,7] USBI_CDATA USBI_CDATA USBI_CDATA J11 TP50 VSENSE 2 4 6 8 10 12 14 16 18 20 22 24 26 28 HEADER_28WAY_UNSHROUD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 IOVDD Master SAI Slave SAI 256xFs, PLL 382xFs,PLL CM=2v25 CM=1v50 I2S TDM TDM4, Pulse TDM8, Pulse TDM16, Pulse TDM8, 50% Duty Cycle [2,6,7] 0 1 0 1 0 1 0 1 00 01 10 11 Stand-Alone Modes C126 10uF Q1 C C ZX5T953GTA [2] LF C17 390pF TP26 1966_CLATCH/ADDR0 1966_CCLK/SCL [2] 1966_COUT/SDA [2] 1966_CDATA/ADDR1 C20 5.6nF R27 562R MCLK [2] [2] JP2 A B PLLVDD C21 39nF R25 3k32 36 35 [5] 1966_DSDATA3 [5] 1966_DSDATA4 [5] 1966_DSDATA6 [6,9] PU_RST IOVDD JP21 SA_MODE 10k0 R138 [2]1966_CLATCH/ADDR0 [2]1966_CCLK/SCL [2]1966_COUT/SDA [2]1966_CDATA/ADDR1 [5] 1966_DSDATA8 [5] 1966_DSDATA7 47 46 45 44 43 42 31 32 33 34 37 [5] 1966_DSDATA5 38 [5] 1966_DSDATA2 19 18 17 14 15 16 PLLVDD C67 [5] 1966_DSDATA1 TP21 C125 10uF + 28 C41 C71 [5] 1966_DLRCLK JP4 C44 C47 U6 PU/RST SA_MODE CLATCH/ADDR0 CCLK/SCL COUT/SDA CDATA/ADDR1 DSDATA8 DSDATA7 DSDATA6 DSDATA5 DSDATA4 DSDATA3 DSDATA2 DSDATA1 DLRCLK DBCLK MCLKO XTALO MCLKI/XTALI PLLGND LF C127 10uF + 1966_IOVDD PLLVDD TP44 27 VSENSE [2] C53 IOVDD JP1 [5] 1966_DBCLK [6] MCLKO [6] XTALO [6] MCLKI/XTALI C18 2.2nF NP0 LRCLK VSENSE [2] 1966_DVDD VSENSE [2] [2] VSUPPLY JP7 TP25 ADAU1966WBSTZ 22 IOVDD 39 IOVDD JP11 See pages 5&6 for jumpers VSUPPLY [2] 25 VSUPPLY VDRIVE [2] 24 VDRIVE 23 VSENSE TP57 20 DVDD 29 DVDD 41 DVDD 21 DGND 26 DGND 30 DGND 40 DGND Enable AVDD DAC16P DAC16N DAC15P DAC15N DAC14P DAC14N DAC13P DAC13N DAC12P DAC12N DAC11P DAC11N DAC10P DAC10N DAC9P DAC9N DAC8P DAC8N DAC7P DAC7N DAC6P DAC6N DAC5P DAC5N DAC4P DAC4N DAC3P DAC3N DAC2P DAC2N DAC1P DAC1N TS_REF CM C42 + DAC1P [3] DAC1N [3] 63 62 59 60 1 2 10 11 8 9 C68 C134 10uF [4] [4] [4] [4] C65 + Figure 22. ADAU1962/ADAU1966 Evaluation Board, PLL LF Selection and Internal Regulator Schematic, Page 2 C130 10uF C45 0.47uF C133 10uF + TS_REF TP63 DAC16P [4] DAC16N [4] DAC15P DAC15N DAC14P DAC14N DAC13P [4] DAC13N [4] 6 7 4 5 [4] [4] [4] [4] DAC12P DAC12N 78 79 [4] [4] DAC9P [4] DAC9N [4] 72 73 DAC11P DAC11N [4] [4] DAC8P DAC8N 70 71 DAC10P DAC10N DAC7P [4] DAC7N [4] 66 67 68 69 76 77 DAC6P [4] DAC6N [4] 64 65 74 75 DAC4P [3] DAC4N [3] DAC5P [4] DAC5N [4] 56 57 DAC3P [3] DAC3N [3] C75 TP27 C131 10uF + DAC2P [3] DAC2N [3] CM C77 C128 10uF + 54 55 TP66 C37 C129 10uF + 52 53 50 51 AVDD JP3 DAC_BIAS1 DAC_BIAS2 DAC_BIAS3 DAC_BIAS4 49 AVDD1 58 AVDD2 3 AVDD3 12 AVDD4 AGND1 AGND2 AGND3 AGND4 48 61 80 13 Rev. A | Page 10 of 28 TP45 TP71 0.47uF C72 0.47uF C43 1966_AVDD 1966_AVDD [2] C76 0.47uF 10717-022 UG-416 Evaluation Board User Guide DAC2N [ 2] DAC2P [ 2] DAC1N [ 2] DAC1P [ 2] Rev. A | Page 11 of 28 DAC4N [ 2] DAC4P [ 2] DAC3N [ 2] TP85 TP84 TP83 237R R98 C87 2.7nF 237R R97 237R R96 C86 2.7nF + + + C88 10uF C89 10uF C90 10uF C91 10uF C92 10uF C93 10uF C94 10uF + + ANALOG_OUT2N [ 3] 237R + ANALOG_OUT2P [ 3] DAC3P [ 2] + C95 10uF ANALOG_OUT2N [ 3] J10 ANALOG_OUT1N [ 3] R95 ANALOG_OUT1N [ 3] ANALOG_OUT2P [ 3] J9 + TP82 237R R94 C85 2.7nF 237R R93 237R R92 C84 2.7nF ANALOG_OUT1P [ 3] TP81 TP80 TP79 237R R91 6 4 2 5 3 1 6 4 2 5 3 1 ANALOG_OUT1P [ 3] C150 10uF C148 + + + + 10uF VREF [ 3] C153 10uF C155 10uF VREF [ 3] 49k9 R100 49k9 49k9 R99 49k9 R101 49k9 R102 R103 49k9 49k9 R104 R105 49k9 R113 1k50 R114 1k50 R106 1k27 R107 1k27 R108 1k27 R115 1k27 R118 1k50 TP91 TP90 TP97 TP93 TP99 TP98 TP101TP100 3 2 + + - 7 1 OUT4N [ 4] OUT4P [ 4] OUT3N [ 4] OUT3P [ 4] OUT2N [ 4] OUT2P [ 4] OUT1N [ 4] OUT1P [ 4] 1.0nF C96 ADA4841-2YRZ O U7-A 1.0nF C101 ADA4841-2YRZ O U7-B 1.0nF R109 C97 5 6 1k50 - 1.0nF R119 C103 49R9 R110 49R9 R116 + + 47uF C98 47uF C102 R112 100k TP103 R117 100k TP107 TP43 U7-C ADA4841-2YRZ V+ V4 8 9VDD C100 1k50 R158 1k50 R159 RING TIP SLEEVE + C156 10uF C99 J14 VREF [ 3] 10717-023 TP78 Evaluation Board User Guide UG-416 Figure 23. ADAU1962/ADAU1966 Evaluation Board, DAC Outputs, CH1 and CH2 Active Buffer and CH1 to CH4 Passive Filters Schematic, Page 3 Rev. A | Page 12 of 28 Figure 24. ADAU1962/ADAU1966 Evaluation Board, RC Output Filters and D-Sub 25-Pin Connectors Schematic, Page 4 DAC10N [ 2] DAC10P [ 2] DAC9N [ 2] DAC9P [ 2] DAC8N [ 2] DAC8P [ 2] DAC7N [ 2] DAC7P [ 2] DAC6N [ 2] DAC6P [ 2] DAC5N [ 2] DAC5P [ 2] TP51 TP54 TP58 TP59 TP61 TP62 TP64 TP67 TP69 TP72 TP74 TP76 237R R5 4 2 .7 n F C4 8 237R R5 7 237R R6 0 2 .7 n F C5 4 237R R6 4 237R R6 8 2 .7 n F C6 1 237R R7 0 237R R7 4 2 .7 n F C7 3 237R R7 6 237R R8 0 2 .7 n F C7 9 237R R8 2 237R R8 6 C8 2 2.7nF 237R R8 8 + + + + + + + + + + + + C4 6 10uF C4 9 10uF C5 1 10uF C5 5 10uF C5 9 10uF C6 2 10uF C6 9 10uF C7 4 10uF C7 8 10uF C8 0 10uF C8 1 10uF C8 3 10uF R5 5 49k9 49k9 49k9 R5 8 R6 1 49k9 49k9 49k9 R6 5 R6 9 49k9 R7 1 R7 5 49k9 49k9 R7 7 R8 1 49k9 49k9 49k9 R8 3 R8 7 R8 9 TP49 TP47 TP55 TP52 TP68 TP65 TP73 TP70 TP77 TP75 TP89 TP87 OUT1 0 N [ 4] OUT1 0 P [ 4] OUT9 N [ 4] OUT9 P [ 4] OUT8 N [ 4] OUT8 P [ 4] OUT7 N [ 4] OUT7 P [ 4] OUT6 N [ 4] OUT6 P [ 4] OUT5 N [ 4] OUT5 P [ 4] DAC16N [ 2] DAC16P [ 2] DAC15N [ 2] DAC15P [ 2] DAC14N [ 2] DAC14P [ 2] DAC13N [ 2] DAC13P [ 2] DAC12N [ 2] DAC12P [ 2] DAC11N [ 2] DAC11P [ 2] TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP39 TP41 TP46 TP48 237R R3 0 2.7nF C2 3 237R R3 1 237R R3 2 2.7nF C2 4 237R R3 3 237R R3 4 2.7nF C2 5 237R R3 5 237R R3 6 2.7nF C2 6 237R R3 7 237R R4 0 2.7nF C3 1 237R R4 4 237R R4 7 2.7nF C3 8 237R R5 1 + + + + + + + + + + + + C8 10uF C9 10uF C1 3 10uF C1 4 10uF C1 5 10uF C1 6 10uF C1 9 10uF C2 2 10uF C3 0 10uF C3 2 10uF C3 5 10uF C3 9 10uF 49k9 R8 49k9 R2 2 49k9 R2 6 49k9 R2 9 49k9 R4 5 49k9 R5 2 49k9 R7 49k9 R1 9 49k9 R2 3 49k9 R2 8 49k9 R4 1 49k9 R4 8 TP10 TP7 TP12 TP11 TP18 TP16 TP22 TP19 TP37 TP24 TP42 TP40 OUT1 6 N [ 4] OUT1 6 P [ 4] OUT1 5 N [ 4] OUT1 5 P [ 4] OUT1 4 N [ 4] OUT1 4 P [ 4] OUT1 3 N [ 4] OUT1 3 P [ 4] OUT1 2 N [ 4] OUT1 2 P [ 4] OUT1 1 N [ 4] OUT1 1 P [ 4] [ 4 ] OUT1 6 N [ 4 ] OUT1 6 P [ 4 ] OUT1 5 N [ 4 ] OUT1 5 P [ 4 ] OUT1 4 N [ 4 ] OUT1 4 P [ 4 ] OUT1 3 N [ 4 ] OUT1 3 P [ 4 ] OUT1 2 N [ 4 ] OUT1 2 P [ 4 ] OUT1 1 N [ 4 ] OUT1 1 P [ 4 ] OUT1 0 N [ 4 ] OUT1 0 P [ 4 ] OUT9 N [ 4 ] OUT9 P [ 4 ] OUT8 N [ 4 ] OUT8 P [ 4 ] OUT7 N [ 4 ] OUT7 P [ 4 ] OUT6 N [ 4 ] OUT6 P [ 4 ] OUT5 N [ 4 ] OUT5 P [ 3 ] OUT4 N [ 3 ] OUT4 P [ 3 ] OUT3 N [ 3 ] OUT3 P [ 3 ] OUT2 N [ 3 ] OUT2 P [ 3 ] OUT1 N [ 3 ] OUT1 P 25 1 2 3 4 5 6 7 8 9 10 11 12 13 25 1 2 3 4 5 6 7 8 9 10 11 12 13 D- SUB2 5 _ ALT_ FEMALE_ PCMOUNT 14 15 16 17 18 19 20 21 22 23 24 J3 D- SUB2 5 _ ALT_ FEMALE_ PCMOUNT 14 15 16 17 18 19 20 21 22 23 24 J7 10717-024 UG-416 Evaluation Board User Guide Figure 25. ADAU1962/ADAU1966 Evaluation Board, BCLK, LRCLK, and SDATA Jumpers and Routing Schematic, Page 5 8416_SDATA [7] INTF_DSDATA1 [7] INTF_DSDATA2 [7] INTF_DSDATA3 [7] INTF_DSDATA4 [7] INTF_DSDATA5 [7] INTF_DSDATA6 [7] INTF_DSDATA7 [7] INTF_DSDATA8 [9] B A C7 2 IOVDD JP22 A [9] 8416_LRCLK [7]INTF_DLRCLK [9] 8416_BCLK 1 Y OE U18 4 SN74LVC1G125DRLR JP10 A B JP12 A B JP13 A B JP14 A B JP15 A B JP16 A B JP17 A B JP18 A B JP19 A B Rev. A | Page 13 of 28 JP20 A B [7] INTF_DBCLK R141 C141 2.2pF 33R2 DSDATA1 DSDATA2 DSDATA3 DSDATA4 DSDATA5 DSDATA6 DSDATA7 DSDATA8 DLRCLK DBCLK 68R1 68R1 68R1 68R1 68R1 68R1 68R1 68R1 33R2 33R2 R90 R85 R84 R79 R78 R73 R72 R67 R66 R62 4.7pF C70 4.7pF C66 4.7pF C64 4.7pF C63 4.7pF C60 4.7pF C58 4.7pF C57 4.7pF C56 2.2pF C52 2.2pF C50 33R2 33R2 R63 R59 1966_DSDATA1 [2] 1966_DSDATA2 [2] 1966_DSDATA3 [2] 1966_DSDATA4 [2] 1966_DSDATA5 [2] 1966_DSDATA6 [2] 1966_DSDATA7 [2] 1966_DSDATA8 [2] 1966_DLRCLK [2] 1966_DBCLK [2] Evaluation Board User Guide UG-416 10717-025 [ 2,7] C3 3 L7 Rev. A | Page 14 of 28 USBI _CLATCH_A J4 R46 10k0 1 U5 4 R129 49R9 OUTPUT 49R9 C28 10pF R38 49R9 C124 10pF R43 R132 49R9 OMCK_ FEED [ 9] 8416_MCLKI [ 9] 0R00 R155 3k 01 2 4 6 8 10 J12 HEADER_10WAY_POL 1 3 5 7 9 J5 1 3 5 7 MCLK Source 2 4 6 8 Y1 22pF C34 R39 USBI _ 5 V0 0 [ 7 ] D10 R49 0R00 150R XTALO [ 2] R5 0 1 M0 0 MCLKI / XTALI [ 2] MCLK sources 22pF 12.288MHz C29 TP38 USBI _CDATA [ 2,7] MBR0 5 3 0 T1 G MR [ 6,8] MR line comes from USBi Board Reset USBi I nt erface R111 3k 01 I OVDD USBi or Aardvark 3 R157 10k 0 GND 2 OE VDD R42 EI 3_MCLKI [ 7] OSC_CPPFXC7- 12.288MHZ_7MMX5MM_SMD JP8 [ 2,7] USBI _SCL [ 2,7] USBI _SDA [ 2 , 7 ] USBI _ COUT [ 2,7] USBI _CCLK I OVDD C2 7 I OVDD U10 GND RESET MR ADM811R VCC Reset 1 4 CLKOUT Feed MCLKO [ 2] 49R9 R53 2 3 C1 1 1 TP20 R126 100k I OVDD 2 A 1 Y 49R9 R24 S2 4 2 SN74LVC1G125DRLR 4 PU_RST [ 2,9] 1 3 OE U4 Power down [ 6,8] MR J2 EI 3 _ MCLKO [ 7 ] UG-416 Evaluation Board User Guide Figure 26. ADAU1962/ADAU1966 Evaluation Board, MCLK Source, USBi Interface, CLKOUT Feed, and Reset Generator Schematic, Page 6 10717-026 JP5 C137 MCLK_SEL [7] [7,8] EI3_MCLK 2 A SN74LVC1G125DRLR C138 U14 1 10k0 R130 EI3_IOVDD [8] EI3_CCLK [8] EI3_CLATCH_C [8] EI3_CLATCH_B [8] EI3_CDATA [8] EI3_CLATCH_A Y 4 10k0 R139 EI3_IOVDD VCCB VCCA VCCB DIR OE A1 B1 A2 B2 A3 U13 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 GND GND GND 24 23 22 21 20 19 18 17 16 15 14 13 MCLK_SEL [7] EI3_IOVDD R147 IOVDD 10k0 R134 EI3_IOVDD SN74LVCH8T245DBR_8BITLVLSHFT 24 1 VCCB VCCA 23 2 VCCB DIR 22 3 OE A1 21 4 B1 A2 20 5 B2 A3 19 6 U16 B3 A4 18 7 B4 A5 17 8 B5 A6 16 9 B6 A7 15 10 B7 A8 14 11 B8 GND 13 12 GND GND SN74LVCH8T245DBR_8BITLVLSHFT 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R135 33R0 C135 49R9 49R9 49R9 49R9 R151 R148 R152 TP95 TP96 USBI_CLATCH_A [2,6] USBI_CDATA [2,6] USBI_CLATCH_B USBI_CLATCH_C R145 3k32 EI3_SPI_EN INTF_DSDATA1 [5] INTF_DSDATA2 [5] INTF_DSDATA3 [5] INTF_DSDATA4 [5] INTF_DSDATA5 [5] INTF_DSDATA6 [5] INTF_DSDATA7 [5] INTF_DSDATA8 [5] USBI_CCLK [2,6] R150 49R9 EI3_MCLKI [6] C145 EI3_DSDATA1 EI3_DSDATA2 EI3_DSDATA3 EI3_DSDATA4 EI3_DSDATA5 EI3_DSDATA6 EI3_DSDATA7 EI3_DSDATA8 R137 1k50 R146 [8] EI3_DBCLK0 [8] EI3_DBCLK1 [8] EI3_DBCLK2 [8] EI3_DBCLK3 [8] EI3_DLRCLK0 [8] EI3_DLRCLK1 [8] EI3_DLRCLK2 [8] EI3_DLRCLK3 [7] MCLK_SEL [7,8] EI3_MCLK EI3_IOVDD 33R0 10k0 16 15 14 13 12 11 10 9 VCCB VCCA VCCB DIR OE A1 B1 A2 B2 A3 U17 B3 A4 B4 A5 B5 A6 A7 B6 B7 A8 B8 GND GND GND U12 1 VCCA 2 SCLA 3 SDAA 4 GND U15 8 VCCB 7 SCLB 6 SDAB 5 EN 24 IOVDD 23 IOVDD 22 21 20 19 18 17 16 15 14 13 49R9 R144 10k0 IOVDD SN74LVCH8T245DBR_8BITLVLSHFT 1 2 3 4 5 6 7 8 9 10 11 12 PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8 R136 1 2 3 4 5 6 7 8 R140 C139 Y A 2 OE 4 [8] EI3_COUT SN74LVC1G126DRLR 1 USBI_5V00 [6] [8] EI3_SCL [8] EI3_SDA C140 [8] [8] [8] [8] [8] [8] [8] [8] OE 10k0 R127 R128 5 3 2 EI3_IOVDD R143 C142 EI3_IOVDD C122 IOVDD C136 49R9 A1 49R9 DIR A2 U11 B2 B1 6 7 IOVDD R142 10k0 R149 IOVDD GND C146 USBI_COUT [2,6] EI3_MCLKO [6] USBI_SCL [2,6] USBI_SDA [2,6] INTF_DLRCLK [5] INTF_DBCLK [5] SN74LVC2T45DCTR_2BITLVLSHFT C120 10k0 JP6 C123 1 VCCA 8 VCCB Rev. A | Page 15 of 28 4 EI3_IOVDD Evaluation Board User Guide UG-416 Figure 27. ADAU1962/ADAU1966 Evaluation Board, Level Shift and Clock Direction Control Schematic, Page 7 10717-027 Rev. A | Page 16 of 28 [6] MR Figure 28. ADAU1962/ADAU1966 Evaluation Board, SDP Interface Connectors Schematic, Page 8 Schottky D9 [7] [7] [7] [7] R133 R131 EI3_CLATCH_C EI3_CLATCH_B EI3_DSDATA2 EI3_DSDATA4 5V0DD 49R9 OPEN J6 26 27 28 95 94 93 26 EI3_CLATCH_A RESET_OUT' 73 72 71 70 69 68 67 66 65 50 51 52 53 54 55 56 71 70 69 68 67 66 65 50 51 52 53 54 55 56 EI3 1B 61 60 61 60 EI3 1A 62 59 62 59 63 58 63 58 64 74 49 72 49 57 75 48 73 48 64 76 47 74 47 57 77 46 75 46 78 79 45 43 76 [7] 45 EI3_SCL 42 80 78 79 81 SDA0' SCL0' 82 EI3_SDA [7] 41 83 84 80 [7] 85 40 38 86 EI3_DBCLK2 88 87 EI3_DLRCLK2 EI3_DSDATA5 89 81 EI3_CCLK 82 35 36 37 [7] [7] [7] 34 [7] EI3_DLRCLK3 EI3_DBCLK3 EI3_DSDATA7 90 91 EI3_IOVDD 92 39 EI3_COUT EI3_CDATA 83 84 85 86 EI3_DBCLK0 87 32 33 EI3_DSDATA6 [7] SPORT3_D1 SPORT2_D1 93 94 44 SDA0' SCL0' SPI0_SEL_A SPI0_MOSI SPI0_MISO SPI0_CLK EI3_DLRCLK0 EI3_DSDATA1 89 88 EI3_DLRCLK1 90 SPORT3_CLK SPORT3_D0 SPORT3_FS SPORT2_FS SPORT2_D0 SPORT2_CLK 77 RESET_OUT' SPI0_SEL_B SPI0_SEL_C SPORT1_D1 SPORT0_D1 SPORT1_CLK SPORT1_D0 SPORT1_FS SPORT0_FS SPORT0_D0 SPORT0_CLK 102 103 104 105 106 107 108 109 112 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 [7] 25 96 25 [7] 24 97 24 31 23 98 23 [7] 22 99 22 [7] 21 100 21 30 20 101 20 [7] 19 102 19 EI3_DSDATA3 18 103 18 91 95 17 104 17 29 96 16 105 16 [7] 97 15 106 15 EI3_DBCLK1 98 14 107 14 92 99 13 108 13 HIROSE_FX8-120S-SV(21)_SOCKET 100 12 109 12 HIROSE_FX8-120S-SV(21)_SOCKET 101 11 110 11 27 110 10 111 10 J8 111 9 112 113 7 8 114 113 8 114 115 116 117 7 6 115 6 118 119 120 9 5 116 EI3_DSDATA8 2 1 3 5 OPEN 4 R156 117 EI3_MCLK [7] 5V0DD 4 118 120 119 DAU_MCLK 2 3 1 EI3_IOVDD [7] [7] [7] [7] [7] [7] C132 47uF + UG-416 Evaluation Board User Guide 10717-028 C112 CTP-021A-S-YEL J1 3 GND U1 TO RX147L(FT) D VD D Rev. A | Page 17 of 28 R6 + 1.0nF C10 10uF C12 10nF 10nF IO VD D C5 C6 22nF PU _RST [2,6] 5 2 C3 S1 C2 3k01 75R0 6 3 1 D PD T Slide 4 1 R5 OUT 10k0 R4 9 10 11 12 13 3 2 1 8 5 4 L4 RST Figure 29. ADAU1962/ADAU1966 Evaluation Board, S/PDIF Receiver Schematic, Page 9 TX 22 7 C U RC BL N V/R ERR AU D IO 96KH Z O M CK SD O U T O LRCK O SCLK RM CK VL 21 DGND CS8416 U2 VD 23 AG N D RXSEL1 RXSEL0 TXSEL1 TXSEL0 RXP1 RXP2 RXP3 FILT RXN RXP0 VA 6 IO VD D L1 C11 15 16 19 18 17 14 25 26 28 27 24 20 U3-B U3-C C4 4 2Y 5 PH D ET RATE Norm D efault EM PH O ff D efault On 47k5 RS3 O M C K _ F E E D [6 ] RS7 R125 47k5 47k5 H igh 10k0 R20 10k0 74HC04D-T 74HC04D-T 2A 3 6 3Y 3A R9 C110 R3 392R Red D iffused U3-F 3V3D D D4 Error R2 392R RS1 47k5 ER RO RS NVERR D efault RERR 74HC04D-T L3 2 12 6Y 6A 13 8 4Y G reen D iffused U3-D U3-E D3 R1 392R 74HC04D-T D2 1 RS2 47k5 R10 R 12 150R R11 150R 1 SFSEL0 0 D efault RS6 47k5 00 01 10 11 = = = = LJ 24bit I2S 24bit RJ 24bit D irect AES SFSEL [1:0] RS5 47k5 RM C K Freq 256xFs D efault 128xFs 8416_SD ATA [5] 8416_LRCLK [5] 8416_BCLK [5] 8416_M CLKI[6] |-------- SERIAL PO RT Form at -------| SFSEL1 0 D efault 150R R21 74HC04D-T 150R SERIAL PO RT Control SLAVE D efault M ASTER RS4 47k5 Yellow D iffused U3-A IO VD D >88kHz 3V3D D Valid Audio 74HC04D-T 2 1Y 1A 1 4A 9 10 5Y 5A 11 IO VD D IO VD D Evaluation Board User Guide UG-416 10717-029 Rev. A | Page 18 of 28 J13 2 1 3 TP88 TP2 GND +12VDC MAX D1 C1 +12VDC L5 C107 47uF + 600 Ohm @ 100 MHz 600 Ohm @ 100 MHz L2 5V0DD C105 600 Ohm @ 100 MHz + C118 47uF + Figure 30. ADAU1962/ADAU1966 Evaluation Board, Power Supply Schematic, Page 10 C106 68nF R120 1k15 C116 C144 47uF IN C104 390pF 2 C147 + 5 6 7 8 10uF U8 FB BIAS BOOST SWITCH U19 1 4 3 2 1 R154 R153 178k 27k4 C109 0.47uF 10k2 R121 402R R123 243R R124 32k4 R122 2 C119 47uF C108 MSS12778-223MLB + C117 BAT54T1G D8 L6 1N5819HW-7-F D7 22uH 1 3v3 Linear Supply 3V3DD ADJ OUT op amp supply = 9v 5v0 Switching Supply ADP3050ARZ COMP SD GND IN 3 LM317MDT OUT C115 1 ADJ U9 IN ON/OFF 4 8 5 2 GND 3 GND 6 GND 7 GND L8 C113 47uF C114 TP9 TP8 C151 100uF 47uF C149+ 9VDD 5V0DD 3V3DD Green Diffused D6 Green Diffused TP60 TP86 TP92 TP5 R18 475R D5 R13 475R OPEN AVDD IOVDD C152 C154 C121 R16 TP1 R17 TP3 TP17 TP6 0R00 OPEN TP15 TP14 TP4 TP13 TP56 TP23 TP94 TP36 TP106TP105TP102TP104 AVDD IOVDD C143 Plane decoupling It is very important that each load only have one 0R00 installed R15 0R00 R14 UG-416 Evaluation Board User Guide 10717-030 UG-416 10717-031 Evaluation Board User Guide Figure 31. ADAU1962/ADAU1966 Evaluation Board, Top Assembly Rev. A | Page 19 of 28 Evaluation Board User Guide 10717-032 UG-416 Figure 32. ADAU1962/ADAU1966 Evaluation Board, Top Layer Copper Rev. A | Page 20 of 28 UG-416 10717-033 Evaluation Board User Guide Figure 33. ADAU1962/ADAU1966 Evaluation Board, L2 Ground Rev. A | Page 21 of 28 Evaluation Board User Guide 10717-034 UG-416 Figure 34. ADAU1962/ADAU1966 Evaluation Board, L3 Power Rev. A | Page 22 of 28 UG-416 10717-035 Evaluation Board User Guide Figure 35. ADAU1962/ADAU1966 Evaluation Board, Bottom Copper Rev. A | Page 23 of 28 Evaluation Board User Guide 10717-036 UG-416 Figure 36. ADAU1962/ADAU1966 Evaluation Board, Bottom Assembly Rev. A | Page 24 of 28 Evaluation Board User Guide UG-416 NOTES Rev. A | Page 25 of 28 UG-416 Evaluation Board User Guide NOTES Rev. A | Page 26 of 28 Evaluation Board User Guide UG-416 NOTES Rev. A | Page 27 of 28 UG-416 Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. 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ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG10717-0-1/14(A) Rev. A | Page 28 of 28