Octal, 16-Bit nanoDAC+ with SPI Interface AD5676 Data Sheet FEATURES GENERAL DESCRIPTION High performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy implementation User selectable gain of 1 or 2 (GAIN pin/gain bit) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Robust 2 kV HBM and 1.5 kV FICDM ESD rating 20-lead, TSSOP and LFCSP RoHS-compliant packages The AD5676 is a low power, octal, 16-bit buffered voltage output digital-to-analog converter (DAC). The device includes a gain select pin, giving a full-scale output of VREF (gain = 1) or 2 × VREF (gain = 2). The AD5676 DAC operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5676 is available in 20-lead TSSOP and LFCSP packages. The internal power-on reset circuit and the RSTSEL pin of the AD5676 ensure that the output DACs power up to zero scale or midscale and then remain there until a valid write takes place. The AD5676 contains a per channel power-down mode that typically reduces the current consumption of the device to 1 µA. The AD5676 employs a versatile serial peripheral interface (SPI) that operates at clock rates up to 50 MHz, and contains a VLOGIC pin intended for 1.8 V to 5.5 V logic. Table 1. Octal nanoDAC+® Devices APPLICATIONS Interface SPI Optical transceivers Base station power amplifiers Process control (PLC input/output cards) Industrial automation Data acquisition systems I2 C Reference Internal External Internal External 16-Bit AD5676R AD5676 AD5675R AD5675 12-Bit AD5672R Not applicable AD5671R Not applicable PRODUCT HIGHLIGHTS 1. 2. 3. High relative accuracy (INL) 16-bit: ±3 LSB maximum. −40°C to +125°C temperature range. 20-lead, TSSOP and LFCSP RoHS-compliant packages. FUNCTIONAL BLOCK DIAGRAM VLOGIC VREF VDD AD5676 DAC REGISTER STRING DAC 0 BUFFER INPUT REGISTER DAC REGISTER STRING DAC 1 BUFFER INPUT REGISTER DAC REGISTER STRING DAC 2 BUFFER INPUT REGISTER DAC REGISTER STRING DAC 3 BUFFER SDI INPUT REGISTER DAC REGISTER STRING DAC 4 BUFFER SDO INPUT REGISTER DAC REGISTER STRING DAC 5 BUFFER LDAC INPUT REGISTER DAC REGISTER STRING DAC 6 BUFFER RESET INPUT REGISTER DAC REGISTER STRING DAC 7 BUFFER SCLK SYNC INTERFACE LOGIC POWER-ON RESET GAIN x1/x2 RSTSEL GAIN VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 POWER-DOWN LOGIC GND 12549-001 INPUT REGISTER Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5676 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Standalone Operation ................................................................ 21 Applications ....................................................................................... 1 Write and Update Commands .................................................. 21 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 21 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 22 Functional Block Diagram .............................................................. 1 Power-Down Operation ............................................................ 22 Revision History ............................................................................... 2 Load DAC (Hardware LDAC Pin) ........................................... 23 Specifications..................................................................................... 3 LDAC Mask Register ................................................................. 23 AC Characteristics........................................................................ 5 Hardware Reset (RESET) .......................................................... 24 Timing Characteristics ................................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 24 Daisy-Chain and Readback Timing Characteristics ............... 7 Amplifier Gain Selection on LFCSP Package ......................... 24 Absolute Maximum Ratings............................................................ 8 Applications Information .............................................................. 25 Thermal Resistance ...................................................................... 8 Power Supply Recommendations............................................. 25 ESD Caution .................................................................................. 8 Microprocessor Interfacing ....................................................... 25 Pin Configuration and Function Descriptions ............................. 9 AD5676 to ADSP-BF531 Interface .......................................... 25 Typical Performance Characteristics ........................................... 11 AD5676 to SPORT Interface ..................................................... 25 Terminology .................................................................................... 17 Layout Guidelines....................................................................... 25 Theory of Operation ...................................................................... 19 Galvanically Isolated Interface ................................................. 26 Digital-to-Analog Converter .................................................... 19 Outline Dimensions ....................................................................... 27 Transfer Function ....................................................................... 19 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 19 Serial Interface ............................................................................ 20 REVISION HISTORY 10/15—Rev. A to Rev. B Added 20-Lead LFCSP....................................................... Universal Changes to Features Section, General Description Section, Table 1, Product Highlights Section, and Figure 1 ....................... 1 Changes to Table 2 ............................................................................ 3 Deleted Figure 5; Renumbered Sequentially................................. 8 Change to Table 5 ............................................................................. 8 Added Table 6; Renumbered Sequentially .................................... 8 Change to Table 7 ............................................................................. 9 Added Figure 6 and Table 8 ........................................................... 10 Change to Figure 10 to Figure 12 ................................................. 11 Change to Figure 13 to Figure 18 ................................................. 12 Changes to Figure 19, Figure 20, and Figure 22 ......................... 13 Change to Figure 25, Figure 28, and Figure 30 ........................... 14 Change to Figure 31, Figure 34, Figure 35, and Figure 36 ........ 15 Change to Figure 37 and Figure 38 .............................................. 16 Changes to Transfer Function Section and Output Amplifiers Section .............................................................................................. 19 Change to Table 9 ........................................................................... 20 Changes to Write to and Update DAC Channel n (Independent of LDAC) Section ........................................................................... 21 Changes to Readback Operation Section .................................... 22 Changes to LDAC Mask Register Section and Table 14 ............ 23 Changes to Reset Select Pin (RSTSEL) Section .......................... 24 Added Amplifier Gain Selection on LFCSP Section, Table 16, and Table 17 .................................................................................... 24 Added Figure 53, Outline Dimensions ........................................ 27 Changes to Ordering Guide .......................................................... 27 2/15—Rev. 0 to Rev. A Changes to Table 2.............................................................................3 Change to RESET Pulse Activation Time Parameter, Table 4 .....6 Change to Terminology Section ................................................... 17 Changes to Transfer Function Section and Output Amplifiers Section.............................................................................................. 19 Changes to Hardware Reset (RESET) Section ............................ 24 Changes to Ordering Guide .......................................................... 27 10/14—Revision 0: Initial Version Rev. B | Page 2 of 27 Data Sheet AD5676 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications −40°C to +125°C, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE1 Resolution Relative Accuracy (INL)2 Min Zero Code Error2 Offset Error2 Full-Scale Error2 Gain Error2 Total Unadjusted Error (TUE) Offset Error Drift2, 3 DC Power Supply Rejection Ratio (PSRR)2, 3 DC Crosstalk2, 3 Reference Input Range Reference Input Impedance Test Conditions/Comments Bits LSB LSB LSB Gain = 1 Gain = 2 Gain = 1 16 ±1.8 ±1.7 ±0.7 ±3 ±3 ±1 ±0.5 0.8 −0.75 −0.1 −0.018 −0.013 +0.04 −0.02 +0.03 +0.006 ±1 0.25 ±1 4 ±6 ±4 ±0.28 ±0.14 ±0.24 ±0.12 ±0.3 ±0.25 ±0.5 0.8 −0.75 −0.1 −0.018 −0.013 +0.04 −0.02 +0.03 +0.006 ±1 0.25 ±1 1.6 ±2 ±1.5 ±0.14 ±0.07 ±0.12 ±0.06 ±0.18 ±0.14 LSB mV mV mV % of FSR % of FSR % of FSR % of FSR % of FSR % of FSR µV/°C mV/V ±2 ±2 µV ±3 ±2 ±3 ±2 µV/mA µV VREF 2 × VREF 15 183 183 V V mA nF nF kΩ µV/mA 0 0 VREF 2 × VREF 15 177 177 µV/mA 40 25 2.5 40 25 2.5 mA Ω µs 398 789 398 789 µA µA V V kΩ kΩ 2 10 1 REFERENCE INPUT Reference Input Current Unit ±8 ±8 ±1 2 10 Short-Circuit Current5 Load Impedance at Rails6 Power-Up Time B Grade Typ Max ±1.8 ±1.7 ±0.7 0 0 Output Current Drive Capacitive Load Stability Resistive Load4 Load Regulation Min 16 Differential Nonlinearity (DNL)2 OUTPUT CHARACTERISTICS3 Output Voltage Range A Grade Typ Max 1 1 1 VDD VDD/2 14 7 1 1 VDD VDD/2 14 7 Rev. B | Page 3 of 27 Gain = 2 Gain = 1 or gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 DAC code = midscale, VDD = 5 V ± 10% Due to single channel, fullscale output change Due to load current change Due to powering down (per channel) Gain = 1 Gain = 2 RL = ∞ RL = 1 kΩ 5 V ± 10%, DAC code = midscale, −30 mA ≤ IOUT ≤ +30 mA 3 V ± 10%, DAC code = midscale, −20 mA ≤ IOUT ≤ +20 mA Exiting power-down mode, VDD = 5 V VREF = VDD = VLOGIC = 5.5 V, gain = 1 VREF = VDD = VLOGIC = 5.5 V, gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 AD5676 Parameter LOGIC INPUTS3 Input Current Input Voltage Low, VINL High, VINH Pin Capacitance LOGIC OUTPUTS (SDO)3 Output Voltage Low, VOL High, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD IDD Normal Mode7 All Power-Down Modes8 Data Sheet Min A Grade Typ Max Min B Grade Typ Max Per pin ±1 µA 0.3 × VLOGIC 0.3 × VLOGIC V V 0.7 × VLOGIC 3 3 0.4 VLOGIC − 0.4 pF 0.4 VLOGIC − 0.4 4 4 5.5 3 3 3 3 5.5 5.5 2.7 VREF + 1.5 Test Conditions/Comments ±1 0.7 × VLOGIC 1.8 Unit 1.8 2.7 VREF + 1.5 V V ISINK = 200 μA ISOURCE = 200 μA pF 5.5 3 3 3 3 5.5 5.5 V µA µA µA µA V V 1.1 1.1 1 1 1.26 1.3 1.7 1.7 1.1 1.1 1 1 1.26 1.3 1.7 1.7 mA mA µA µA 1 1 2.5 2.5 1 1 2.5 2.5 µA µA 1 1 5.5 5.5 1 1 5.5 5.5 µA µA Power-on, −40°C to +105°C Power-on, −40°C to +125°C Power-down, −40°C to +105°C Power-down, −40°C to +125°C Gain = 1 Gain = 2 −40°C to +85°C −40°C to +105°C Three-state, −40°C to +85°C Power down to 1 kΩ, −40°C to +85°C Three-state, −40°C to +105°C Power down to 1 kΩ, −40°C to +105°C Three-state, −40°C to +125°C Power down to 1 kΩ, −40°C to +125°C DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280. 2 See the Terminology section. 3 Guaranteed by design and characterization; not production tested. 4 Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink 40 mA up to a junction temperature of 125°C. 5 VDD = 5 V. The AD5676 includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV. 7 Interface inactive. All DACs active. DAC outputs unloaded. 8 All DACs powered down. 1 Rev. B | Page 4 of 27 Data Sheet AD5676 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted. Guaranteed by design and characterization, not production tested. Table 3. Parameter Output Voltage Settling Time1 Slew Rate Digital-to-Analog Glitch Impulse1 Digital Feedthrough1 Digital Crosstalk1 Analog Crosstalk1 DAC-to-DAC Crosstalk1 Total Harmonic Distortion (THD)1, 2 Output Noise Spectral Density (NSD)1 Output Noise Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Signal-to-Noise-and-Distortion Ratio (SINAD) 1 2 Min Typ 5 0.8 1.4 0.13 0.1 −0.25 −1.3 −2.0 −80 300 6 90 83 80 Max 8 Unit µs V/µs nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/√Hz µV p-p dB dB dB See the Terminology section. Digitally generated sine wave at 1 kHz. Rev. B | Page 5 of 27 Test Conditions/Comments ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry, gain = 1 Gain = 1 Gain = 2 TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, bandwidth = 10 kHz, gain = 2 0.1 Hz to 10 Hz, gain = 1 TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz AD5676 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 4. Parameter1 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time (Single, Combined, or All Channel Update) SYNC Falling Edge to SCLK Fall Ignore LDAC Pulse Width Low SCLK Falling Edge to LDAC Rising Edge SCLK Falling Edge to LDAC Falling Edge RESET Minimum Pulse Width Low RESET Pulse Activation Time Power-Up Time2 2 1.8 V ≤ VLOGIC < 2.7 V Min Max 20 4 4.5 15.1 0.8 +0.1 0.95 9.65 4.75 4.85 41.25 26.35 4.8 132 5.15 2.7 V ≤ VLOGIC ≤ 5.5 V Min Max 20 1.7 4.3 10.1 0.8 −0.8 1.25 6.75 9.7 5.45 25 20.3 6.2 80 5.18 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Time to exit power-down to normal mode of AD5676 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded. t9 t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 SDI DB23 DB0 t12 t10 LDAC1 t11 LDAC2 t13 RESET t14 VOUTx 1ASYNCHRONOUS 2SYNCHRONOUS 12549-002 1 Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 LDAC UPDATE MODE. LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. B | Page 6 of 27 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns μs Data Sheet AD5676 DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 5. Parameter1 SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SDO Data Valid from SCLK Rising Edge SCLK Falling Edge to SYNC Rising Edge Symbol t1 t2 t3 t4 t5 t6 t7 t8 t10 t11 1.8 V ≤ VLOGIC < 2.7 V Min Max 120 33 2.8 75 1.2 0.3 16.2 55.1 21.5 24.4 2.7 V ≤ VLOGIC ≤ 5.5 V Min Max 83.3 25.3 3.25 50 0.5 0.4 13 45 22.7 20.3 Unit ns ns ns ns ns ns ns ns ns ns SYNC Rising Edge to SCLK Rising Edge t12 85.5 54 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Circuit Diagram and Daisy-Chain and Readback Timing Diagrams 200µA VOH (MIN) CL 20pF 200µA 12549-003 TO OUTPUT PIN IOL IOH Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications SCLK 48 24 t11 t8 t12 t4 SYNC SDI t6 DB23 DB0 INPUT WORD FOR DAC N DB23 DB0 t10 INPUT WORD FOR DAC N + 1 DB23 SDO UNDEFINED DB0 INPUT WORD FOR DAC N Figure 4. Daisy-Chain Timing Diagram Rev. B | Page 7 of 27 12549-004 t5 AD5676 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. The design of the thermal board requires close attention. Thermal resistance is highly impacted by the printed circuit board (PCB) being used, layout, and environmental conditions. Parameter VDD to GND VLOGIC to GND VOUTx to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb-Free (J-STD-020) ESD Ratings Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −40°C to +125°C −65°C to +150°C 125°C 260°C 2 kV 1.5 kV Table 6. Thermal Resistance Package Type 20-Lead TSSOP (RU-20)1 20-Lead LFCSP (CP-20-8)2 θJA 98.65 θJB 44.39 θJC 17.58 ΨJT 1.77 ΨJB 43.9 Unit °C/W 82 16.67 32.5 0.43 22 °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51 2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. 1 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 27 Data Sheet AD5676 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUT1 1 20 VOUT0 2 19 VOUT3 VDD 3 18 VREF VLOGIC 4 17 RESET SYNC 5 16 SDO SCLK 6 15 LDAC SDI 7 14 RSTSEL GAIN 8 13 GND VOUT7 9 12 VOUT4 VOUT6 10 11 VOUT5 12549-006 AD5676 TOP VIEW (Not to Scale) VOUT2 Figure 5. 20-Lead TSSOP Pin Configuration Table 7. 20-Lead TSSOP Pin Function Descriptions Pin No. 1 2 3 Mnemonic VOUT1 VOUT0 VDD 4 5 VLOGIC SYNC 6 SCLK 7 SDI 8 GAIN 9 10 11 12 13 14 VOUT7 VOUT6 VOUT5 VOUT4 GND RSTSEL 15 LDAC 16 SDO 17 RESET 18 19 20 VREF VOUT3 VOUT2 Description Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. Power Supply Input. The AD5676 operates from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on the falling edges of the next 24 clocks. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates of up to 50 MHz. Serial Data Input. The AD5676 has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Device. Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all eight DACs to midscale. Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to update simultaneously. This pin can also be tied permanently low. Serial Data Output. Use this pin to daisy-chain a number of devices together, or use it for readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Reference Input Voltage. Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. Rev. B | Page 9 of 27 Data Sheet 20 19 18 17 16 VOUT0 VOUT1 VOUT2 VOUT3 NIC AD5676 AD5676 TOP VIEW (Not to Scale) 15 14 13 12 11 VREF RESET SDO LDAC GND 12549-100 1 2 3 4 5 VOUT7 6 VOUT6 7 VOUT5 8 VOUT4 9 NIC 10 VDD VLOGIC SYNC SCLK SDI NIC = NOT INTERNALLY CONNECTED Figure 6. 20-Lead LFCSP Pin Configuration Table 8. 20-Lead LFCSP Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 3 VLOGIC SYNC 4 SCLK 5 SDI 6 7 8 9 10, 16 11 VOUT7 VOUT6 VOUT5 VOUT4 NIC GND 12 LDAC 13 SDO 14 RESET 15 17 18 19 20 VREF VOUT3 VOUT2 VOUT1 VOUT0 EPAD Description Power Supply Input. The AD5676 operate from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on the falling edges of the next 24 clocks. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates of up to 50 MHz. Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. Not Internally Connected Ground Reference Point for All Circuitry on the Device. Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. That allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Reference Input Voltage. Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. Rev. B | Page 10 of 27 Data Sheet AD5676 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 10 8 1.5 6 4 INL ERROR (LSB) INL ERROR (LSB) 1.0 0.5 0 –0.5 2 0 –2 –4 –1.0 –6 VDD = 5V TA = 25°C VREF = 2.5V –8 10000 20000 30000 40000 50000 60000 70000 CODE –10 –40 –20 10 0.8 8 0.6 6 0.4 4 DNL ERROR (LSB) 0.2 0 –0.2 –0.4 60000 70000 CODE VDD = 5V TA = 25°C VREF = 2.5V –10 –40 12549-008 –1.0 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 8. DNL Error vs. Code Figure 11. DNL Error vs. Temperature 0.04 TOTAL UNADJUSTED ERROR (% OF FSR) 0.10 0.03 0.02 0.01 0 –0.01 –0.02 0 10000 20000 30000 40000 CODE 50000 60000 70000 12549-009 TOTAL UNADJUSTED ERROR (% OF FSR) 120 –4 –8 50000 100 –2 –6 40000 120 0 –0.8 30000 100 2 –0.6 20000 80 0.09 0.08 VDD = 5V TA = 25°C VREF = 2.5V 0.07 0.06 0.05 0.04 0.03 0.02 12549-012 DNL ERROR (LSB) 1.0 10000 20 40 60 TEMPERATURE (°C) Figure 10. INL Error vs. Temperature Figure 7. INL Error vs. Code 0 0 12549-011 0 12549-007 –2.0 12549-010 –1.5 0.01 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 12. TUE vs. Temperature Figure 9. TUE vs. Code Rev. B | Page 11 of 27 100 120 AD5676 Data Sheet 10 0.10 VDD = 5V TA = 25°C VREF = 2.5V 6 0.08 0.06 ERROR (% OF FSR) INL ERROR (LSB) 4 2 0 –2 –4 –6 0.04 0.02 FULL-SCALE ERROR 0 –0.02 GAIN ERROR –0.04 12549-016 –0.06 –8 –10 2.7 3.2 3.7 4.2 4.7 VDD = 5V TA = 25°C VREF = 2.5V –0.08 –0.10 –40 5.2 12549-019 8 –20 0 SUPPLY VOLTAGE (V) 0.10 8 0.08 6 0.06 4 0.04 ERROR (% OF FSR) 10 2 0 –2 –4 3.2 100 120 VDD = 5V TA = 25°C VREF = 2.5V 0.02 GAIN ERROR 0 –0.02 FULL-SCALE ERROR –0.04 3.7 4.2 4.7 –0.08 –0.10 2.7 5.2 3.2 3.7 SUPPLY VOLTAGE (V) 4.2 4.7 5.2 SUPPLY VOLTAGE (V) Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage Figure 14. DNL Error vs. Supply Voltage 1.8 0.10 0.08 1.5 0.06 VDD = 5V TA = 25°C VREF = 2.5V 1.2 ERROR (mV) 0.04 0.02 0 –0.02 ZERO CODE ERROR 0.9 0.6 0.3 OFFSET ERROR –0.04 –0.08 –0.10 2.7 VDD = 5V TA = 25°C VREF = 2.5V 3.2 3.7 4.2 4.7 5.2 –0.3 –0.6 –40 12549-021 –0.06 0 12549-018 TOTAL UNADJUSTED ERROR (% OF FSR) 80 12549-020 –8 60 –0.06 VDD = 5V TA = 25°C VREF = 2.5V –10 2.7 40 Figure 16. Gain Error and Full-Scale Error vs. Temperature 12549-017 DNL ERROR (LSB) Figure 13. INL Error vs. Supply Voltage –6 20 TEMPERATURE (°C) –20 0 20 40 60 80 100 120 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 18. Zero Code Error and Offset Error vs. Temperature Figure 15. TUE vs. Supply Voltage Rev. B | Page 12 of 27 Data Sheet AD5676 6 1.5 5 1.0 ZERO CODE ERROR 4 3 VOUT (V) ERROR (mV) 0.5 OFFSET ERROR 0 2 1 –0.5 0 4.2 3.7 3.2 4.7 –2 –0.06 5.2 VREF = 2.5V –0.04 –0.02 SUPPLY VOLTAGE (V) 0 0.02 0.04 0.06 LOAD CURRENT (A) Figure 19. Zero Code Error and Offset Error vs. Supply Voltage Figure 22. Source and Sink Capability at 5 V 120 4.0 VDD = 5V TA = 25°C VREF = 2.5V 100 VDD = 3V TA = 25°C GAIN = 1 0xFFFF 0xC000 0x8000 0x4000 0x0000 3.5 3.0 VREF = 2.5V 2.5 VOUT (V) 80 HITS VDD = 5V TA = 25°C GAIN = 2 0x4000 0x0000 12549-025 –1.5 2.7 0xFFFF 0xC000 0x8000 –1 12549-022 VDD = 5V TA = 25°C VREF = 2.5V –1.0 60 2.0 1.5 1.0 40 0.5 0 12549-023 20 0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 –0.5 –1.0 –0.06 1.01 –0.04 –0.02 IDD FULL SCALE (mA) 0 0.02 0.04 0.06 LOAD CURRENT (A) Figure 20. IDD Histogram with External Reference 12549-026 0 Figure 23. Source and Sink Capability at 3 V 1.4 1.6 1.0 DEVICE 1 DEVICE 2 DEVICE 3 1.5 0.6 IDD (mA) 0.2 –0.2 1.1 –1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 LOAD CURRENT (A) 12549-027 –1.0 1.3 1.2 SINKING –2.7V SINKING –3V SINKING –5V SOURCING –5V SOURCING –3V SOURCING –2.7V –0.6 12549-024 VOUT (V) 1.4 1.0 0 10000 20000 30000 40000 CODE 50000 60000 Figure 24. Supply Current (IDD) vs. Code Figure 21. Headroom/Footroom (∆VOUT) vs. Load Current Rev. B | Page 13 of 27 70000 AD5676 Data Sheet 2.0 2.0 1.8 1.8 FULL SCALE 1.6 1.6 1.4 ZERO CODE 1.2 1.2 VOUT (V) 1.0 0.8 1.0 0.6 VDD = 5V GAIN = 1 TA = 25°C VREF = 2.5V 1/4 TO 3/4 SCALE 0.8 0.4 0.4 –40 12549-028 0.6 –20 0 20 40 60 80 100 0.2 0 80 120 100 120 200 Figure 28. Full-Scale Settling Time Figure 25. Supply Current (IDD) vs. Temperature 2.0 6 1.8 5 1.6 0.006 VDD (V) VOUT0 (V) VOUT1 (V) VOUT2 (V) VOUT3 (V) VOUT4 (V) VOUT5 (V) VOUT6 (V) VOUT7 (V) 4 FULL SCALE VDD (V) 1.4 IDD (mA) 180 160 TIME (µs) TEMPERATURE (°C) ZERO CODE 1.2 140 12549-031 EXTERNAL REFERENCE, FULL SCALE 3 0.005 0.004 0.003 2 0.002 1 0.001 0 0 VOUT (V) IDD (mA) 1.4 DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 EXTERNAL REFERENCE, FULL SCALE 0.8 0.4 2.7 12549-029 0.6 3.2 3.7 4.2 4.7 –1 0 5.2 0.002 0.004 0.006 0.008 –0.001 0.010 TIME (Seconds) LOGIC INPUT VOLTAGE (V) Figure 26. Supply Current (IDD) vs. Supply Voltage Figure 29. Power-On Reset to 0 V and Midscale 3.00 2.2 2.0 FULL SCALE MIDSCALE, GAIN = 2 2.50 1.8 VOUT (V) 2.00 1.4 ZERO CODE 1.2 1.0 SYNC 1.50 MIDSCALE, GAIN = 1 1.00 EXTERNAL REFERENCE, FULL SCALE 0.8 0.50 0.6 0.4 2.7 3.2 3.7 4.2 4.7 0 –5 5.2 VDD = 5V TA = 25°C VREF = 2.5V 0 5 TIME (µs) LOGIC INPUT VOLTAGE (V) Figure 27. Supply Current (IDD) vs. Logic Input Voltage Figure 30. Exiting Power-Down to Midscale Rev. B | Page 14 of 27 12549-033 12549-030 IDD (mA) 1.6 10 12549-032 1.0 Data Sheet AD5676 0.004 0.003 0.002 VOUT (V) 0.001 1 0 –0.003 –0.004 15 17 16 19 18 20 21 12549-034 VDD = 5V GAIN = 1 TA = 25°C VREF = 2.5V CODE = 0x7FFF TO 0x8000 ENERGY = 1.209376nV-sec –0.002 CH1 5µV 22 M1.0sec A CH1 401mV 12549-038 –0.001 TIME (µs) Figure 31. Digital-to-Analog Glitch Impulse Figure 34. 0.1 Hz to 10 Hz Output Noise 0.003 1200 VDD = 5V TA = 25°C GAIN = 1 VREF = 2.5V 0.002 1000 0.001 NSD (NV/√Hz) 800 –0.001 –0.002 –0.004 –0.005 1 2 3 4 5 6 7 400 –0.006 0 2 4 6 8 12 10 14 16 18 FULL SCALE MIDSCALE ZERO SCALE 600 200 12549-040 ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL –0.003 12549-035 VOUT (V) 0 0 10 20 100 1k TIME (µs) 1M 100k Figure 35. Noise Spectral Density (NSD) Figure 32. Analog Crosstalk 0 0.012 ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL ATTACK CHANNEL 0.010 0.008 0.006 0.004 1 2 3 4 5 6 7 VDD = 5V TA = 25°C VREF = 2.5V –20 –40 –60 dBV 0.002 0 –0.002 –80 –100 –120 –0.004 –140 12549-037 –0.006 –160 –0.008 –0.010 0 2 4 6 8 10 12 14 TIME (µs) 16 18 20 12549-036 VOUT (V) 10k FREQUENCY (Hz) –180 0 2 4 6 8 10 12 FREQUENCY (kHz) Figure 36. THD at 1 kHz Figure 33. DAC-to-DAC Crosstalk Rev. B | Page 15 of 27 14 16 18 20 AD5676 Data Sheet 2.0 0.3 3 0nF 1.9 0.1nF 1.8 1nF VOUT AT MIDSCALE (V) 1.5 1.4 1.3 1.1 1.0 0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 12549-039 VDD = 5V GAIN = 1 TA = 25°C VREF = 2.5V 1.2 0.19 0.2 2 MIDSCALE, GAIN = 1 0.1 1 ZERO SCALE, GAIN = 1 0 –20 0.20 0 20 TIME (ms) TIME (µs) Figure 37. Settling Time vs. Capacitive Load Figure 39. Hardware Reset 2.0 0 1.6 1.4 1.2 BANDWIDTH (dB) DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 1.8 1.0 0.8 0.6 VDD = 5.5V GAIN = 1 TA = 25°C VREF = 2.5V 1/4 TO 3/4 SCALE 0.4 0.2 0 80 100 120 140 160 180 12549-041 VOUT (V) 0 60 40 12549-042 10nF 1.6 –10 –20 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V, ±0.1Vp-p GAIN = 1 VOUT = FULL SCALE –30 1K 200 10K 100K 12549-043 VOUT (V) 1.7 VOUT AT ZERO SCALE (V) RESET 4.7nF 1M FREQUENCY (Hz) TIME (µs) Figure 38. Settling Time, 5.5 V Figure 40. Multiplying Bandwidth, External Reference Rev. B | Page 16 of 27 10M Data Sheet AD5676 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. The AD5676 is guaranteed monotonic by design. Zero Code Error Zero code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 V. The zero code error is always positive because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured with Code 256 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the rising edge of SYNC. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Noise Spectral Density (NSD) NSD is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. To measure analog crosstalk, load one of the input registers with a fullscale code change (all 0s to all 1s and vice versa). Then, execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Rev. B | Page 17 of 27 AD5676 Data Sheet Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference with full-scale code loaded to the DAC appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. THD is measured in decibels. Rev. B | Page 18 of 27 Data Sheet AD5676 THEORY OF OPERATION The AD5676 is an octal 16-bit, serial input, voltage output DAC. The device operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5676 in a 24-bit word format via a 3-wire serial interface. The AD5676 incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to typically 1 µA. Figure 42 shows the simplified segmented resistor string DAC structure. The code loaded to the DAC register determines the switch on the string that is connected to the output buffer. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. VREF R TRANSFER FUNCTION R The gain of the output amplifier can be set to ×1 or ×2 using the gain select pin (GAIN) on the TSSOP package or the gain bit on the LFCSP package. When the GAIN pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. When the GAIN pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. When using the LFCSP package, the gain bit in the gain setup register is used to set the gain of the output amplifier. The gain bit is 0 by default. When the gain bit is 0 the output span of all eight DACs is 0 V to VREF. When the gain bit is 1 the output span of all eight DACs is 0 V to 2 × VREF. The gain bit is ignored on the TSSOP package. R R R DAC ARCHITECTURE Figure 42. Simplified Resistor String Structure The DAC architecture implements a segmented string DAC with an internal output buffer. Figure 41 shows the internal block diagram. Output Amplifiers The output buffer amplifier generates rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the gain setting, the offset error, and the gain error. VREF REF (+) DAC REGISTER RESISTOR STRING REF (–) GND VOUTx GAIN (GAIN = 1 OR 2) 12549-044 INPUT REGISTER TO OUTPUT AMPLIFIER 12549-045 DIGITAL-TO-ANALOG CONVERTER The output amplifiers can drive a load of 1 kΩ in parallel with 10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale settling time of 5 µs. Figure 41. Single DAC Channel Architecture Block Diagram Rev. B | Page 19 of 27 AD5676 Data Sheet SERIAL INTERFACE Table 9. Command Bit Definitions The AD5676 has a 3-wire serial interface (SYNC, SCLK, and SDI) that is compatible with SPI, QSPI™, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The AD5676 contains an SDO pin that allows the user to daisy chain multiple devices together (see the Daisy-Chain Operation section) or for readback. Input Shift Register The input shift register of the AD5676 is 24 bits wide. Data is loaded MSB first (DB23), and the first four bits are the command bits, C3 to C0 (see Table 9), followed by the 4-bit DAC address bits, A3 to A0 (see Table 10), and finally, the 16bit data-word. The data-word comprises 16-bit input code, followed by zero, two, or four don’t care bits. These data bits are transferred to the input register on the 24 falling edges of SCLK and are updated on the rising edge of SYNC. Commands execute on individual DAC channels, combined DAC channels, or on all DACs, depending on the address bits selected. C3 0 0 Command C2 C1 C0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 … 1 1 … 1 0 … 1 0 … 1 Description No operation Write to Input Register n (where n = 1 to 8, depending on the DAC selected from the address bits in Table 10), dependent on LDAC Update the DAC register with contents of Input Register n Write to and update DAC Channel n Power down/power up the DAC Hardware LDAC mask register Software reset (power-on reset) Gain setup register (LFCSP package only) Set up the DCEN register (daisy-chain enable) Set up the readback register (readback enable) Update all channels of the input register simultaneously with the input data Update all channels of the DAC register and input register simultaneously with the input data Reserved Reserved Table 10. Address Bits and Selected DACs Address Bits A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 Selected Output DAC Channel1 DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 A0 0 1 0 1 0 1 0 1 Any combination of DAC channels can be selected using the address bits. DB23 (MSB) C3 C2 DB0 (LSB) C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND BITS 12549-046 DATA BITS ADDRESS BITS Figure 43. Input Shift Register Content Rev. B | Page 20 of 27 Data Sheet AD5676 STANDALONE OPERATION AD5676 68HC11* The write sequence begins by bringing the SYNC line low. Data from the SDI line is clocked into the 24-bit input shift register on the falling edge of SCLK. After the last of the 24 data bits is clocked in, bring SYNC high. The programmed function is then executed, that is, an LDAC dependent change in the DAC register contents and/or a change in the mode of operation occurs. MOSI SDI SCK SCLK PC7 SYNC PC6 LDAC SDO MISO SDI If SYNC is taken high at a clock before the 24th clock, it is considered a valid frame, and invalid data may be loaded to the DAC. Bring SYNC high for a minimum of 9.65 ns (single channel, see t8 in Table 4) before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Idle SYNC at the rails between write sequences for even lower power operation. The SYNC line is kept low for 24 falling edges of SCLK, and the DAC is updated on the rising edge of SYNC. AD5676 SCLK SYNC LDAC SDO SDI When data is transferred into the input register of the addressed DAC, all DAC registers and outputs update by taking LDAC low while the SYNC line is high. AD5676 SCLK WRITE AND UPDATE COMMANDS SYNC Write to Input Register n (Dependent on LDAC) LDAC Update DAC Register with Contents of Input Register n Command 0010 loads the DAC registers and outputs with the contents of the selected input registers and updates the DAC outputs directly. Write to and Update DAC Channel n (Independent of LDAC) Command 0011 allows the user to write to the DAC registers and updates the DAC outputs directly. Bit D7 to Bit D0 determine which DACs have data from the input register transferred to the DAC register. Setting a bit to 1 transfers data from the input register to the appropriate DAC register. DAISY-CHAIN OPERATION For systems that contain several DACs, the SDO pin can daisy chain several devices together and is enabled through a software executable daisy-chain enable (DCEN) command. Command 1000 is reserved for this DCEN function (see Table 9). The daisy-chain mode is enabled by setting Bit DB0 in the DCEN register. The default setting is standalone mode, where DB0 = 0. Table 11 shows how the state of the bit corresponds to the mode of operation of the device. *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 44. Daisy-Chaining the AD5676 The SCLK pin is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the SDI input on the next DAC in the chain, a daisy-chain interface is constructed. Each DAC in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of devices updated. If SYNC is taken high at a clock that is not a multiple of 24, it is considered a valid frame, and invalid data may be loaded to the DAC. When the serial transfer to all devices is complete, SYNC goes high, which latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be continuous or a gated clock. If SYNC is held low for the correct number of clock cycles, a continuous SCLK source is used. In gated clock mode, use a burst clock containing the exact number of clock cycles, and take SYNC high after the final clock to latch the data. Table 11. Daisy-Chain Enable (DCEN) Register DB0 0 1 12549-047 SDO Command 0001 allows the user to write to the dedicated input register for each DAC individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). Description Standalone mode (default) DCEN mode Rev. B | Page 21 of 27 AD5676 Data Sheet READBACK OPERATION Table 12. Modes of Operation Readback mode is invoked through a software executable readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is enabled automatically for the duration of the read operation, after which it is disabled again. Command 1001 is reserved for the readback function. This command, in association with the address bits, A3 to A0, selects the DAC input register to read. Note that, during readback, only one DAC register can be selected. The remaining data bits in the write sequence are don’t care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. Operating Mode Normal Operation Power-Down Modes 1 kΩ to GND Three-State 1. 2. Write 0x900000 to the AD5676 input register. This configures the device for read mode with the DAC register of Channel 0 selected. Note that all data bits, DB15 to DB0, are don’t care bits. Follow this with a second write, a no operation (NOP) condition, 0x000000. During this write, the data from the register is clocked out on the SDO line. DB23 to DB20 contain undefined data, and the last 16 bits contain the DB19 to DB4 DAC register contents. 0 1 1 1 Any or all DACs (DAC 0 to DAC 7) power down to the selected mode by setting the corresponding bits. See Table 13 for the contents of the input shift register during the power-down/ power-up operation. When both Bit PD1 and Bit PD0 in the input shift register are set to 0, the device works normally with its normal power consumption of 1.1 mA typically. However, for the two power-down modes, the supply current falls to 1 µA typically. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the devices are known while the devices are in power-down mode. There are two different power-down options. The output is connected internally to GND through either a 1 kΩ resistor, or it is left open-circuited (three-state). The output stage is shown in Figure 45. When SYNC is high the SDO pin is driven by a weak latch which holds the last data bit. The SDO pin can be overdriven by the SDO pin of another device, thus allowing multiple devices to be read using the same SPI interface. DAC AMPLIFIER POWER-DOWN CIRCUITRY POWER-DOWN OPERATION The AD5676 provides two separate power-down modes. Command 0100 is designated for the power-down function (see Table 9). These power-down modes are software programmable by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register. There are two bits associated with each DAC channel. Table 12 shows how the state of the two bits corresponds to the mode of operation of the device. PD0 0 VOUTx RESISTOR NETWORK 12549-048 For example, to read back the DAC register for Channel 0, implement the following sequence: PD1 0 Figure 45. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The DAC register updates while the device is in power-down mode. The time required to exit power-down is typically 5 µs for VDD = 5 V. Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1 [DB23:DB20] 0100 1 DB19 0 [DB18:DB16] XXX DAC 7 [DB15: B14] [PD1:PD0] DAC 6 [DB13: B12] [PD1:PD0] DAC 5 [DB11: B10] [PD1:PD0] X means don’t care. Rev. B | Page 22 of 27 DAC 4 [DB9:DB8] [PD1:PD0] DAC 3 [DB7:DB6] [PD1:PD0] DAC 2 [DB5:DB4] [PD1:PD0] DAC 1 [DB3:DB2] [PD1:PD0] DAC 0 [DB1:DB0] [PD1:PD0] Data Sheet AD5676 LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5676 DAC has a double buffered interface consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for this hardware LDAC function. Address bits are ignored. Writing to the DAC using Command 0101 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wants to select which channels respond to the LDAC pin. OUTPUT AMPLIFIER VREF 16-BIT DAC LDAC DAC REGISTER VOUTx Table 14. LDAC Overwrite Definition Load LDAC Register INPUT REGISTER INTERFACE LOGIC SDO 12549-049 SCLK SYNC SDI LDAC Bits (DB7 to DB0) 00000000 11111111 LDAC Pin LDAC Operation 1 or 0 X1 Determined by the LDAC pin. DAC channels update and override the LDAC pin. DAC channels see LDAC as 1. Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC Instantaneous DAC Updating (LDAC Held Low) 1 LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the rising edge of SYNC and the output begins to change (see Table 15). Deferred DAC Updating (LDAC is Pulsed Low) X means don’t care. The LDAC register gives the user extra flexibility and control over the hardware LDAC pin (see Table 14). Setting the LDAC bits (DB0 to DB7) to 0 for a DAC channel means that the update for this channel is controlled by the hardware LDAC pin. LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after SYNC is taken high. The update occurs on the falling edge of LDAC. Table 15. Write Commands and LDAC Pin Truth Table1 Command 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update the DAC register with contents of Input Register n Write to and update DAC Channel n 0011 Hardware LDAC Pin State VLOGIC GND2 VLOGIC GND Input Register Contents Data update Data update No change No change DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents VLOGIC GND Data update Data update Data update Data update A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. 1 Rev. B | Page 23 of 27 AD5676 Data Sheet HARDWARE RESET (RESET) The RESET pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the RESET select pin. It is necessary to keep the RESET pin low for a minimum time (see Table 4) to complete the operation (see Figure 2). When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. While the RESET pin is low, the outputs cannot be updated with a new value. A software executable reset function is also available that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 9). Any events on the LDAC or RESET pins during power-on reset are ignored. The RSTSEL pin is only available on the TSSOP package. When the AD5676 LFCSP package is used the outputs power up to 0 V. AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE The output amplifier gain setting for the LFCSP package is determined by the state of Bit DB2 in the Gain setup register (see Table 16 and Table 17). Table 16. Gain Setup Register Bit DB2 Description Amplifier gain setting DB2 = 0; amplifier gain = 1 (default) DB2 = 1; amplifier gain = 2 RESET SELECT PIN (RSTSEL) The AD5676 contains a power-on reset circuit that controls the output voltage during power-up. By connecting the RSTSEL pin low, the output powers up to zero scale. Note that this is outside the linear region of the DAC; by connecting the RSTSEL pin high, VOUTx power up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. Table 17. 24-Bit Input Shift Register Contents for Gain Setup Command DB23 (MSB) 0 DB22 1 DB21 1 DB20 1 DB19 to DB3 Don’t care DB2 Gain Rev. B | Page 24 of 27 DB1 Reserved; set to 0 DB0 (LSB) Reserved; set to 0 Data Sheet AD5676 APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS AD5676 TO SPORT INTERFACE The AD5676 is typically powered by the following supplies: VDD = 3.3 V and VLOGIC = 1.8 V. The Analog Devices ADSP-BF527 has one SPORT serial port. Figure 49 shows how a SPORT interface controls the AD5676. The ADP7118 can be used to power the VDD pin. The ADP160 can be used to power the VLOGIC pin. This setup is shown in Figure 47. The ADP7118 can operate from input voltages up to 20 V. The ADP160 can operate from input voltages up to 5.5 V. ADSP-BF527 3.3V: VDD ADP160 LDO 1.8V: VLOGIC SYNC SCLK SDI GPIO0 GPIO1 Figure 47. Low Noise Power Solution for the AD5676 LDAC RESET 12549-054 SPORT_TFS SPORT_TSCK SPORT_DTO ADP7118 LDO 12549-057 5V INPUT AD5676 Figure 49. SPORT Interface MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5676 is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5676 requires a 24-bit data-word with data valid on the rising edge of SYNC. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5676 is mounted so that the AD5676 lies on the analog plane. AD5676 TO ADSP-BF531 INTERFACE The SPI interface of the AD5676 can easily connect to industrystandard DSPs and microcontrollers. Figure 48 shows the AD5676 connected to the Analog Devices, Inc. Blackfin® DSP. The Blackfin has an integrated SPI port that can connect directly to the SPI pins of the AD5676. In systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. AD5676 ADSP-BF531 PF9 PF8 The GND plane on the device can be increased (as shown in Figure 50) to provide a natural heat sinking effect. SYNC SCLK SDI LDAC RESET AD5676 12549-053 SPISELx SCK MOSI The AD5676 must have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Figure 48. ADSP-BF531 Interface BOARD Figure 50. Pad Connection to Board Rev. B | Page 25 of 27 12549-055 GND PLANE AD5676 Data Sheet CONTROLLER In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5676 makes the device ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 51 shows a 4-channel isolated interface to the AD5676 using an ADuM1400. For further information, visit www.analog.com/icoupler. SERIAL CLOCK IN SERIAL DATA OUT ADuM14001 VOA VIA ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VIB VOB VIC SYNC OUT LOAD DAC OUT 1 VOC VID VOD ADDITIONAL PINS OMITTED FOR CLARITY. Figure 51. Isolated Interface Rev. B | Page 26 of 27 TO SCLK TO SDI TO SYNC TO LDAC 12549-056 GALVANICALLY ISOLATED INTERFACE Data Sheet AD5676 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 52. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.75 2.60 SQ 2.35 11 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5 10 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 020509-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 53. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5676ARUZ AD5676ARUZ-REEL7 AD5676BRUZ AD5676BRUZ-REEL7 AD5676ACPZ-REEL7 AD5676ACPZ-RL AD5676BCPZ-REEL7 AD5676BCPZ-RL EVAL-AD5676SDZ 1 Resolution 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Accuracy ±8 LSB INL ±8 LSB INL ±3 LSB INL ±3 LSB INL ±8 LSB INL ±8 LSB INL ±3 LSB INL ±8 LSB INL Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12549-0-10/15(B) Rev. B | Page 27 of 27 Package Option RU-20 RU-20 RU-20 RU-20 CP-20-8 CP-20-8 CP-20-8 CP-20-8