ISL34340 ® Data Sheet March 7, 2008 WSVGA 24-Bit Long-Reach Video Serdes with Bidirectional Side-Channel The ISL34340 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. Ordering Information PART NUMBER Features • 24-bit RGB transport over single differential pair • Bidirectional auxiliary data transport without extra bandwidth and over the same differential pair • 40MHz PCLK transports - SVGA 800 x 600 @ 70fps, 16% blanking - WSVGA 1024 x 600 @ 60fps, 8% blanking • Internal 100Ω termination on high-speed serial lines • DC balanced 8b/10b line code allows AC-coupling - Provides immunity against ground shifts TEMP. RANGE (°C) PART MARKING FN6255.0 PKG. DWG. # PACKAGE ISL34340INZ* ISL34340INZ -40 to +85 64 Ld EPTQFP Q64.10x10B (Note) (Pb-free) *Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates • Same device for serializer and deserializer simplifies inventory • I2C interface • High-speed serial lines meet 8kV ESD rating Applications • Navigation and display systems • Video entertainment systems • Industrial computing terminals • Remote cameras Typical Application Diagram RSTB/PDB VDD_CR VDD_P VDD_IO VDD_CDR VSYNC HSYNC DE mode) PCLK_OUT ISL34340 (deserializer VIDEO SINK VIDEO_TX 3.16 KΩ I2CA1 I2CA0 PCLK_IN GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO VIDEO_TX I2CA1 I2CA0 TEST_EN REF_RES 3.16 KΩ 1 VDD_IO VDD_AN SERIOP SERION REF_CLK 24 RGB 27 nf SERION VDD_IO 27 nf REF_RES (serializer mode) 27 nf 1.8V TEST_EN 10m DIFFERENTIAL CABLE SERIOP ISL34340 GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO VIDEO SOURCE VDD_TX 27 nf RGB VSYNC HSYNC DE PCLK_IN 3.3V RSTB/PDB VDD_CR VDD_P VDD_IO VDD_CDR 1.8V VDD_IO VDD_TX 24 VDD_AN 3.3V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL34340 Pinout ISL34340 (64 LD EPTQFP) TOP VIEW Block Diagram SCL SDA I2C VCM GENERATOR RAM SERIOP PREEMPHASIS TX 3 V/H/DE TDM 8b/10b RGB SERION MUX DEMUX 24 RX EQ VIDEO_TX (HI) CDR PCLK_IN (REF_CLK when VIDEO_TX is LO) x30 ÷30 PCLK_OUT 2 FN6255.0 March 7, 2008 ISL34340 Absolute Maximum Ratings Thermal Information Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . . . -0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . -0.5V to 4.6V Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model All pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV SERIOP/N (all VDD connected, all GND connected) . . . . . . .8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Thermal Resistance (Typical, Notes 1, 2) θJA θJC (°C/W) EPTQFP. . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD_CDR, VDD_CR 1.7 1.8 1.9 V VDD_TX, VDD_P, VDD_AN, VDD_IO 3.0 3.3 3.6 V POWER SUPPLY VOLTAGE SERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current IDDTX Analog CDR Supply Current IDDCDR VIDEO_TX = 1 PCLK_IN = 40MHz 17 mA 57 mA Digital I/O Supply Current IDDIO 1 Digital Supply Current IDDCR 20 mA IDDP 17 mA IDDAN 5.5 mA PLL/VCO Supply Current Analog Bias Supply Current 2 mA Total 1.8V Supply Current 77 90 mA Total 3.3V Supply Current 40 46 mA DESERIALIZER POWER SUPPLY CURRENTS Analog TX Supply Current IDDTX Analog CDR Supply Current IDDCDR VIDEO_TX = 0 REF_CLK = 40MHz 24 mA 45 mA Digital I/O Supply Current IDDIO 17 Digital Supply Current IDDCR 32 mA IDDP 17 mA IDDAN 5.4 mA PLL/VCO Supply Current Analog BIAS Supply Current 25 mA Total 1.8V Supply Current 77 90 mA Total 3.3V Supply Current 64 80 mA 3 FN6255.0 March 7, 2008 ISL34340 Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER-DOWN SUPPLY CURRENT Total 1.8V Power-down Supply Current RSTB = GND; spec is per device Total 3.3V Power-down Supply Current 0.5 mA 1 mA PARALLEL INTERFACE High Level Input Voltage VIH Low Level Input Voltage VIL Input Leakage Current IIN 2.0 -10 High Level Output Voltage VOH IOH = -2.0mA, VDD_IO = 3V Low Level Output Voltage VOL IOL = 2.0mA, VDD_IO = 3V Output Short Circuit Current IOSC Output Rise and Fall Times tOR/tOF V ±0.01 0.8 V 10 µA 0.8*VDD_IO V 0.2*VDD_IO V 50 mA Slew rate control set to min, CL = 8pF 1 ns Slew rate control set to max, CL = 8pF 4 ns SERIALIZER PARALLEL INTERFACE PCLK_IN Frequency fIN 6 PCLK_IN Duty Cycle tIDC 40 Parallel Input Setup Time tIS 3.6 ns Parallel Input Hold Time tIH 1.6 ns PCLK_OUT Frequency fOUT 6 PCLK_OUT Duty Cycle tODC 50 40 MHz 60 % DESERIALIZER PARALLEL INTERFACE PCLK_OUT Period Jitter (rms) PCLK_OUT Spread Width Time to paRallel Output Data Valid Deserializer Output Latency 40 MHz 50 % tOJ Clock randomizer off 0.5 %Tpclk tOSPRD Clock randomizer on ±20 %Tpclk tDV tCPD Relative to PCLK_OUT Part-to-part, side-channel disabled -4.7 4 9 5.5 ns 14 PCLK DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN) REF_CLK Lock Time tPLL REF_CLK to PCLK_OUT Clock Maximum Frequency Offset 100 µs ppm PCLK_OUT is the recovered clock 1500 5000 TXCN = 0x00 600 825 HIGH-SPEED TRANSMITTER HS Differential Output Voltage, Transition Bit HS Differential Output Voltage, Non-Transition Bit HS Generated Output Common Mode Voltage 4 VODTR VODNTR VOCM 990 mVP-P TXCN = 0x0F 1170 mVP-P TXCN = 0xF0 975 mVP-P TXCN = 0xFF 1300 mVP-P TXCN = 0x00 600 825 990 mVP-P TXCN = 0x0F 460 mVP-P TXCN = 0xF0 975 mVP-P TXCN = 0xFF 600 mVP-P 2.35 V FN6255.0 March 7, 2008 ISL34340 Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued) PARAMETER SYMBOL CONDITIONS HS Common Mode Serializer-Deserializer Voltage Difference ΔVCM HS Differential Output Impedance ROUT HS Output Latency tLPD Part-to-part HS Output Rise and Fall Times tR/tF 20% to 80% MIN TYP MAX UNITS 20 120 mV 80 100 120 Ω 4 7 10 PCLK 150 ps tSKEW <10 ps HS Output Random Jitter tRJ 13.4 psrms HS Output Deterministic Jitter tDJ 40 psP-P HS Differential Skew HIGH SPEED RECEIVER HS Differential Input Voltage VID HS Generated Input Common Mode Voltage HS Differential Input Impedance 150 VICM mVP-P 2.32 RIN 80 HS Maximum Jitter Tolerance 100 V 120 0.52 Ω UIP-P I2 C I2C Clock Rate (on SCL) FI2C 100 400 kHz I2C Clock Pulse Width (HI or LO) 1.3 I2C Clock Low to Data Out Valid 0 I2C Start/Stop Setup/Hold Time 0.6 µs I2C Data in Setup Time 100 ns I2C Data in Hold Time 100 ns I2C Data out Hold Time 100 ms µs 1 µs Pin Descriptions DESCRIPTION PIN NUMBER 52 to 63, 2 to 13 PIN NAME SERIALIZER DESERIALIZER RGBA[7:0], Parallel video data LVCMOS inputs RGBB[7:0], RGBC[7:0] Parallel video data LVCMOS outputs 22 HSYNC Horizontal (line) Sync LVCMOS input Horizontal (line) Sync LVCMOS output 23 VSYNC Vertical (frame) Sync LVCMOS input Vertical (frame) Sync LVCMOS output 21 DATAEN Video Data Enable LVCMOS input Video Data Enable LVCMOS output 26 PCLK_IN Pixel clock LVCMOS input PLL reference clock LVCMOS input 51 PCLK_OUT Default not used Recovered clock LVCMOS output 41, 40 SERIOP/N High speed differential serial I/O High speed differential serial I/O 24 HSYNCPOL CMOS input for HSYNC 1: HSYNC is active low 0: HSYNC is active high 25 VSYNCPOL CMOS input for VSYNC 1: VSYNC is active low 0: VSYNC is active high 49 VIDEO_TX CMOS input for video flow direction 1: video serializer 0: video deserializer 5 FN6255.0 March 7, 2008 ISL34340 Pin Descriptions (Continued) DESCRIPTION PIN NUMBER PIN NAME SERIALIZER DESERIALIZER 29, 30 SDA, SCL I2C Interface Pins (I2C DATA, I2C CLK) 31-33 I2CA[2:0] I2C Device Address 16 RSTB/PDB CMOS input for Reset and Power-down. For normal operation this pin must be forced high. When this pin is forced low, the device will be reset. If this pin stays low the device will be in PD mode. 14 STATUS CMOS output for Receiver Status: 1: Valid 8b/10b data received 0: otherwise Note: serializer and deserializer switch roles during side-channel reverse traffic 36 REF_RES Analog bias setting resistor connection; use 3.16kΩ ±1% to ground 27 GND_P PLL Ground 48, 64 GND_IO Digital (Parallel and Control) Ground 44, 45 GND_CDR Analog (Serial) Data Recovery Ground 39, 42 GND_TX Analog (Serial) Output Ground 37 GND_AN Analog Bias Ground 17, 18 GND_CR Core Logic Ground 19, 20 VDD_CR Core Logic VDD 43 VDD_TX Analog (Serial) Output VDD 38 VDD_AN Analog Bias VDD 46, 47 VDD_CDR Analog (Serial) Data Recovery VDD 1, 50 VDD_IO Digital (Parallel and Control) VDD 28 VDD_P PLL VDD TEST_EN, TEST Must be connected to ground Exposed Pad Must be connected to ground 15, 35 Exposed Pad NOTES: 3. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components or features. 4. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be considered a common connection. 6 FN6255.0 March 7, 2008 ISL34340 Diagrams VODTR VODNTR TXCN 0x00 0x0F 0xF0 0xFF FIGURE 1. VOD vs TXCN SETTING VIDEO_TX = 1 tIDC 1/fIN PCLK_IN tIH tIS RGB[A:C][7:0] VALID DATA VALID DATA DATA IGNORED tIS VALID DATA DATA IGNORED tIH HSYNC VSYNC DATAEN FIGURE 2. PARALLEL VIDEO INPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0] 7 FN6255.0 March 7, 2008 ISL34340 VIDEO_TX = 0 tOR 1/fOUT tOF tODC PCLK_OUT tDV RGB[A:C][7:0] VALID DATA VALID DATA DATA HELD AT PREVIOUS VALUE VALID DATA tDV HSYNC VSYNC DATAEN FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0] Applications Overview A pair of ISL34340 serdes transports 24-bit parallel video (16-bit parallel video for the ISL34320) along with auxiliary data over a single 100Ω differential cable either to a display or from a camera. Auxiliary data is transferred in both directions and can be used for remote configuration and telemetry. The benefits include lower EMI, lower costs, greater reliability and space savings. The same device can be configured to be either a serializer or deserializer by setting one pin (VIDEO_TX), simplifying inventory. RGBA/B/C, VSYNC, HSYNC, and DATAEN pins are inputs in serializer mode and outputs in deserializer mode. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. The side-channel data is transferred between the serdes pair during two lines of the vertical video blanking interval. PCB traces need to be adjacent and matched in length (so as to minimize the imbalanced coupling to other traces or elements), and of a geometry to match the impedance of the transmitter and receiver, to minimize reflections. Similar care needs to be applied to the choice of connectors and cables. SERIOP and SERION pins incorporate internal differential termination of the serial signal lines. External termination cannot be used unless the side-channel is disabled. SERIO Pin AC-Coupling AC-coupling minimizes the effects of DC common mode voltage difference and local power supply variations between two serdes. The serializer outputs DC balanced 8b/10b line code, which allows AC-coupling. The AC-coupling capacitor on SERIO pins must be 27nf on the serializer board and 27nf on the deserializer board. The value of the AC-coupling capacitor is very critical since a value too small will attenuate the high speed signal at low clock rate. A value too big will slow down the turn around time for the side-channel. Receiver Reference Clock (REF_CLK) When the side-channel is enabled, there will be a number of PCLK cycles uncertainty from frame-to-frame. This should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. When properly configured, the serdes link supports end-to-end transport with fewer than one error in 1010 bits. The reference clock (REF_CLK) for the PLL is fed into PCLK_IN pin. REF_CLK is used to recover the clock from the high speed serial stream. REF_CLK is very sensitive to any instability. The following conditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: Differential Signals and Termination • REF_CLK frequency must within the limits specified The ISL34340 serializes the 24-bit parallel data at 30x the PCLK_IN frequency. The ISL34320 serializes the 16-bit parallel data at 20x the PCLK_IN frequency. The extra two bits per word come from the 8b/10b encoding scheme. • REF_CLK amplitude must be stable. The high bit rate of the differential serial data requires special care in the layout of traces on PCBs, in the choice and assembly of connectors, and in the cables themselves. 8 A simple 3.3V CMOS crystal oscillator can be used for REF_CLK. Power Supply Sequencing The 3.3V supply must be higher than the 1.8V supply at all times, including during power-up and power-down. To meet FN6255.0 March 7, 2008 ISL34340 this requirement, the 3.3V supply must be powered up before the 1.8V supply. For the deserializer, REF_CLK must not be applied before the device is fully powered up. Applying REF_CLK before power-up may require the deserializer to be manually reset. A 10ms delay after the 1.8V supply is powered up guarantees normal operation. Power Supply Bypassing The serializer and deserializer functions rely on the stable functioning of PLLs locked to local reference sources or locked to an incoming signal. It is important that the various supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the PLL to approaching the signal bit rate of the serial data. A combination of different values of capacitors from 1000pF to 5µF or more with low ESR characteristics is generally required. Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz region, and 1000pF capacitors in the 100MHz to 200MHz region. In general, one of the lower value capacitors should be used at each supply pin on the IC. Figure 4 shows the grounding of the various capacitors to the pin corresponding to the supply pin. Although all the ground supplies are tied together, the PCB layout should be arranged to emulate this arrangement, at least for the smaller value (high frequency) capacitors, as much as possible. The parallel LVCMOS VDD_IO supply is inherently less sensitive, but since the RGB and SYNC/DATAEN signals can all swing on the same clock edge, the current in these pins and the corresponding GND pins can undergo substantial current flow changes, so once again, a combination of different values of capacitors over a wide range, with low ESR characteristics, is desirable. A set of arrangements of this type is shown in Figure 4, where each supply is bypassed with a ferrite-bead-based choke, and a range of capacitors. A “choke” is preferable to an “inductor” in this application, since a high-Q inductor will be likely to cause one or more resonances with the shunt capacitors, potentially causing problems at or near those frequencies, while a “lossy” choke will reflect a high impedance over a wide frequency range. The higher value capacitor, in particular, needs to be chosen carefully, with special care regarding its ESR. Very good results can be obtained with multilayer ceramic capacitors, available from many suppliers, and generally in small outlines (such as the 1210 outline suggested in the schematic shown in Figure 4), which provide good bypass capabilities down to a few mΩ at 1MHz to 2MHz. Other capacitor technologies may also be suitable (perhaps niobium oxide), but “classic” electrolytic capacitors frequently have ESR values of above 1Ω, that nullify any decoupling effect above the 1kHz to 10kHz frequency range. FIGURE 4. POWER SUPPLY BYPASSING I2C Interface The I2C interface allows access to internal registers used to configure the serdes and to obtain status information. A serializer must be assigned a different address than its deserializer counterpart. The upper 3-bits are permanently set to 011 and the lower 4 bits determined by pins as follows: 0 1 1 I2CA3 I2CA2 I2CA1 I2CA0 R/W Thus, 16 serdes can reside on the same bus. By convention, when all address pins are tied low, the device address is referred to as 0x60. SCL and SDA are open drain to allow multiple devices to share the bus. If not used, SCL and SDA should be tied to VDD_IO. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6255.0 March 7, 2008 ISL34340 Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP) Q64.10x10B (JEDEC MS-026ACD-HU ISSUE D) 64 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE D D1 -D- MILLIMETERS SYMBOL -B- -A- E E1 e PIN 1 TOP VIEW MIN MAX NOTES A - 1.20 - A1 0.05 0.15 - A2 0.95 1.05 - b 0.16 0.28 6 b1 0.17 0.23 - D 11.80 12.20 3 D1 9.90 10.10 4, 5 D2 3.46 3.76 - E 11.80 12.20 3 E1 9.90 10.10 4, 5 E2 3.46 3.76 - L 0.45 0.75 - N 64 7 e 0.50 BSC Rev. 0 2/07 NOTES: 11o-13o 0.020 0.008 MIN 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 0o MIN 2. All dimensions and tolerances per ANSI Y14.5M-1982. A2 A1 GAGE PLANE 0o-7o L 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 11o-13o 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.25 0.010 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). PIN 1 7. “N” is the number of terminal positions. -H- A SEATING PLANE 0.08 0.003 E2 -C0.08 M 0.003 D S C A-B S b b1 0.09/0.16 0.004/0.006 D2 BOTTOM VIEW 10 BASE METAL WITH PLATING 0.09/0.20 0.004/0.008 FN6255.0 March 7, 2008