MAXIM MAX2140

19-3123; Rev 1a; 9/04
KIT
ATION
EVALU
E
L
B
A
AVAIL
Complete SDARS Receiver
♦ Differential I/Q Interface
♦ Complete Integrated Frequency Generation
♦ Bias Supply for External LNAs
♦ Overcurrent Protection
♦ Low-Power Standby Mode
♦ Very Small 44-Pin Thin QFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2140ETH
-40°C to +85°C
44 Thin QFN-EP*
*EP = Exposed paddle.
•Individual functional block shutdown
The MAX2140 minimizes the requirement on the baseband controller. No compensation or calibration procedures are required. The device is available in a 7mm ✕
7mm 44-pin thin QFN package.
I CA2
2
VCC_BE4
IF2QO-
IF2QI-
IF2QO+
IF2QI+
QOUT-
QOUT+
•Lowpass filters tuning
2
Block Diagram/Pin Configuration
I CA1
Channel selectivity is ensured by the SAW filter and by
on-chip monolithic lowpass filters.
The fractional-N PLL allows a very small frequency
step, making possible the implementation of an AFC
loop. Additionally, the reference is provided by an
external XTAL and on-chip oscillator. A reference buffer
output is also provided.
A 2-wire interface (I2C™ bus compatible) programs the
circuit for a wide variety of conditions, providing features such as:
•Programmable gains
♦ Self-Contained RF AGC Loop
SCL
The receiver includes a self-contained RF AGC loop
and baseband-controlled IF AGC loop, effectively providing a total dynamic range of over 92dB.
♦ Integrated Receiver, Requires Only One SAW
Filter
SDA
The MAX2140 complete receiver is designed for satellite
digital audio radio services (SDARS). The device
includes a fully monolithic VCO and only needs a SAW at
the IF and a crystal to generate the reference frequency.
To form a complete SDARS radio, the MAX2140
requires only a low-noise amplifier (LNA), which can be
controlled by a baseband controller. The small number
of external components needed makes the MAX2140based platform the lowest cost and the smallest solution for SDARS.
Features
44
43
42
41
40
39
38
37
36
35
34
XM TUNER
VCC_FE0 1
32 VCCREG
RFIN- 3
31 VCC_VCO
MAX2140
VCC_FE1 4
Σ ∆ - MOD
RFAGC_C 7
2.4GHz ISM Radios
VCC_FE2 8
PFD
CHP
1/R
IFOUT- 6
Satellite Digital Audio Radio Services (SDARS)
30 VCC_FE3
1/N
RF
AGC
IFOUT+ 5
Applications
33 VTUNE
RFIN+ 2
28 LOCK
27 VCC_A
LPF
HPF
26 VCC_D
/4/8
QUAD
AGCPWM 9
25 REFOUT
IFIN+ 10
24 XTAL
LPF
HPF
IFIN- 11
13
14
15
16
17
18
19
20
21
22
VCC_BE2
VCC_BE3
VINANT
VOUTANT
IF2IO-
IF2II-
IF2IO+
IF2II+
IOUT-
IOUT+
23 VCC_XTAL
12
VCC_BE1
I2C is a trademark of Philips Corp.
Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to
the I2C Standard Specification as defined by Philips.
29 CPOUT
ACTUAL SIZE
7mm x 7mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX2140
General Description
MAX2140
Complete SDARS Receiver
ABSOLUTE MAXIMUM RATINGS
VCC_XX to GND..................................................... -0.3V to +4.3V
VINANT to GND.................................................... -0.3V to +5.6V
AGCPWM to GND ................................................ -0.3V to +3.0V
Digital Input Current ........................................................ ±10mA
Maximum VSWR Without Damage ........................................ 4:1
Maximum VSWR Without Oscillations ................................... 4:1
Continuous Power Dissipation (TA = +70°C)
44-Pin QFN (derate 26.31mW/°C above +70°C) ..... 2105mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Theta JC ..........................................................................12°C/W
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.1V to 3.6V; VINANT ≥ VCC, VOUTANT in open circuit, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, VINANT =
3.3V, and TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage Range (Note 2)
Operating Supply Current
SYMBOL
MIN
TYP
MAX
VCC
3.1
3.3
3.6
VINANT
3.1
3.3
5.3
180
ICC
All blocks on
150
ISHDN
All blocks off
30
Lock Indicator High (Locked)
VIH_LK
Lock Indicator Low (Unlocked)
VIL_LK
Digital Input-Logic High
VIH
Digital Input-Logic Low
VIL
Input Current for Digital Control
Pins
IDIG
IAGCPWM
Input Current for AGCPWM
Voltage Drop VINANT to
VOUTANT in Normal Operating
Mode
VANTDCDROP
Current Sink at VOUTANT to Flag
Bit ACP = 1
IANTDC_H
Current Sink at VOUTANT to Flag
Bit AND = 1
IANTDC_L
2
CONDITIONS
V
mA
µA
VCC - 0.5
V
0.5
V
0.5
V
-1
+1
µA
-10
+290
µA
0.35
V
700
mA
30
mA
VCC - 0.5
V
Maximum current sink at VOUTANT is
150mA
VOUTANT shorted to ground
UNITS
195
12
20
_______________________________________________________________________________________
Complete SDARS Receiver
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-84
dBm
GENERAL RECEIVER
Minimum Input RF Power to
Produce 20mVP-P (Differential) at
I and Q Baseband Outputs
PMIN
IF AGC is set at maximum gain,
bit HPF = 0 (Note 4)
-91
Maximum Input RF Power to
Produce 400mVP-P (Differential)
at I and Q Baseband Outputs
PMAX
RF AGC threshold: RF_AGC_TRIP =
-17dBm; IF AGC is set at minimum gain, bit
HPF = 0
+3
PLK_H
LO-related spurious > 2GHz
-66
PLK_L
LO-related spurious < 2GHz
-38
NF
RF AGC is at maximum gain,
IF AGC is at reference gain
8.5
In-Band Input IP3 (Notes 5, 6)
I_IIP3
RF AGC is at maximum gain,
IF AGC is at reference gain
-32
dBm
Out-of-Band Input IP3
(Notes 5, 7)
O_IIP3
RF AGC is at maximum gain,
IF AGC is at reference gain
-9
dBm
In-Band Input IP2 (Notes 5, 6)
I_IIP2
RF AGC is at maximum gain,
IF AGC is at reference gain
+1
dBm
Out-of-Band Input IP2
(Notes 5, 7)
O_IIP2
RF AGC is at maximum gain,
IF AGC is at reference gain
+38
dBm
LO to RF Input Leakage
Noise Figure (Notes 3, 5)
32
dBm
dBm
10.4
dB
Opposite Sideband Rejection
OSR
Baseband frequencies = 100kHz (Note 4)
39
dB
Image Rejection
IRej
At fLO - fIF
54
dB
Half IF Rejection
HRej
At fLO + 0.5 x fIF
53
dB
30
42
dB
-37
-33
RF AGC LOOP
LNA Gain Reduction
RFAGC_
Range
(Note 4)
Minimum RF AGC Trip Point
RFAGC_mi Bits RF4/3/2/1/0 = 00000 (BIN)
RF AGC Trip Point
RFAGC_int Bits RF4/3/2/1/0 = 00010 (BIN) (Note 4)
Maximum RF AGC Trip Point
RFAGC_m
-35
Bits RF4/3/2/1/0 = 10100 (BIN)
dBm
-29
-15
dBm
dBm
FRONT-END (FE) PROGRAMMABLE GAIN
FE Programmable Gain Range
FE_Rge
FE Programmable Gain Step
FE_Step
(Note 4)
19
22
26
dB
2
dB
IF FILTER INTERFACE
IF Output Differential Admittance
Input Differential Impedance
Presented by the IC to the IF
Filter Output
Yout, IF
Between pins IFOUT+, IFOUT-,
fIF = 259MHz and 467MHz
1/900
+ j0
S
Zin, IF
Between pins IFOUT+, IFOUT-,
fIF = 259MHz and 467MHz
150
+ j0
Ω
_______________________________________________________________________________________
3
MAX2140
AC ELECTRICAL CHARACTERISTICS
MAX2140
Complete SDARS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IF AGC LOOP
IF AGC Control Voltage for Max
Gain
IFAGC_VM Applied at pin AGCPWM
0.2
V
IF AGC Control Voltage for Min
Gain
IFAGC_Vm Applied at pin AGCPWM
2.5
V
IF AGC Gain-Control Range
IFAGC_
Rge
(Note 4)
47
64
dB
INTERNAL BASEBAND LOWPASS FILTERS
LPF In-Band Ripple
LPFA_rip
From 0 to 6.3MHz with respect to the
amplitude at 100kHz
0.7
LPFrej
At 10.25MHz with respect to the amplitude
at 2MHz
14
21
LPFrej
At 16MHz with respect to the amplitude at
2MHz
47
51
Gain Increase
BB_DG
From bit HPF = 0 to HPF = 1
Maximum I/QOUT± Pin Loading
IQ_load
Per each of the four pins
LPF Out-of-Band Rejection
(Note 4)
dB
dB
INTERNAL OUTPUT STAGE
4
dB
10//10
kΩ//pF
FREQUENCY GENERATION: VCO AND PLL
VCO Frequency Range
VCO Tuning Gain
VCO_
Range
VCO_Gain
Synthesized VCO Phase Noise
VCO_PN
Synthesized VCO Phase-Noise
Jitter
VCO_jit
Charge-Pump Voltage Range
VCHP
Charge-Pump Current
ICHP
Pin CHP Leakage Current
PLL Reference Division Ratio
Synthesized VCO Smallest
Fractional Step
4
CHP_leak
Over VCHP range (Note 4)
2079
(Note 4)
240
MHz
MHz/V
At 10kHz outside PLL band
-80
dBc/Hz
Integrated from 100Hz to 100kHz,
LO frequency = 2079MHz
1.2
DegRMS
0.40
2.75
Bit CHP = 0
0.6
Bit CHP = 1
1.2
Across VCHP range
PLLref
PLLstep
1861
Programmable through I2C
mA
5
1
V
nA
2
23
_______________________________________________________________________________________
Hz
Complete SDARS Receiver
(MAX2140 EV kit, current drawn at VOUTANT, IVOUTANT = 150mA max, VCC = 3.1V to 3.6V, VINANT = 3.1V to 5.3V, fRF = 2320MHz
to 2345MHz, fLO = 2076MHz, TA = -40°C to +85°C. Typical values are at VCC = VINANT = 3.3V, fRF = 2338MHz, TA = +25°C, unless
otherwise noted.) (Note 2)
Interstage (IF) 259MHz SAW filter specification: insertion loss = 19dB max, 9.3MHz to 12MHz from center attenuation = 24dB min,
beyond 12MHz from center attenuation = 40dB min.
PARAMETER
Synthesized VCO Spurs
XTAL Oscillator Frequency
Range
SYMBOL
VCOspur
CONDITIONS
10kHz < foffset < 1MHz
(Note 9)
1MHz < foffset < 10MHz
-47
24
XTAL Oscillator Frequency Error
XTALerror
XTAL Oscillator Input Voltage
XTALswing Using an external TCXO
XTALduty
Reference Buffer Output Voltage
REFV
Reference Buffer Output Duty
Cycle
Maximum REFOUT Pin Loading
REFduty
REFOUT_1d
TYP
(Note 9)
XTALrge
XTAL Oscillator Input Duty Cycle
MIN
0Hz < foffset < 10kHz
Using an external XTAL (Note 8)
Using an external TCXO
Using the REFOUT pin loading specified
below (Note 4)
Using an external XTAL, not overdriven;
bit RFD = 0, using the REFOUT pin loading
specified below
MAX
UNITS
dBc
49
MHz
-16
+16
ppm
0.8
VCC
VP-P
53
%
47
50
0.95
1.10
45
50
REFOUT pin frequency = 24MHz
20
REFOUT pin frequency = 48MHz
8
VP-P
55
%
pF
TIMING CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE (Note 2)
Serial Clock Frequency
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
fSCL
200
kHz
At TA = -40°C, minimum and maximum values are guaranteed by design and characterization.
Minimum and maximum values are guaranteed by design and characterization, unless otherwise noted.
At TA = +25°C, minimum and maximum values are guaranteed by design and characterization.
At TA = +25°C and TA = +85°C, parameters are production tested.
IF AGC reference level is defined as being the required voltage applied on pin AGCPWM, and the corresponding receiver
IF gain, to measure 20mVP-P at each I/Q differential output when the RF input power is -91dBm. If even for zero volts
applied on pin AGCPWM the I/Q differential outputs are below 20mVP-P when the RF input power is -91dBm, then the reference level is defined as zero volts.
In-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2339.55MHz, f2 = 2339.75MHz.
Out-of-band IP2 and IP3 are measured with two CW tones at RF input: f1 = 2326.25MHz, f2 = 2330.25MHz.
Error computed using a crystal with no error.
No spur in the offset frequency range.
_______________________________________________________________________________________
5
MAX2140
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
INPUT RETURN LOSS
vs. FREQUENCY
-15
MAXIMUM RF AGC
-20
-25
MINIMUM RF AGC
-30
DIVIDER: /4
-20
-25
-30
DIVIDER: /8
50
-35
2.3
2.4
2.5
40
TA = +25°C
TA = -40°C
30
TA = +85°C
20
10
-40
0
0
4
8
12
20
16
0
0.6
1.2
2.4
RF AGC ENGAGEMENT SETTING
CONTROL VOLTAGE (V)
RF AGC SETTLING TIME
WITH 20dB STEP
IF AGC ATTENUATION
vs. CONTROL VOLTAGE
IF AGC ATTENUATION
vs. CONTROL VOLTAGE
5dB/div
50
TA = -40°C
40
30
TA = +85°C
20
TA = +25°C
40
30
TA = -40°C
20
TA = +85°C
10
TA = +25°C
10
-50dBm
0
0
0
START TIME: 0µs
STOP TIME: 200µs
3.0
MAX2140 toc06
R4 = 5000Ω
C32 = 0.22µF
IF AGC ATTENUATION (dB)
RF AGC DECAY
TIME
R4 = 100Ω
C32 = 0.1µF
60
50
MAX2140 toc05
RF AGC ATTACK
TIME
70
IF AGC ATTENUATION (dB)
0dBm
0.6
1.2
1.8
3.0
2.4
CONTROL VOLTAGE (V)
0
0.6
1.2
10.250000MHz
-27.278dB
MAX2140 toc07
LPF FREQUENCY RESPONSE
-100dB
1MHz
1.8
CONTROL VOLTAGE (V)
0dB
6
1.8
FREQUENCY (GHz)
MAX2140 toc04
2.2
MAX2140 toc03
MAX2140 toc02
-15
60
RF AGC ATTENUATION (dB)
-10
-10
RF AGC ENGAGEMENT THRESHOLD (dBm)
-5
RF AGC ATTENUATION
vs. CONTROL VOLTAGE
RF AGC ENGAGEMENT THRESHOLD
MAX2140 toc01
0
INPUT RETURN LOSS (dB)
MAX2140
Complete SDARS Receiver
16MHz
_______________________________________________________________________________________
2.4
3.0
Complete SDARS Receiver
LPF GROUP DELAY vs. FREQUENCY
REF
80ns
100ns/div
REFOUT WAVEFORM (REF = 0, RFD = 0)
MAX2140 toc10
MAX2140 toc09
MAX2140 toc08
VCO PHASE NOISE vs. OFFSET FREQUENCY
-50dBc/Hz
6.250000MHz
113.8ns
500mV/div
-150dBc/Hz
1MHz
16MHz
10
REFOUT WAVEFORM (REF = 1, RFD = 0)
FREQUENCY OFFSET (Hz)
1M
20ns/div
REFOUT WAVEFORM (REF = 1, RFD = 1)
MAX2140 toc11
200mV/div
MAX2140 toc12
500mV/div
10ns/div
20ns/div
_______________________________________________________________________________________
7
MAX2140
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX2140
Complete SDARS Receiver
Pin Description
PIN
NAME
1, 4, 8,
12–15, 23,
26, 27, 30,
31, 40
VCC_FE0, VCC_FE1,
VCC_FE2, VCC_BE1,
VCC_BE2, VCC_BE3,
VINANT, VCC_XTAL,
VCC_D, VCC_A,
VCC_FE3, VCC_VCO,
VCC_BE4
2, 3
RFIN+, RFIN-
5, 6
IFOUT+, IFOUT-
7
RFAGC_C
RF AGC Power-Detector Output. Set the RF AGC attack and decay response times.
9
AGCPWM
IF AGC Control Voltage Input. Input from the filtered PWM AGC control signal from the SDARS
channel-decoder IC.
10, 11
IFIN+, IFIN-
Differential First IF Input
16
VOUTANT
Overcurrent-Protected Unregulated DC Supply Output. Provides DC power supply to the
antenna module.
17, 19, 37,
39
IF2IO-, IF2IO+,
IF2QO+, IF2QO-
18, 20, 36,
38
IF2II-, IF2II+, IF2QI+,
IF2QI-
21, 22, 34,
35
IOUT-, IOUT+,
QOUT+, QOUT-
24
XTAL
25
REFOUT
28
LOCK
29
CPOUT
32
VCCREG
33
VTUNE
41, 42
I2CA2, I2CA1
43, 44
SCL, SDA
—
Exposed Pad
8
FUNCTION
Power Supplies. Bypass to ground with capacitors as close to the pins as possible.
Differential RF Inputs. Accept RF input signal from the SDARS cabled antenna with a 50Ω to
100Ω balun.
Differential First IF Output. Connect an external SAW filter to the IF output.
Differential Baseband DC Blocking Outputs.
IF2IO- = Inverting in-phase baseband output. AC couple to pin 18.
IF2IO+ = Noninverting in-phase baseband output. AC couple to pin 20.
IF2QO+ = Noninverting quadrature baseband output. AC couple to pin 36.
IF2QO- = Inverting quadrature baseband output. AC couple to pin 38.
Differential Baseband DC Blocking Inputs.
IF2II- = Inverting in-phase baseband input. AC couple to pin 16.
IF2II+ = Noninverting in-phase baseband input. AC couple to pin 19.
IF2QI+ = Noninverting quadrature baseband input. AC couple to pin 37.
IF2QI- = Inverting quadrature baseband input. AC couple to pin 39.
Differential I/Q Baseband Outputs.
IOUT- = Inverting in-phase baseband output.
IOUT+ = Noninverting in-phase baseband output.
QOUT+ = Noninverting quadrature baseband output.
QOUT- = Inverting quadrature baseband output.
Crystal Reference Input
Buffered System Clock Output. Provides clock signal to the SDARS channel-decoder IC.
Digital Logic Output to the System Controller. Indicates the lock status of the internal PLL.
VCO Charge-Pump Output
Regulated Supply Voltage for the VCO
High-Impedance VCO Tuning Input
I2C Input Signals. Define the MAX2140 I2C device address.
I2C-Compatible Programming Input. Connect to an I2C-compatible bus.
Exposed Paddle. Connect to ground.
_______________________________________________________________________________________
Complete SDARS Receiver
Front End
The front end of the MAX2140, which downconverts the
RF signal to IF, is defined from the differential RF inputs
(pins RFIN+ and RFIN-) to the output (pins IFOUT+ and
IFOUT-) to the SAW filter.
The front end includes a self-contained analog RF AGC
loop. The engagement threshold of the loop can be
programmed from -35dBm to -15dBm referred to the
RF input in 1dB steps using the RF4–RF0 programming
bits. The time constant of the loop is set externally by
the capacitor connected to RFAGC_C.
The image reject first mixer ensures a good image and
half IF rejection.
The front-end gain can be reduced by programming
bits PM3–PM0 over a 22dB range, with a step of 2dB.
This allows the selections of SAW filters with different
insertion loss.
The IF output is nominally 900Ω differentially and requires
pullup inductors to VCC, which can be used as part of the
matching network to the SAW filter impedance.
Back End
The back end, which downconverts the IF signal to
quadrature baseband, is defined from the SAW filter
inputs (pins IFIN+ and IFIN-) to the baseband outputs
(pins IOUT+, IOUT-, QOUT+, QOUT-).
The back end contains an IF AGC loop, which is closed
by the baseband controller. The IF AGC control voltage
is applied at the AGCPWM pin. The gain can be
reduced over 53dB (typ) and exhibits a log-linear characteristic.
The back end also contains individual lowpass filters on
each channel. The lowpass-filter bandwidth is the useful SDARS downconverted bandwidth (6.25MHz). The
lowpass-filter performance is factory trimmed. The bit
IOT switches between the factory-trimmed set and the
control through the I 2 C-compatible bus using bits
B4–B1. Even when using the factory-trimmed set, the
user can still slightly modify the cutoff frequency (by
±250kHz) by varying bits LP1/LP0.
Highpass filters are also inserted in the back-end signal
paths. Their purpose is to remove the DC offset. They
are designed for a low corner frequency so as not to
degrade the SDARS content. Their exact cutoff frequency is set by the external capacitors connected between
IF2 access pins, given by the following equation:
fcutoff = 1/(2 x π x R x C) [Hz]
where R = 8000Ω, C = external capacitor to be
connected.
Finally, the HPF bit allows an increase to the back-end
gain by 4dB at the slight expense of a degraded inband linearity.
Frequency Generation
An on-chip VCO and a low-step fractional-N PLL
ensure the necessary frequency generation. The 1st
mixer’s LO is at the VCO frequency itself, while the 2nd
mixer’s LO is the VCO frequency divided by 4 or by 8
(bit D48). Hence, the two possible IF frequencies for
SDARS are 467MHz and 259MHz. Typical applications
are based on 259MHz IF frequency.
The reference divider path in the PLL can either use an
external crystal and the on-chip crystal oscillator or an
external TCXO that can overdrive the on-chip crystal
oscillator. A reference division ratio of 1 or 2 is set by
the REF bit. The crystal oscillator (or TCXO) signal is
available at pin REFOUT. The output is either at the
same frequency as the reference signal, or divided by
two, based on the setting of bit RFD.
The VCO main division ratio is set by bits N6–N0 (for
the integer part) and bits F19–F00 (for the fractional
part). The minimum step is below 30Hz, small enough
for effective AFC to be implemented by the baseband.
The charge-pump (pin CPOUT) is to be connected to
the VCO tuning input (pin VTUNE) through an appropriate loop filter.
Overcurrent Protection
This DC function allows external circuitry consuming up
to 150mA and connected to the pin VOUTANT to sink
current from a VCC line (pin VINANT) through overcurrent-protection circuitry.
When no overcurrent is present, a low dropout voltage
exists between pins VINANT and VOUTANT. In overcurrent conditions (including short-circuit from
VOUTANT to GND), the current is limited to approximately 300mA and bit ACP in the READ byte status
goes high.
This circuit also senses if the current drawn at the pin
VOUTANT is typically larger than 20mA, in which case
the bit AND from the READ byte status goes high (the
purpose is to inform the baseband controller if there is
any device drawing current from VOUTANT).
_______________________________________________________________________________________
9
MAX2140
Detailed Description
MAX2140
Complete SDARS Receiver
Applications Information
Serial Interface and Control Registers
I 2C Bit Description
MAX2140 Programming Bits:
The MAX2140 conforms to the Philips I 2C standard,
400kbps (fast mode), and operates as a slave.
The MAX2140 addresses can be selected from three
values, which are determined by the logic state of the
two address-select pins I2CA1 and I2CA2. In all cases,
the MSB is transmitted (and read) first.
MAX2140 I2C-Compatible Programming Bit Definition:
BYTE PLLint:
RFD = reference buffer division: RFD = 0 (/1) and
RFD = 1 (/2)
N6 to N0 is the binary-written main dividing ratio,
integer part.
BYTE PLLfrac2:
PLS = Reserved: use only PLS = 0
LI1/0 = Reserved: use only LI1 = LI0 = 0
INT = Integer N mode: INT = 1 (fractional) and INT =
0 (integer)
Table 1. MAX2140 Write Address Bytes
AS1
AS0
MSB
Low
High
High
High
Low
High
1
1
1
ADDRESS BYTE
1
1
1
0
0
0
0
0
0
LSB
0
0
0
0
1
1
1
0
1
0
0
0
Table 2. MAX2140 Read Address Bytes
AS1
AS0
MSB
Low
High
1
1
0
ADDRESS BYTE
0
0
0
1
LSB
1
High
Low
1
1
0
0
0
1
0
1
High
High
1
1
0
0
0
1
1
1
Table 3. MAX2140 Write Programming Bits
WRITE-TO MODE
Address
PLLint
RESET VALUE
ADDR (hex)
MSB
CONTROL BYTE
LSB
—
C2
C4
C6
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
01010110
00
RFD
N6
N5
N4
N3
N2
N1
N0
PLLfrac2
00011110
01
PLS
LI1
LI0
INT
F19
F18
F17
F16
PLLfrac1
10010000
02
F15
F14
F13
F12
F11
F10
F09
F08
PLLfrac0
01101001
03
F07
F06
F05
F04
F03
F02
F01
F00
Control
01100000
04
REF
CHP
D48
SDR
ANT
SDF
SDB
SDP
CustomGain
00000100
05
RF4
RF3
RF2
RF1
RF0
LP1
LP0
HPF
PMA_Test
00000000
06
PM3
PM2
PM1
PM0
SDX
T2
T1
T0
LPFTrim
00000000
09
0
0
IOT
B4
B3
B2A
B2
B1
Unused2
00000000
08
0
0
0
0
0
0
0
0
Unused1
00000000
07
0
0
0
0
0
0
0
0
Unused0
00000000
10
0
0
0
0
0
0
0
0
10
______________________________________________________________________________________
Complete SDARS Receiver
BYTES PLLfrac1 and PLLfrac0:
F15 to F0 is the lower-part binary-written main dividing ratio, fractional part multiplied by 220 = 1,048,576.
BYTE Control:
REF = reference division ratio: REF = 0 (/1) and REF
= 1 (/2)
CHP = charge-pump current: CHP = 0 (0.6mA) and
CHP = 1 (1.2mA)
B4/B3/B2/B2A/B1 = Reserved for LPF trim. All = 0 in
normal operating mode
IOT = LPF corner frequency setup: IOT = 0 (default
factory trim) and IOT = 1 (controllable through I2C).
IOT = 0 in normal operating mode
BYTE Status:
RF AGC = RF AGC status: RF AGC = 0 (is not
engaged) and RF AGC = 1 (engaged)
D48 = LO division ratio: D48 = 0 (/4) and D48 = 1 (/8)
SDR = shutdown RF AGC: SDR = 0 (on) and SDR =
1 (shutdown)
ACP = antenna current protection: ACP = 0 (no overcurrent) and ACP = 1 (overcurrent)
AND = antenna detection: ANT = 0 (current < threshold) and ANT = 1 (current > threshold)
LD = lock detect: LD = 0 (out of lock) and LD = 1
(lock)
BYTE Reserved:
Inactive at this time, all bits are 0
ANT = antenna overcurrent protection: ANT = 0 (on)
and ANT = 1 (shutdown)
SDF = shutdown front end: SDF = 0 (on) and SDF =
1 (shutdown)
SDB = shutdown back end: SDB = 0 (on) and SDB =
1 (shutdown)
SDP = shutdown PLL: SDP = 0 (on) and SDP = 1
(shutdown)
Register configuration for the LO generation
when the comparison frequency = 23.92MHz:
to generate 2078.893333MHz:
BYTE CustomGain:
RF4/RF3/RF2/RF1/RF0 = RF AGC engagement
threshold (dBm): see the RF AGC Settling Time
graph in the Typical Operating Characteristics.
LP1/LP0 = change by 250kHz the LPF corner frequency: LP1/LP0 = 10 (nominal), LP1/LP0 = 11
(decrease), LP1/LP0 = 00 (increase)
PLLint = 01010110, PLLfrac2 = 00011110,
PLLfrac1= 10010000, PLLfrac0 = 01101001
to generate 2067.777778MHz:
PLLint = 01010110, PLLfrac2 = 00010111,
PLLfrac1 = 00100001, PLLfrac0 = 00000010
to generate 1871.004000 MHz:
PLLint = 01001110, PLLfrac2 = 00010011,
PLLfrac1 = 10000001, PLLfrac0 = 11111000
to generate 1861.000000MHz:
PLLint = 01001101, PLLfrac2 = 00011100,
PLLfrac1 = 11010000, PLLfrac0 = 11101000
HPF = HPF gain increase by 4dB: HPF = 0 (off) and
HPF = 1 (on)
BYTE PMA_Test:
PM3/PM2/PM1/PM0 = PMA gain cutback (dB):
PM3/PM2/PM1/PM0DEC
SDX = shutdown reference buffer: SDX = 0 (on) and
SDX = 1 (shutdown)
Table 4. MAX2140 Read Programming Bits
READ-FROM MODE
Address
RESET VALUE
ADDRESS (hex)
MSB
—
C3
C5
C7
1
1
1
CONTROL BYTE
1
1
1
0
0
0
0
0
0
0
0
0
LSB
0
1
1
1
0
1
1
1
1
Reserved
00000000
00
0
0
0
0
0
0
0
0
Status
00000000
01
0
0
0
0
RFAGC
ACP
AND
LD
______________________________________________________________________________________
11
MAX2140
T2/T1/T0 = test bits: 000 (normal), 001 (main division), 010 (reference division), 011 (reserved),
100 (CHP low-Z), 101 (CHP source on), 110 (CHP
sink on), 111 (CHP high-Z)
BYTE LPFTrim:
F19 to F16 is the upper-part binary-written main
dividing ratio, fractional part multiplied by 2 20 =
1,048,576.
MAX2140
Complete SDARS Receiver
I 2C Functional Description
I2C Register Map:
This is the standard I2C protocol. The first byte is either
C6, C4, C2 (hex) dependent on the state of the I2CA_
pins, for a write-to-device operation and either C7, C5,
C3 (hex) for a read-from operation (again dependent
on the state of pins I2CA_).
Write Operation:
The first byte is the device address plus the direction
bit (R/W = 0).
The second byte contains the internal address command of the first address to be accessed.
Power-Supply Layout
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central
VCC node. The VCC traces branch out from this node,
each going to a separate VCC node in the MAX2140
circuit. At the end of each trace is a bypass capacitor
with impedance to ground less than 1Ω at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass
capacitor for a low-inductance ground connection.
Matching Network Layout
The layout of a matching network can be very sensitive
to parasitic circuit elements. To minimize parasitic
inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and
any other planes) below the matching network components can be used. On the high-impedance ports (e.g.,
IF inputs and outputs), keep traces short to minimize
shunt capacitance.
The third byte is written to the internal register directed
by the command address byte.
The following bytes (if any) are written into successive
internal registers.
The transfer lasts until stop conditions are encountered.
The MAX2140 acknowledges every byte transfer.
Read Operation:
When either address C3, C5, C7 is sent, the MAX2140
sends back first the status byte then the reserved byte.
See Table 5 and Table 6 for read/write register operations.
Chip Information
TRANSISTOR COUNT: 22,000
PROCESS: BiCMOS
Layout Issues
The MAX2140 EV kit can be used as a starting point for
layout. For best performance, take into consideration
power-supply issues, as well as the RF, LO, and IF layout.
Table 5. Example: Write Registers 1 to 3 with 0E, D8, 26
Device Address Write
(C2, C4, C6)
ACK
Register Address 00
ACK DATA 0E
ACK
DATA D8
ACK
DATA 26
ACK
STOP
Table 6. Example: Read from Status Registers (Sending an NACK Terminate Slave
Transmit Mode
Start
Device Address Read (C1, C3, C5, C7)
ACK
Status Register 00
ACK/\NACK
STOP
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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