BF1005S... Silicon N-Channel MOSFET Tetrode • For low noise, high gain controlled input stages up to 1 GHz • Operating voltage 5 V • Integrated biasing network Drain AGC HF Input G2 G1 HF Output + DC GND EHA07215 ESD: Electrostatic discharge sensitive device, observe handling precaution! Type Package Pin Configuration Marking BF1005S SOT143 1=S 2=D 3=G2 4=G1 - - NZs BF1005SR SOT143R 1=D 2=S 3=G1 4=G2 - - NZs BF1005SW SOT343 1=D 2=S 3=G1 4=G2 - - NZ Maximum Ratings Parameter Symbol Value Drain-source voltage VDS Continuous drain current ID 25 Gate 1/ gate 2-source current ±IG1/2SM 10 Gate 1 (external biasing) +VG1SE 3 Total power dissipation Ptot 8 Unit V mA V mW TS ≤ 76 °C, BF1005S, BF1005SR 200 TS ≤ 94 °C, BF1005SW 200 Storage temperature Tstg -55 ... 150 Channel temperature Tch 150 °C Note: It is not recommended to apply external DC-voltage on Gate 1 in active mode. 1 Feb-18-2004 BF1005S... Thermal Resistance Parameter Symbol Channel - soldering point 1) Rthchs Value Unit K/W BF1005S, BF1005SR ≤ 370 BF1005SW ≤ 280 Electrical Characteristics Parameter Symbol Values Unit min. typ. max. V(BR)DS 12 - - +V(BR)G1SS 8 - 12 ±V (BR)G2SS 8 - 13 +IG1SS - 100 - µA ±IG2SS - - 50 nA IDSS - - 800 µA IDSO 8 13 16 mA VG2S(p) - 1 - DC Characteristics Drain-source breakdown voltage V ID = 650 µA, VG1S = 0 , VG2S = 0 Gate1-source breakdown voltage +IG1S = 10 mA, V G2S = 0 , VDS = 0 Gate2 source breakdown voltage ±IG2S = 10 mA, VG1S = 0 , V DS = 0 Gate1-source leakage current VG1S = 6 V, VG2S = 0 Gate 2 source leakage current ±V G2S = 8 V, VG1S = 0 , V DS = 0 Drain current VDS = 5 V, VG1S = 0 , VG2S = 4 V Operating current (selfbiased) VDS = 5 V, VG2S = 4 V Gate2-source pinch-off voltage V VDS = 5 V, I D = 100 µA 1For calculation of R thJA please refer to Application Note Thermal Resistance 2 Feb-18-2004 BF1005S... Electrical Characteristics Parameter AC Characteristics Symbol Values Unit min. typ. max. 26 30 - mS Cg1ss - 2.4 2.7 pF Cdss - 1.3 - 20 22 - dB - 1.6 2.1 dB 40 50 - (verified by random sampling) Forward transconductance g fs VDS = 5 V, V G2S = 4.5 V Gate1 input capacitance VDS = 5 V, V G2S = 4 V, f = 1 MHz Output capacitance VDS = 5 V, V G2S = 4 V, f = 100 MHz Power gain (self biased) Gp VDS = 5 V, V G2S = 4 V, f = 800 MHz Noise figure F VDS = 5 V, V G2S = 4 V, f = 800 MHz ∆G p Gain control range VDS = 5 V, V G2S = 4 V ... 0 V, f = 800 MHz 3 Feb-18-2004 BF1005S... Total power dissipation Ptot = ƒ(TS) Total power dissipation Ptot = ƒ(TS) BF1005S, BF1005SR BF1005SW 220 220 mA 180 180 160 160 P tot P tot mW 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 15 30 45 60 75 90 105 120 °C 0 0 150 15 30 45 60 75 90 105 120 °C TS 150 TS Drain current ID = ƒ(VG2S) Insertion power gain |S21|² = ƒ(VG2S) 20 15 mA dB 16 -5 |S21|² ID 14 12 10 -15 -25 8 -35 6 -45 4 -55 2 0 0 0.5 1 1.5 2 2.5 3 3.5 V -65 0 4.5 VG2S 0.5 1 1.5 2 2.5 3 3.5 V 4.5 VG2S 4 Feb-18-2004 BF1005S... Forward transfer admittance Gate 1 input capacitance Cg1ss= ƒ(Vg2s) |Y21| = ƒ(VG2S) f = 200MHz 40 3 mS pF C g1ss |Y 21| 32 28 24 20 2 1.5 16 1 12 8 0.5 4 0 0 0.5 1 1.5 2 2.5 3 3.5 V 0 0 4.5 VG2S 0.5 1 1.5 2 2.5 3 3.5 V 4.5 VG2S Output capacitance C dss = ƒ(VG2S) f = 200MHz 3 Cdss pF 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 V 4.5 VG2S 5 Feb-18-2004