1M × 16-Bit Dynamic RAM 1k Refresh (Fast Page Mode) HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 Advanced Information • 1 048 576 words by 16-bit organization • 0 to 70 °C operating temperature • Fast Page Mode operation • Performance: -50 -60 tRAC RAS access time 50 60 ns tCAC CAS access time 13 15 ns tAA Access time from address 25 30 ns tRC Read/Write cycle time 84 104 ns tPC Fast page mode cycle time 35 40 ns • Power Dissipation, Refresh & Addressing: HYB5118160 -50 Power Supply Addressing -50 -60 5 V ± 10 % 3.3 V ± 0.3 V 10/10 10/10 Refresh Active -60 HYB3118160 1024 cycles / 16 ms 715 632 468 414 mW TTL Standby 11 7.2 mW CMOS Standby 5.5 3.6 mW • Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh and hidden refresh • All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible • Plastic Package: Semiconductor Group P-SOJ-42-1 400 mil 1 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM The HYB 5(3)118160 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized as 1 048 576 words by 16-bits. The HYB 5(3)118)160 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)118160 to be packaged in a standard SOJ-42 plastic package with 400 mil width. This package provide high system bit densities and is compatible with commonly used automatic testing and insertion equipment. Ordering Information Type Ordering Code Package Descriptions HYB 5118160BSJ-50 Q67100-Q1072 P-SOJ-42-1 400 mil 5V 50 ns FPM-DRAM HYB 5118160BSJ-60 Q67100-Q1073 P-SOJ-42-1 400 mil 5V 60 ns FPM-DRAM HYB 3118160BSJ-50 on request P-SOJ-42-1 400 mil 3.3 V 50 ns FPM-DRAM HYB 3118160BSJ-60 on request P-SOJ-42-1 400 mil 3.3 V 60 ns FPM-DRAM Pin Names HYB 5(3)118160 Row Address Inputs A0 - A9 Column Address Inputs A0 - A9 Row Address Strobe RAS Upper Column Address Strobe UCAS Lower Column Address Strobe LCAS Output Enable OE Data Input/Output I/O1 - I/O16 Read/Write Input WE Power Supply VCC Ground (0 V) VSS Not Connected N.C. Semiconductor Group 2 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM P-SOJ-42 (400 mil) V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. N.C. A0 A1 A2 A3 V CC 42 V SS 41 I/O16 40 I/O15 39 I/O14 38 I/O13 37 V SS 36 I/O12 35 I/O11 34 I/O10 33 I/O9 32 N.C. 31 LCAS 30 UCAS 29 OE 28 A9 27 A8 26 A7 25 A6 24 A5 23 A4 22 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SPP02812 Pin Configuration Semiconductor Group 3 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM I/O1 I/O2 . . . I/O16 . . . Data In Buffer WE UCAS LCAS Data Out Buffer OE 16 & 16 No.2 Clock Generator 10 Column Address Buffers (10) 10 Column Decoder A0 A1 Refresh Controller A2 A3 Sense Amplifier I/O Gating A4 16 A5 . .. 1024 x 16 A7 A8 . .. Refresh Counter (10) A6 10 A9 10 RAS Row Address Buffers (10) 10 Row Decoder .. . 1024 .. . Memory Array 1024 x 1024 x 16 No.1 Clock Generator Voltage Down Generator V CC V CC (internal) SPB02826 Block Diagram for HYB 5118160BSJ Semiconductor Group 4 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 °C Storage temperature range........................................................................................ – 55 to 150 °C Input/output voltage (5 V versions) .................................................... – 0.5 to min (VCC + 0.5, 7.0) V Input/output voltage (3.3 V versions) ................................................. – 0.5 to min (VCC + 0.5, 4.6) V Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V Power dissipation (5 V versions) ............................................................................................. 1.0 W Power dissipation (3.3 V versions) .......................................................................................... 0.5 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition V 5 V Versions Power supply voltage VCC 4.5 5.5 Input high voltage VIH 2.4 VCC + 0.5 V 1 Input low voltage VIL – 0.5 0.8 V 1 Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1 Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1 Power supply voltage VCC 3.0 3.6 V Input high voltage VIH 2.0 VCC + 0.5 V 1 Input low voltage VIL – 0.5 0.8 V 1 TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1 TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1 CMOS Output high voltage (IOUT = – 100 µA) VOH VCC – 0.2 – V CMOS Output low voltage (IOUT = 100 µA) VOL – V Semiconductor Group 5 3.3 V Versions 0.2 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns Parameter Symbol Limit Values Unit Notes min. max. Common Parameters Input leakage current (0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V) IO(L) – 10 10 µA 1 Average VCC supply current ICC1 – – 130 115 mA mA 2, 3, 4 ICC2 – 2 mA – Average VCC supply current, during RAS-only refresh ICC3 cycles -50 ns version -60 ns version (RAS cycling, CAS = VIH, tRC = tRC MIN.) – – 130 115 mA mA 2, 4 Average VCC supply current, during fast page mode -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: tPC = tPC MIN.) ICC4 – – 40 30 mA mA 2, 3, 4 Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 – 1 mA 1 Average VCC supply current, during CAS-before-RAS ICC6 refresh mode -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC MIN.) – – 130 115 mA mA 2, 4 -50 ns version -60 ns version (RAS, CAS, address cycling: tRC = tRC MIN.) Standby VCC supply current (RAS = CAS = VIH) Semiconductor Group 6 2, 3, 4 2, 4 2, 3, 4 2, 4 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM Capacitance TA = 0 to 70 °C, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11) CI1 – 5 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1 - I/O16) CIO – 7 pF AC Characteristics 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. Common Parameters Random read or write cycle time tRC 90 – 110 – ns RAS precharge time tRP 30 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 13 10k 15 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 8 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 10 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 RAS to column address delay time tRAD 13 25 15 30 ns RAS hold time tRSH 13 – 15 – ns CAS hold time tCSH 50 – 60 – ns CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 ns Refresh period for 1k-refresh version tREF – 16 – 16 ms Access time from RAS tRAC – 50 – 60 ns 8 ,9 Access time from CAS tCAC – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8, 10 OE access time tOEA – 13 – 15 ns 7 Read Cycle Semiconductor Group 7 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. Column address to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 Output buffer turn-off delay from OE tOEZ 0 13 0 15 ns 12 Data to OE low delay tDZO 0 – 0 – ns 13 CAS high to data delay tCDD 13 – 15 – ns 14 OE high to data delay tODD 13 – 15 – ns 14 Write command hold time tWCH 8 – 10 – ns Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – ns Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS 0 – 0 – ns 16 Data hold time tDH 10 – 10 – ns 16 Data to CAS low delay tDZC 0 – 0 – ns 13 Read-write cycle time tRWC 126 – 150 – ns RAS to WE delay time tRWD 68 – 80 – ns 15 CAS to WE delay time tCWD 31 – 35 – ns 15 Column address to WE delay time tAWD 43 – 50 – ns 15 OE command hold time tOEH 13 – 15 – ns Fast page mode cycle time tPC 35 – 40 – ns CAS precharge time tCP 10 – 10 – ns Write Cycle 15 Read-Modify-Write Cycle Fast Page Mode Cycle Semiconductor Group 8 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. Access time from CAS precharge tCPA – 30 – 35 ns RAS pulse width tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHPC 30 – 35 – ns Fast page mode read-write cycle time tPRWC 71 – 80 – ns CAS precharge to WE tCPWD 48 – 55 – ns CAS setup time tCSR 10 – 10 – ns CAS hold time tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – ns tCPT 35 – 40 – ns 7 Fast Page Mode Read-Modify-Write Cycle CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Semiconductor Group 9 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 100 pF and at VOH = 2.0 V (IOH = – 2 mA), VOL = 0.8 V (IOL = 2 mA). 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.) , the cycle is a readwrite cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 10 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RP t RAS VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CRP t CAS VIH VIL t RAD t ASR t RAL t CAH t ASC t ASR VIH Address Row VIL Column Row t RAH t RCH t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t DZO I/O (Inputs) t ODD VIH VIL t OFF t CAC t CLZ VOH I/O (Outputs) V OL Hi Z t OEZ Valid Data OUT Hi Z t RAC "H" or "L" SPT03043 Read Cycle Semiconductor Group 11 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CAS VIH t CRP VIL t RAL t RAD t ASR t ASC t CAH t ASR VIH Address Row VIL Column t RAH t CWL t WCS VIH Row t WP WE VIL t WCH t RWL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03044 Write Cycle (Early Write) Semiconductor Group 12 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CAS VIH t CRP VIL t RAD t RAL t CAH t ASC t ASR t ASR VIH Address Row VIL Column Row t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t ODD t DZO t DZC I/O (Inputs) t DH t DS VIH Valid Data VIL t CLZ t OEZ t OEA VOH I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03045 Write Cycle (OE Controlled Write) Semiconductor Group 13 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RWC t RAS VIH RAS VIL t CSH t RP t RSH t RCD UCAS LCAS t CAS t CRP VIH VIL t RAH t ASR t CAH t ASC t ASR VIH Address Row Column Row VIL t RAD t CWL t AWD t RWL t CWD t RWD t WP VIH WE VIL t AA t RCS t OEA t OEH VIH OE VIL t DZC t DS t DZO I/O (Inputs) t DH VIH Valid Data IN VIL t ODD t CAC t OEZ t CLZ VOH I/O (Outputs) V OL Data OUT t RAC "H" or "L" SPT03046 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RASP VIH RAS VIL t PC t CAS t RCD t RHCP t CAS t RSH t CP UCAS LCAS t RP t CRP t CAS VIH VIL t RAH t ASR t ASC t CSH t CAH t ASC t CAH t CAH t ASR t ASC VIH Address Row Column Column VIL Column Row t RCH t RAD t RCS t RCH t RCS t RCS t RRH VIH WE VIL t RAC t CPA t AA t AA t OEA t CPA t AA t OEA t OEA VIH OE VIL t DZC t DZC t DZO t DZC t DZO t DZO t ODD I/O (Inputs) t CDD t ODD t ODD VIH VIL t OFF t OFF t OEZ t CAC I/O (Outputs) V OL t OEZ t CAC t CLZ VOH t OEZ t CAC t CLZ Valid Data OUT t OFF t CLZ Valid Data OUT Valid Data OUT "H" or "L" SPT03047 Fast Page Mode Read Cycle Semiconductor Group 15 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RASP VIH RAS VIL t PC t CAS t RCD UCAS LCAS t RP t RSH t CAS t CAS t CP t CRP VIH VIL t RAH t ASR t ASC t RAL t CAH t ASC t CAH t CAH t ASC t ASR VIH Address Row Column Column Column Row VIL t RAD t WCS t CWL t CWL t WCS t WCH t WCS t WCH t WP t RWL t CWL t WCH t WP t WP VIH WE VIL VIH OE VIL t DS I/O (Inputs) VIH t DH Valid Data IN VIL t DH t DS Valid Data IN VOH I/O (Outputs) V OL t DS t DH Valid Data IN Hi Z "H" or "L" SPT03048 Fast Page Mode Early Write Cycle Semiconductor Group 16 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RAS VIH RAS VIL t CSH t RP t PRWC t CP t RCD UCAS LCAS t CAS t RSH t CAS t CAS t CRP VIH VIL t ASR t RAD t RAH t ASC t RAL t CAH t CAH t CAH t ASC t ASC t ASR VIH Address VIL Row Column Column t RWD t CWD t RCS Column t CPWD t CWD t CWL Row t CPWD t CWD t CWL t RWL t CWL VIH WE VIL t AWD t AA t AWD t WP t OEA t AWD t WP t OEA t WP t OEA t OEH t OEH t OEH VIH OE VIL t CLZ t DZC t CLZ t ODD t CLZ t CPA t ODD t DZC t DZO VIH I/O (Inputs) V IL Data IN t CAC t RAC VOH I/O (Outputs) V t OEZ t CPA t ODD Data IN t DH t DS t DZC Data IN t DH t AA t DS t OEZ Data OUT Data OUT t DH t CAC t DS t AA t OEZ Data OUT OL "H" or "L" SPT03049 Fast Page Mode Late Write and Read-Modify-Write Cycle Semiconductor Group 17 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RAS t RP VIH RAS VIL t CRP t RPC UCAS LCAS VIH VIL t RAH t ASR t ASR VIH Address Row Row VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03050 RAS-only Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RP t RAS t RP VIH RAS VIL t RPC t CP t CHR t RPC t CSR UCAS LCAS t CRP VIH VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ VOH Hi Z I/O (Outputs) V OL t OFF "H" or "L" SPT03051 CAS-before-RAS Refresh Cycle Semiconductor Group 19 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RC t RP t RP t RAS t RAS VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t WRP t RAH t ASR t WRH t CAH t ASR VIH Address Row VIL Column Row t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t ODD t DZO I/O (Inputs) VIH VIL t CLZ t CAC t OFF t RAC t OEZ VOH I/O (Outputs) V OL Valid Data OUT "H" or "L" Hi Z SPT03053 Hidden Refresh Cycle (Read) Semiconductor Group 20 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM t RC t RC t RAS t RP t RAS t RP VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR t ASR t CAH VIH Address Row VIL Column Row t WCS t WCH t WP t WRH t WRP VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL VOH I/O (Output) V OL Hi Z "H" or "L" SPT03054 Hidden Refresh Cycle (Early Write) Semiconductor Group 21 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM Read Cycle t RAS t RP VIH RAS VIL t CHR t CSR UCAS LCAS t RSH t CP VIH t CAS VIL t RAL t CAH t ASR t ASC VIH Column Address VIL t WRP Row t AA t RRH VIH WE VIL t WRH t CAC t RCS t RCH t OEA VIH OE VIL t CDD t DZC I/O (Inputs) VIH t ODD VIL t OFF t DZO t OEZ t CLZ VOH I/O (Outputs) V OL Write Cycle Data OUT t WCS t RWL t WRP t CWL t WCH VIH WE VIL t WRH t DH VIH OE VIL t DS I/O (Inputs) VIH Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03055 CAS-before-RAS Refresh Counter Test Cycle Semiconductor Group 22 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM Package Outlines GPJ05853 Plastic Package P-SOJ-42-1 (SMD) (400mil) (Plastic small outline J-leaded) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 23 Dimensions in mm 1998-10-01 HYB 5118160BSJ-50/-60 HYB 3118160BSJ-50/-60 1M × 16 DRAM 0.8 15˚ ±5˚ 24x 0.8 = 19.2 10.16 ±0.13 2) 0.15 +0.06 -0.03 1 ±0.05 15˚ ±5˚ 0.1±0.05 Plastic Package P-TSOPII-50/44-1 (400 mil) (SMD) (Plastic Thin Small Outline Package (Type II)) 0.1 50x 0.5 ±0.1 11.76 ±0.2 0.2 M 50x 3) 0.4 +0.05 -0.1 40 36 26 1 11 15 2.5 max 25 6 max 50 20.95 ±0.13 1) GPX05958 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 24 Dimensions in mm 1998-10-01