Data Sheet No PD94723 revA IR3622AMPbF HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING Description Features • • • • • • • • • • • • • • • • • • Dual Synchronous Controller with 180o Out of Phase Operation Configurable to 2-Independent Outputs or Current Shared Single Output Output Voltage Tracking Power up / down Sequencing Current Sharing Using Inductor’s DCR +/-1% Accurate Reference Voltage Programmable Switching Frequency up 600kHz Programmable Over Current Protection Hiccup Current Limit Using MOSFET Rds(on) sensing Latched Overvoltage Protection Dual Programmable Soft-Starts Programmable Enable Input Pre-Bias Start-up Dual Power Good Outputs On Board Regulator External Frequency Synchronization Thermal Protection 32-Lead MLPQ Package Applications • • • • • Embedded Telecom Systems Distributed Point of Load Power Architectures Computing Peripheral Voltage Regulator Graphics Card General DC/DC Converters The IR3622A IC integrates a dual synchronous Buck controller, providing a high performance and flexible solution. The IR3622A can be configured as 2-independent outputs or as current shared single output. The current share configuration is ideal for high current applications. The IR3622A enables output tracking and sequencing of multiple rails in either ratiometric or simultaneous fashion. The IR3622A features 180o out of phase operation which reduces the required input/output capacitance and results in lower number of capacitors. The switching frequency is programmable from 200kHz to 600kHz per phase using one external resistor. In addition, IR3622A also allows the switching frequency to be synchronized to an external clock signal. Other key features offered by this device include two independent programmable soft starts, two independent power good outputs, precision enable input, and under voltage lockout function. The current limit is provided by sensing the lower MOSFET's on-resistance for optimum cost and performance. The output voltages are monitored through dedicated pins to protect against open circuit, and enhance faster response to an overvoltage event. Vin Rt IR3622A Comp2 Vo1 Vo2 Vo2 HDrv1 OCSet1 Comp1 Vo1 Vout1 LDrv1 Ratiometric Powerup PGnd1 Vin SS1 / SD Ratiometric Powerdown Vo1 Vo1 Vo2 Vo2 SS2 / SD Vout1 HDrv2 Track OCSet2 Gnd PGnd2 Vout2 LDrv2 Simultaneous Powerup Simultaneous Powerdown ORDERING INFORMATION PKG DESIG M M www.irf.com PACKAGE DESCRIPTION IR3622AMPbF IR3622AMTRPbF PIN PARTS PARTS COUNT PER TUBE PER REEL 32 73 ------32 -------3000 T&R ORIANTAION Fig A 03/21/07 IR3622AMPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) •Vcc, VcL Supply Voltage .....................................… -0.5V to 16V •VcH1,VcH2 ……………………….………….……… -0.5V to 30V •PGood1, PGood2 ………. .…………………………. -0.5V to 16V •HDrv1, HDrv2 ………………………………………… -0.5V to 30V (-2V for 100ns) •LDrv1, LDrv2 ………………………………………… -0.5V to 16V (-2V for 100ns) •Gnd to PGnd ……………………………………….. +/- 0.3V •Storage Temperature Range .................................. -65°C To 150°C •Operating Junction Temperature Range ................ -40°C To 125°C •ESD Classification ………………………………..… JEDEC, JESD22-A114 (1KV) •Moisture Sensitivity Level ………………………….. JEDEC, Level 3 @ 260oC Caution: Stresses above those listed in “Absolute Maximum Rating” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability. VP 28 27 26 25 1 VP 29 2 PG oo d1 Gn d VR 30 31 EF Vc c 32 UT 3 Tra ck VO Package Information Rt 1 24 PGood2 VSEN2 2 23 Sync 3 Comp2 4 22 VSEN1 Fb2 SS2/SD2/Mode 21 Fb1 Pad 5 20 Comp1 OCSet2 6 19 SS1/SD1 VcH2 7 18 OCSet1 HDrv2 8 17 12 VcL 10 13 14 15 16 LD rv1 PG nd 1 Se q HD rv1 11 En ab le PG nd 2 LD rv2 9 VcH1 ΘJA = 36o C/W ΘJC = 1o C/W *Exposed pad on underside is connected to a copper pad through vias for 4-layer PCB board design www.irf.com 2 IR3622AMPbF Recommended Operating Conditions Symbol Definition Min Max Units Vcc, VcL VcH1, VcH2 Fs Supply Voltage Supply Voltage Operating frequency 4.5 Converter Voltage + 5V 200 14.5 28 600 V V kHz Tj* Junction temperature -40 125 o C * The Operating Junction Temperature for 5V application is 0oC-125oC Electrical Specifications Unless otherwise specified, these specification apply over Vcc=VcL=VcH1=VcH2=12V, 0oC<Tj<105oC Parameter SYM Test Condition Min TYP MAX Units -1 +1 % -1.5 +1.5 Output Voltage Accuracy FB1,2 Voltage VFB Vp1=Vp2=Vref=0.8V o Accuracy o 0 C <Tj< 125 C o o -40 C <Tj< 125 C; Note2 0.8 V % Supply Current VCC Supply Current (Static) VCC Supply Current (Dynamic) VCL Supply Current (Static) ICC (Static) ICC (Dynamic) ICL (Static) VCL Supply Current (Dynamic) ICL (Dynamic) VCH1,2 Supply Current (Static) ICH (Static) VCH1,2 Supply Current (Dynamic) ICH (Dynamic SS=0V, No Switching 13 18 mA Fs=300kHz, CLOAD= 3.3nF 20 30 mA SS=0V, No Switching 8 10 mA Fs=300kHz, CLOAD= 3.3nF 30 42 mA SS=0V, No Switching 9 11 mA Fs=300kHz, CLOAD= 3.3nF 30 42 mA V Under Voltage Lockout, Enable VCC-Start Threshold VCC_UVLO(R) Supply ramping up 3.9 4.1 4.3 VCC-Stop Threshold VCC_UVLO(F) Supply ramping down 3.7 3.8 4.1 V Supply ramping up and down 0.15 0.25 0.3 V Supply ramping up 1.14 1.24 1.34 V Supply ramping up and down 0.15 0.22 0.33 V 600 kHz +12 % VCC-Hysteresis Enable-Threshold En_UVLO Enable-Hysteresis Oscillator Frequency Range FS Accuracy Ramp Amplitude Fs=300kHz Vramp Min Duty Cycle Dmin Min Pulse Width Dmin(ctrl) Max duty Cycle Dmax Sync Frequency Range Sync Pulse Duration Sync High Level Threshold Sync Low Level Threshold www.irf.com 200 Sync(F) -12 Note1 1.25 Fb=1V FS=300kHz, Note1 FS=300kHz, Fb=0.6V V 0 % 150 ns 84 % 20% above free running Freq 1200 Sync(Pulse) 200 Sync(H) Sync(L) 2 300 kHz ns 0.6 V V 3 IR3622AMPbF Electrical Specifications Parameter SYM Test Condition Min TYP MAX Units -0.1 -0.5 µA 200 280 µA 4500 µmho +4 mV Vcc-2 V 7.7 V Error Amplifier 1, 2 Fb Voltage Input Bias Current E/A Source/Sink Current Transconductance IFB SS=3V I(source/Sink) 120 gm1,2 Input offset Voltage VP Voltage Range Voffset VP 3000 Fb to Vref -4 Note1 0.4 0 Internal Regulator Output Accuracy Vout3 Dropout Vdrop Current Limit 6.7 7.2 Vcc(min)=9V, Isource=100mA Ishort 2 110 V mA Soft Start/SD Soft Start Current ISS Shutdown Threshold SD Source/Sink 18 23 28 µA 0.25 V Over Current Protection OCSET Current Hiccup Duty Cycle IOCSET Hiccup(duty) 16 20 5 24 µA % 1.1Vref 1.15Vref 1.2Vref V 5 µs Ihiccup / Iocset, Note1 Over Voltage Protection OVP Trip Threshold OVP Fault Prop Delay OVP(trip) OVP(delay) Output Forced to 1.25Vref Thermal Shutdown Note1 Thermal shutdown Thermal shutdown Hysteresis o 140 20 Note1 o C C Power Good Vsen Lower Trip point PGood Output Low Voltage Vsen(trip) PG(voltage) Vsen Ramping Down 0.8Vref IPGood=2mA 0.9Vref 0.95Vref V 0.1 0.5 V Output Drivers LO, Drive Rise Time Tr(Lo) CLOAD=3.3nF, Fs=300KHz, 2V to 9V 25 50 ns LO Drive Fall Time Tf(Lo) CLOAD =3.3nF, Fs=300KHz, 9V to 2V 25 50 ns HI Drive Rise Time Tr(Hi) 25 50 ns HI Drive Fall Time Tf(Hi) CLOAD =3.3nF, Fs=300KHz, 9V to 2V 25 50 ns Dead Band Time Tdead See Figure1 20 60 100 ns On Off 2.0 CLOAD =3.3nF, Fs=300KHz, 2V to 9V Seq Input Seq Threshold Seq V 0.3 Tracking Track voltage range www.irf.com TK Note1 0 Vcc V 4 IR3622AMPbF Note1: Guaranteed by design but not test in production Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production Tr Tf 9V High Side Driver (HDrv) 2V Tr Tf 9V Low Side Driver (LDrv) 2V Deadband H_to_L Deadband L_to_H Fig. 1: Rise / Fall and deadband time for driver section www.irf.com 5 IR3622AMPbF Pin# Pin Name Description 1 Rt 2 VSEN2 Connecting a resistor from this pin to ground sets the switching frequency (see figure 16 on page 17 for selecting resistor value) Sense pin for OVP2 and Power Good2, Channel 2 3 Fb2 Inverting input to the error amplifier2 4 5 Comp2 SS2/SD2/Mode 6 OCSet2 Compensation pin for the error amplifier2 Soft start for channel 2, can be used as SD pin. Float this pin for current share single output application Current limit set point for channel2 7, 17 VcH2, VcH1 8,16 HDrv2, HDrv1 Supply voltage for the high side output drivers. These are connected to voltage that must be typically 6V higher than their bus voltages. A 0.1uF high frequency capacitor must be connected from these pins to PGND to provide peak drive current capability Output drivers for the high side power MOSFETs Enable Enable pin, recycling this pin will reset OV, SS and Prebias latch 10, 14 PGnd2, PGnd1 11, 13 LDrv2 , LDrv1 These pins serve as the separate grounds for MOSFET drivers and should be connected to the system’s ground plane Output drivers for the synchronous power MOSFETs 12 VcL Supply voltage for the low side output drivers 15 Seq 18 OCSet1 Enable pin for tracking and sequencing. If this pin is not used connect it to Vout3 Current limit set point for Channel 1 19 SS1/SD1 Soft start for Channel 1, can be used as SD pin 20 Comp1 Compensation pin for the error amplifier1 21 Fb1 Inverting input to the error amplifier1 22 VSEN1 Sense pin for OVP1 and Power Good1, Channel 1 23 Sync External synchronization pin 24 PGood2 25 VP1 Power Good pin output for channel 2, open collector. This pin needs to be externally pulled high Non inverting input of error amplifier1 26 VP2 Non inverting input of error amplifier2 27 VREF Reference Voltage 28 Gnd IC’s Ground 29 PGood1 30 Vcc 31 Vout3 32 Track Power Good pin output for Channel 1, open collector. This pin needs to be externally pulled high Supply voltage for the internal blocks of the IC. A 0.1uF high frequency capacitor must be connected from this pin to Gnd. Output of the internal regulator. A 0.1uF high frequency capacitor must be connected from this pin to PGnd. Sets the type of power up / down sequencing (ratiometric or simultaneous). If this pin is not used connect it to Vout3 9 www.irf.com 6 IR3622AMPbF Block Diagram 0.3V Enable S POR SS1 Vcc Q 23uA 23uA Seq Mode SS2 / SD 3V Bias Generator 64uA UVLO SS1 / SD VcH1 0.8V 64uA PBias1 R POR HDrv1 VcH1 VcH2 POR PWM Comp1 Thermal Shutdown Error Amp1 OVP1 LDrv1 3uA R VP1 VCL SS1 PBias1 PGnd1 Q Fb1 Set1 Ramp1 Comp1 20uA Reset Dom Two Phase Oscillator Rt OCSet1 S Set2 Ramp2 VcH2 Reset Dom Sync S PWM Comp2 0.8V VREF Q R Error Amp2 Track HDrv2 SS1 Hiccup Control SS2 Mode OVP2 VP2 LDrv2 0.3V Fb2 S PBias2 Q Comp2 SS2 POR R S VSEN1 Q 1.15Vref POR PGnd2 SS2 OVP1 HDrv1 OFF / LDrv1 ON OCSet2 3uA 20uA R PGood1 0.90Vref SS1 / SD Vcc Q 1.15Vref POR VOUT3 Tracking Seq 23uA S VSEN2 Regulator OVP2 HDrv2 OFF / LDrv2 ON R PGood2 0.90Vref Gnd Fig. 2: Simplified block diagram of the IR3622A www.irf.com 7 IR3622AMPbF TYPICAL OPERATING CHARACTERISTICS (-40oC-125oC) VFb2 vs Tem perature 0.802 0.802 0.8015 0.8015 0.801 VF b 1 (V) VF b 1 (V) VFb1 vs Tem perature 0.8005 0.8 0.7995 0.799 0.801 0.8005 0.8 0.7995 0.799 0.7985 0.7985 0.798 -40 -20 0 20 40 60 80 100 120 -40 -15 10 Tem perature SS1 C u rren t (u A ) SS1 C u rren t (u A ) -20 -21 -22 -23 -24 -25 10 35 60 85 -20 -21 -22 -23 -24 -40 110 -15 10 V o u t3 (V ) Vcc_U V L O (V ) 4.12 4.1 4.08 4.06 4.04 4.02 4 35 60 Tem perature www.irf.com 60 85 110 85 110 Vout3 vs Temperature 4.2 4.18 4.16 4.14 10 35 Tem perature Vcc_UVLO vs Temperature -15 110 -19 Tem perature -40 85 SS2 Current vs Tem perature -19 -15 60 Tem perature SS1 Current vs Tem perature -40 35 85 110 7.29 7.27 7.25 7.23 7.21 7.19 7.17 7.15 7.13 7.11 7.09 7.07 7.05 -40 -15 10 35 60 Tem perature 8 IR3622AMPbF TYPICAL OPERATING CHARACTERISTICS (-40oC-125oC) IOCSET1 vs Temperature IOCSET2 vs Tem perature 22 IO C SET 1 (u A ) IO C SE T 1 ( u A ) 22 21.5 21 20.5 20 19.5 21.5 21 20.5 20 19.5 19 18.5 18 19 -40 -15 10 35 60 85 -40 110 -15 10 Temperature 60 85 110 85 110 GM2 vs Temperature 4100 4100 4000 4000 G M 1 (u m h o ) G M 1 (u m h o ) GM1 vs Temperature 3900 3800 3700 3600 3500 3400 3900 3800 3700 3600 3500 3400 -40 -15 10 35 60 85 110 -40 -15 10 Tem perature 300 290 280 10 35 60 Tem perature www.irf.com 85 110 M ax D u ty C ycle (% ) 310 -15 60 Max Duty Cycle vs Tem perature 320 -40 35 Tem perature Freq 300kHz vs Tem perature PW M 1 F req (K H z ) 35 Temperature 96 94 92 90 88 86 84 -40 -15 10 35 60 85 110 Tem perature 9 IR3622AMPbF Circuit Description THEORY OF OPEARTION Introduction Enable The IR3622A is a versatile device for high performance buck converters. It consists of two synchronous buck controllers which can be operated either in two independent outputs mode or in current share single output mode for high current applications. The enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by under-voltage lockout circuit. It’s threshold can be externally programmed to desired level by using two external resistors, so the converter doesn’t start up until the input voltage is sufficiently high (see figure 3). The timing of the IC is provided by an internal oscillator circuit which generates two-180o-out-ofphase clock that can be externally programmed up to 600kHz per phase. Under-Voltage Lockout The under-voltage lockout circuit monitors two signals (Vcc and Enable). This ensures the correct operation of the converter during power up and power down sequence. The driver outputs remain in the off state whenever one of these signals drop below set thresholds. Normal operation resumes once these signals rise above the set values. Figure 3 shows a typical start up sequence. 12V 11V 12V 4.1V 7.2V Vbus Vcc Vout3 Seq Enable OK (IC's POR) 3V Enable SS Fig. 3: Normal Start up, Enable threshold is externally set to 11V Seq pin is pulled to Vout3 prior to start up www.irf.com 10 IR3622AMPbF In addition, the 180o out of phase contributes to input current cancellation. This results in much smaller input capacitor’s RMS current and reduces the number of required input capacitors. Figure 5 shows the equivalent RMS current. Internal Regulator RMS Current Normalized (IRMS/Iout) The IR3622A features an on-board 7.2V regulator with short circuit protection. The regulator is capable of sourcing current up to 100mA. This integrated regulator can be used to generate the necessary bias voltage for drivers, an example of how this can be used is shown in figure 23, page26. Out-of-Phase Operation The IR3622A drives its two output stages 180o out-of-phase. In current share mode single output, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same voltage ripple requirement. Figure 4 shows two channels inductor current and the resulting voltage ripple at the output. Single Phase 2 Phase Duty Cycle (Vo/Vin) Fig. 5: Input RMS value vs. Duty Cycle HDRV1 Mode Selection 0 DT The IR3622A can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (current share mode). The SS2 pin is used for mode selection. In current share mode this pin should be floating. In the dual output mode, a soft start capacitor must be connected from this pin to the ground to program the start time for the second output. T HDRV2 IL1 IL2 Independent Mode Ic Io Fig. 4: Current ripple cancellation for output www.irf.com In this mode the IR3622A provides control to two independent output power supplies with either common or different input voltages. The output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. The error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (PWM) which are applied to the internal MOSEFT drivers. Figure 24 shows a typical schematic for such application. 11 IR3622AMPbF Master Phase Vin Current Share Mode IL1 This feature allows to connect both outputs together to increase current handling capability of the converter to support a common load. In the current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, figure 6 shows the configuration of error amplifier 2. In this mode, IR3622A makes sure the master channel starts first followed by slave channel to prevent any glitch during start up. This is done by clamping the output of slave’s error amplifier until the master channel generates the first PWM signal. L1 + Q2 The IR3622A uses a lossless current sensing for current share purposes. The inductor current is sensed by connecting a series resistor and a capacitor network in parallel with the inductor and by measuring the voltage across the capacitor. The measured voltage is proportional to the inductor current. This is shown figure 6. The voltage across the inductor’s DCR can be expressed by: R L1 V RL 1 ( s ) = (V in − V out ) * - - - -(1 ) R L1 + sL 1 V RL 1 ( s ) = I L1 * R L1 - - - -( 2 ) VL1 (s) C1 + VC1(s) VP2 VOUT FB2 Vin Q3 At no load condition the slave channel may be kept off depending on the offset of the error amplifier. Lossless Inductor Current Sensing R1 RL1 R2 L2 C2 RL2 Q4 Slave Phase Fig. 6: Loss Less inductor current sensing and current sharing the sense circuit can be treated as if only a sense resistor with the value RL1 was used. If : R 1 * C 1 = L1 R L1 VC ( s ) ≈ I L1 * R L1 The mismatch of the time constant does not affect the measurements of inductor DC current, but affects the AC component of the inductor current. The voltage across the C1 can expressed by: Soft-Start 1 VC 1 ( s ) = (V in − V out sC 1 )* R1 + 1 sC 1 - - - -( 3 ) Combining equations (1),(2) and (3) result in the following expression for VC1: VC 1 ( s ) = I L1 * R L1 + sL 1 1 + sR 1 * C 1 - - - -( 4 ) Usually the resistor R1 and C1 are chosen so that the time constant of R1 and C1 equals the time constant of the inductor which is the inductance L1 over the inductor’s DCR (RL1). If the two time constants match, the voltage across C1 is proportional to the current through L1, and www.irf.com The IR3622A has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. It provides a separate soft-start function for each output. This will enable to sequence the outputs by controlling the rise time of each output through selection of different value soft-start capacitors. To ensure correct start-up, the soft-start sequence initiates when the Vcc and Enable rise above their threshold and generate the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the error amplifier’s output of the PWM converter. 12 IR3622AMPbF 3V Soft-Start (cont.) During power up, the converter output starts at zero and thus the voltage at Fb is about 0V. An internal voltage-controlled current source (64uA) injects current into the Fb pin and generates a voltage about 1.6V (64ux25K) across the negative input of error amplifier, see figure 7. This keeps the output of the error amplifier low. The magnitude of this current is inversely proportional to the voltage at the soft-start pin. The 23uA current source starts to charge up the external capacitor. In the mean time, the softstart voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at the negative input of error amplifier. ISS1 = 23uA 64uA OCP1 SS1/SD1 Ihiccup1 = 3uA POR Seq E/A1 Fb1 VP1 When the soft-start voltage reaches about 1V, the voltage at the negative input of the error amplifier is approximately 0.8V. As the soft-start capacitor voltage charges up, the current flowing into the Fb pin keeps decreasing. The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 1.8V and the output voltage goes into steady state. Figure 8 shows the theoretical operational waveforms during soft-start. The output start-up time is the time period when soft-start capacitor voltage increases from 1V to 1.8V. The start-up time will be dependent on the size of the external soft-start capacitor. The startup time can be estimated by: 23µA ∗ Tstart = 1.8V − 1V Css 3V ISS2 = 23uA 64uA SS2/SD2 OCP2 Ihiccup2 = 3uA POR E/A2 Fb2 VP2 Track Fig. 7: Soft-Start circuit for IR3622A Output of POR 3V ≅1.8V For a given start up time, the soft-start capacitor (nF) can be estimated as: C SS ≅ 23 ( µ A ) * T start ( ms ) 0 . 8 (V ) - - - -( 5 ) For normal start up the Seq pin should be pulled high (usually can be connected to Vout3). Soft-Start Voltage Current flowing into Fb pin ≅1V 0V 64uA 0uA Voltage at negative input ≅1.6V of Error Amp 0.8V 0.8V Voltage at Fb pin 0V Fig. 8: Theoretical operation waveforms during soft-start www.irf.com 13 IR3622AMPbF Output Voltage Tracking and Sequencing The IR3622A can accommodate a full spectrum of user programmable tracking and sequencing options using Track, Seq, Enable and Power Good pins. Through these pins both simple voltage tracking such as that required by the DDR memory application or more sophisticated sequencing such as ratiometric or simultaneous can be implemented. The Seq pin controls the internal current sources to set the power up or down sequencing. Toggle this pin high for power up, and toggle this pin low for power down. The Track pin is used to determine the second channel output for either ratiometric or simultaneous by using two external resistors. Figure 9 shows how these pins are configured for different sequencing mode. In general the RA and RB set the output voltage for the first output and RC and RD set the output voltage for the second output. For simultaneous vs. ratiometric, RE and RF can be selected according to the table below: Track Pin Simultaneously Ratiometric RE=RC , RF=RD RE =RA , RF=RB 3V ISS1 = 23uA 64uA SS1/SD1 OCP1 CSS1 Ihiccup1 = 3uA POR Seq Vo1 RA Fb1 RB VP1 Fig. 10: Ratiometric Power Up / down E/A1 VREF 3V ISS2 = 23uA 64uA SS2/SD2 Floating OCP2 POR Vo2 RC RD Vo1 RE RF Fb2 Ihiccup2 = 3uA E/A2 Track VP2 VREF Fig. 9: Using Seq and Track pin for different sequencing www.irf.com Fig. 11: Simultaneously Power up /down 14 IR3622AMPbF Fault Protection The IR3622A monitors the output voltage for over voltage protection and power good indication. It senses the Rds(on) of low side MOSFET for over current protection. It also protects the output for prebias conditions. Figure 12 shows the IC’s operating waveforms under different fault conditions. POR 3V 1.8V 1.0V SS Set Voltage 90%Vfb Pre_Bias Voltage Vo PGood OCP Threshold Iout OV t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Fig. 12: Fault Conditions t0 – t1: Vcc, VcH1,VcH2 and Enable signals passed their respective UVLO threshold. Soft start sequence starts. t1 – t2: Power Good signal flags high. t1 – t3: Output voltage ramps up and reaches the set voltage. t4 – t5: OC event, SS ramps down. IC in Hiccup mode. t5– t6: OC is removed, recovery sequence, fresh SS. t6 –t7: Output voltage reaches the set voltage. t8: OVP event. HDrv turns off and LDrv turns on. The IC latches off. t9 –t10: Manually recycled the Vcc after latched OVP. PreBias start up. t10 –t11: New Soft Start sequence www.irf.com 15 IR3622AMPbF Over-Current Protection The over current protection is performed by sensing current through the Rds(on) of the low side MOSFET (Q2). This method enhances the converter’s efficiency and reduce cost by eliminating a current sense resistor. As shown in figure 13, an external resistor (RSET) is connected between the OCSet pin and the drain of Q2 which sets the current limit set point. The internal current source develops a voltage across RSET. When the Q2 is turned on, the inductor current flows through the Q2 and results in a voltage drop which is given by: VOCSet = (IOCSet ∗ ROCSet ) − (Rds(on) ∗ IL ) - - - -( 6 ) IOCSET Q1 IR3622 L1 OCSet RSET VOUT 28uA OCP 23uA SS1 / SD 20 3uA Fig. 14: 3uA current source for discharging soft-start capacitor during hiccup The OCP circuit starts sampling current when the low gate drive is about 3V. The OCSet pin is internally clamped to approximately 1.4V during deadtime to prevent false trigging. Figure 15 shows the OCSet pin during one switching cycle. There is about 150ns delay to mask out the deadtime, since this node contains switching noise, this delay also functions as a filter. Q2 Hiccup Control Fig. 13: Connection of over current sensing resistor The critical inductor current can be calculated by setting: Deadtime VOCSet = (IOCSet ∗ ROCSet ) − (Rds(on) ∗ IL ) = 0 ISET = IL(critical) R ∗I = OCSet OCSet Rds(on) Blanking time Iocset * Rocset Clamp Voltage - - - -(7 ) An over current is detected if the OCSet pin goes below ground. This trips the OCP comparator and cycles the soft start function in hiccup mode. The hiccup is performed by charging and discharging the soft-start capacitor at a certain slope rate. As shown in figure 14 the 3uA current source is used to discharge the soft-start capacitor. The OCP comparator resets after every soft start cycles, and the converter stays in this mode until the overload or short circuit is removed. The converter will automatically recover. www.irf.com Fig. 15: OCset pin during normal condition Ch1: Inductor point, Ch2:LDrv, Ch3:OCSet The value of RSET should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. The IR3622A current limit is designed primarily as short circuit protection, "no blow up" circuit, and doesn't operate as a precision current regulator. When the SS2 is floating, an over current condition on either phase would result in hiccup current protection. 16 IR3622AMPbF Pre-Bias Operating Frequency Selection The IR3622A is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Figure below shows a typical Pre-Bias condition at start up. Depending on system configuration, specific amount of output capacitance may be required to prevent discharging the output voltage. The switching frequency is determined by connecting an external resistor (Rt) to ground. Figure 16 provides a graph of oscillator frequency versus Rt. The maximum recommended channel frequency is 600kHz. Vo Pre-Bias Voltage (Output Voltage before startup) 600 500 Fsw (kHz) V 700 400 300 200 100 Time 0 5 Over Voltage Protection Over-voltage is sensed through two dedicated sense pins VSEN1, VSEN2. A separate OVP circuit is provided for each channel. The OVP threshold is user programmable and can be set by two external resistors. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on the fault output. In this mode, the upper FET driver turns off and the lower FET drivers turn on, thus crowbaring the output. Reset is performed by recycling the Vcc or Enable. Power Good The IR3622A provides two separate open collector power good signals which report the status of the outputs. The outputs are sensed through the two dedicated VSEN1 and VSEN2 pins. Once the IR3622A is enabled and the outputs reach the set value (90% of the Vout set point) the power good signals go open and stay open as long as the outputs stay within the set values. These pins need to be externally pulled high. Shutdown using Soft Start pins The outputs can be shutdown by pulling the softstart pins below 0.3V. This can be easily done by using an external small signal transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin. www.irf.com 10 15 20 25 30 35 40 45 50 55 60 65 Rt (Kohm) Fig. 16: Switching Frequency vs. External Resistor (Rt) Frequency Synchronization The IR3622A is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Per –channel switching frequency is set by external resistor (Rt). The free running frequency oscillator frequency is twice the perchannel frequency. During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. Synchronization capability is provided for both single output current share mode and dual output configuration. The sync pin is noise immune, when unused it should be left floating. Thermal Shutdown Temperature sensing is provided inside IR3622A. The trip threshold is typically set to 140oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range. There is a 20oC (typical) hysteresis in the shutdown threshold. 17 IR3622AMPbF Application Information Design Example: Soft-Start Programming The following is a design of typical single output current share application for IR3622A. The application circuit is shown on page 26. The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated using the following expression: Vin = 12V , ( ±10%) CSS (nF ) ≅ 28.75(µA) * Tstart (ms) Vo = 1.8V Io = 40 A - - - -(10 ) Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.15uF. Choose a ceramic capacitor at 0.15uF. ∆Vo ≤ 30 mV Fs = 375 kHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. As shown in figure 17 the Fb1 pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider is set to provide 0.8V at the Fb pin when the output is at its desired value. The output voltage is defined by the following equation: VOUT IR3622A The 180o out of phase will reduce the RMS value of the ripple current seen by input capacitors. This reduces numbers of input capacitors. The input capacitors must be able to handle both the maximum ripple RMS current at the highest ambient temperature, as well as the maximum input voltage. The RMS value of current ripple for a duty cycle under 50% is expressed by: IRMS = (I D (1 − D ) + I D (1 − D ) − 2I I D D ) 2 1 1 1 2 2 2 2 R5 Fig. 17: Typical application of the IR3622A for programming the output voltage ⎛ R ⎞ Vo = VREF ∗ ⎜⎜1 + 6 ⎟⎟ R5 ⎠ ⎝ - - - -( 8 ) Equation (8) can be rewritten as: ⎞ ⎟⎟ ⎠ - - - -( 9 ) For the calculated values of R5 and R6 see feedback compensation section. 1 2 - - - -(11) Where: -IRMS is the RMS value of the input capacitor current -D1 and D2 are duty cycle for each channel -I1 and I2 are the output current for each channel For Io=40A and D=0.16 (1.8V/10.8V), the IRMS= 9.43A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency, which enhance circuit efficiency. Use 10x22uF, 16V ceramic capacitor from TDK (C3225X5R1C226M). For the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total RMS current for the input capacitor current: IRMS = IO (2D(1 − D) + (2 − 2D)) www.irf.com 1 2 R6 Fb1 ⎛ V R5 = R6 ∗ ⎜⎜ ref ⎝ V o−Vref Input Capacitor Selection D > 0.5 18 IR3622AMPbF Inductor Selection Output Capacitor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value results in large ripple current, smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( ∆i ) . The optimum point is usually found between 20% and 50% ripple of the output current. The voltage ripple and transient requirements determine the output capacitors types and values. The criteria is normally based on the value of the Equivalent Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing factors. The overall output voltage ripple can be expressed as: For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Vin − Vo = L ∗ L = (Vin − Vo ) ∗ ∆i 1 ; ∆t = D ∗ Fs ∆t Vo Vin ∗ ∆i * Fs Vin = Maximum input voltage Vo = Output Voltage ∆i = Inductor ripple current F s= Switching frequency ∆t = Turn on time D = Duty cycle For 2-phase single output application the inductor ripple current is chosen between 20-50% of maximum phase current If ∆i ≈ 50%(Io ) , then the output inductor will be: L = 0.41uH The Coilcraft MLC1260-401ML (L1=0.4uH, 20A, RL1=0.93mOhm) is a low profile inductor suitable for this application. Use the following equation to calculate C1 and R1 for current sensing: (refer to figure 6 on page 12) L1 R L1 This results to C1=1uF and R1=0.432K www.irf.com where: ∆Vo(ESR) = ∆IL * ESR - - - -(13) ⎛Vin ⎞ ⎟ * ESL ⎝L⎠ ∆Vo(ESL) = ⎜ - - - -(12 ) Where: R1 * C1 = ∆Vo = ∆Vo(ESR) + ∆Vo(ESL) + ∆Vo(C ) ∆Vo(C ) = ∆IL 8 * Co * Fs ∆Vo = Output voltage ripple ∆IL = Inductor ripple current Therefore it is recommended to select output capacitor with low enough ESR to meet output ripple and step load transient requirements. The output ripple is highest at maximum input voltage since ∆i increases with input voltage. Special Polymer capacitors offers low ESR with large storage capacity per unit volume. These capacitors offer a cost effective output capacitor solution and are ideal choice when combined with a controller having high loop bandwidth. The IR3622A can perform well with all types of capacitors. Panasonic EEFSXOD221R (SP, 220F, 2V, 9mOhm) is selected for this design. Equation (13) can be used to calculate the required ESR for the specific voltage ripple. Four SP capacitors would meet the voltage ripple requirement. 19 IR3622AMPbF Power MOSFET Selection The IR3622A uses two N-Channel MOSFETs per channel. The selection criteria to meet power transfer requirements are based on maximum drain-source voltage (VDSS), gate-source drive voltage (Vgs), maximum output current, Onresistance RDS(on), and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (Vin). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low gate threshold voltage (Vgs) to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: Psw = Vds(off ) tr + tf * * Iload - - - (13A) 2 T Where: V ds(off) = Drain to source voltage at the off time tr = Rise time tf = Fall time T = Switching period Iload = Load current The switching time waveforms is shown in figure18. VDS 90% 2 Pcond = (upper switch)= Iload ∗ Rds(on) ∗ D ∗ ϑ 2 Pcond = (lower switch)= Iload ∗ Rds(on) ∗ (1 − D) ∗ϑ ϑ = Rds(on) temperature dependency The RDS(on) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. For this design, IRF6622 is selected for control FET and IRF6629 is selected for synchronous FET. These devices provide low on resistance in a compact Direct FET package. The MOSFETs have the following data: ControlFET(IRF6622): Vds = 25V,Qg = 18.7 nC @10Vgs Rds(on) = 6.3mΩ @Vgs = 10V SyncFET(IRF6629): Vds = 25V,Qg = 51nC @10Vgs Rds(on) = 2.1mΩ @Vgs = 10V The conduction losses will be: Pcon=1.1W/Phase The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the www.irf.com 10% VGS td(ON) tr td(OFF) tf Fig. 18: switching time waveforms From IRF6622 data sheet: tr = 13ns tf = 14ns These values are taken under a certain condition test. For more details please refer to the IRF6622 data sheet. By using equation (13A), we can calculate the switching losses. Psw=2.8W The reverse recovery loss is also another contributing factor in control FET switching losses. This is equivalent to extra current requires to remove the minority charges from synchronous FET. The reverse recovery loss can be expressed as: PQrr = Qrr * trr * Fs Qrr : ReverseRecoveryCharge trr : ReverseRecoveryTime Fs : SwitchingFrequency 20 IR3622AMPbF Feedback Compensation The IR3622A is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). FESR = VOUT 1 2 ∗ π Lo ∗ Co Gain R5 VREF -40dB/decade -180 CPOLE Gain(dB) H(s) dB Frequency Fig. 20: TypeII compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: - - - -(16) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: FLC Frequency [H(s)] = ⎛⎜⎜ g Fig. 19: Gain and Phase of LC filter The IR3622A’s error amplifier is a differentialinput transconductance amplifier. The output is available for DC gain control and AC phase compensation. The E/A can be compensated either in type II or type III compensation. When it is used in type II compensation the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in figure 20. This method requires that the output capacitor has enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: www.irf.com Ve R4 ⎛ R5 ⎞ 1 + sR4C9 ⎟* H(s) = ⎜⎜ gm * R5 + R6 ⎟⎠ sC9 ⎝ 0 0dB Comp C9 FZ Phase FLC Frequency E/A - - - -(14) Figure 19 shows gain and phase of the LC filter. Since we already have 180o phase shift just from the output filter, the system risks being unstable. - - - -(15) R6 Fb The output LC filter introduces a double pole, – 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 19). The resonant frequency of the LC filter expressed as follows: FLC = 1 2 ∗ π * ESR * Co ⎝ Fz = m * R5 ⎞ ⎟ * R4 R5 + R6 ⎟⎠ 1 2π * R4 * C9 - - - -(17) - - - -(18) The gain is determined by the voltage divider and E/A’s transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs Use the following equation to calculate R4: R4 = Vosc * Fo * FESR * (R5 + R6 ) Vin * FLC2 * R5 * gm - - - -(19) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter gm = Error Amplifier Transconductance 21 IR3622AMPbF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz = 75%FLC Fz = 0.75 * 1 2π Lo * Co VOUT ZIN C12 C10 - - - -(20) R8 R7 C11 R6 Zf Using equations (18) and (20) to calculate C9. C9 = Fb 1 2π * R4 * Fz R5 One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP = 1 C *C 2π * R4 * 9 POLE C9 + CPOLE CPOLE = 1 π * R4 * Fs − For FP << 1 C9 ≅ 1 π * R4 * Fs Fs 2 For a general solution for unconditional stability for any type of output capacitors in a wide range of ESR values, we should implement local feedback with a compensation network (typeIII). The typically used compensation network for voltage-mode controller is shown in figure 21. In such configuration, the transfer function is given by: Ve 1 − g m Zf = Vo 1 + g m ZIN - - - -(21) By replacing Zin and Zf according to figure 15, the transformer function can be expressed as: H (s ) = (1 + sR7C11 ) * [1 + sC10 (R6 + R8 )] 1 * sR6 (C11 + C12 ) ⎡ ⎛ C11 * C12 ⎞⎤ ⎟⎟⎥ * (1 + sR8C10 ) ⎢1 + sR7 ⎜⎜ ⎝ C11 + C12 ⎠⎦ ⎣ www.irf.com Ve H(s) dB FZ2 FP2 FP3 Frequency Fig. 21: Compensation network with local feedback and its asymptotic gain plot As known, transconductance amplifier has high impedance (current source) output, which needs to be considered when loading the E/A output. If the source/sink output current capability is exceeded the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP 2 = 1 2π * R8 * C10 1 1 ≅ ⎛ C11 * C12 ⎞ 2π * R7 * C12 ⎟⎟ 2π * R7 ⎜⎜ ⎝ C11 + C12 ⎠ 1 Fz1 = 2π * R7 * C11 FP 3 = The error amplifier gain is independent of the transconductance under the following condition: g m * Zf >> 1 and g m * Zin >> 1 Comp VREF Gain(dB) FZ1 The pole sets to one half of switching frequency which results in the capacitor CPOLE: E/A Fz 2 = 1 1 ≅ 2π * C10 * (R6 + R8 ) 2π * C10 * R6 Cross over frequency is expressed as: Fo = R7 * C10 * Vin 1 * Vosc 2π * Lo * Co 22 IR3622AMPbF Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. Compensator type FESR vs. Fo Output capacitor TypII(PI) FLC<FESR<Fo<Fs/2 Electrolytic , Tantalum TypeIII(PID) Method A FLC<Fo<FESR<Fs/2 Tantalum, ceramic TypeIII(PID) Method B FLC<Fo<Fs/2<FESR Ceramic Table1- The compensation type and location of FESR versus Fo The following design rules will give a crossover frequency approximately one-sixth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. 2 ; R7 ≥ 0.67KΩ ; Select : R7 = 6.04KΩ gm R7 ≥ Calculate C11 , C12 and C10 : FZ1 = 0.75 * FLC 1 ; C11 = 2.90nF, Select : C11 = 2.8nF 2π * FZ1 * R 7 C11 = FP3 = Fs The details of these compensation types are discussed in application note AN-1043 which can be downloaded from IR Web-Site. C12 = 1 ; C12 = 70pF, Select : C12 = 56pF 2π * FP 3 * R7 For this design we have: C10 = 2π * Fo * Lo * Co * Vosc ; C10 = 1.03nF, R7 * Vin Vin=13.2V Vo=1.8V Vosc=1.25V Vref=0.8V gm=3000umoh Lo=0.4uH, DCR=0.930mOhm Co=4x220uF, ESR= 2.25mOhm Fs=375kHz Select : C10 = 1.5nF Calculate R8 , R6 and R5 : R8 = 1 ; R8 = 1.32KΩ, Select : R8 = 1KΩ 2π * C10 * FP 2 R6 = 1 − R8 ; R6 = 7.84KΩ, Select : R6 = 7.87KΩ 2π * C10 * FZ 2 R5 = Vref * R6 ; R5 = 6.30KΩ , Select : R5 = 6.34KΩ Vo − Vref These result in: FLC=12kHz (Replace L to L/2 in formula#14 for current share configuration) FESR=80.38kHz Fs/2=185kHz Select crossover frequency: Fo < FESR and Fo ≤ (1/5 ~ 1/10) * Fs Fo=60kHz Since: FLC<Fo<FESR<Fs/2, typeIII method A is selected to place the pole and zeros. www.irf.com Check : R8 R6 R5 0.78kΩ > > 1 gm 1 = 0.33 KΩ gm 1 OK! gm If this condition is not met, then iteration may be required by selecting larger R7. 23 IR3622AMPbF Compensation for (slave channel) Current Loop The slave error amplifier is differential transconductance amplifier, in 2-phase configuration the main goal for the slave channel feedback loop is to control the inductor current to match the master channel inductor current as well provides highest bandwidth and adequate phase margin for overall stability. The following analysis is valid for both using external current sense resistors and using DCR of the inductor. The transfer function of power stage is expressed by: G(s) = IL2 (s) Vin = Ve sL2 * Vosc Select a zero frequency for current loop (Fo2) 1.2 times larger than zero cross frequency for voltage loop (Fo1). FO2 ≅ 1.25% * FO1 H(FO2 ) = gm * Rs1 * R2 * Where: Vin=Input voltage L2=Output inductor Vosc=Oscillator Peak Voltage As shown the G(s) is a function of inductor current. The transfer function for compensation network is given by equation (23), when using a series RC circuit as shown in figure22. IL2 1 2π * FO2 * L2 * Vosc * gm * Rs1 Vin Vin=13.2V Vosc=1.25V gm=3000umoh L2=0.4uH Rs1=DCR=0.930mOhm Fo2=72kHz This results to : R2=6.14K Select R2=6.09K Fb2 Vp2 - - - -( 25 ) The power stage of current loop has a dominant pole (Fp) at frequency expressed by: L2 RS2 - - - -( 24 ) From (24), R2 can be expressed as: R2 = - - - -( 22 ) Vin =1 2π * FO2 * L2 * Vosc E/A2 FP = Comp2 Ve Req = Rds(on1) * D + Rds(on2 ) * (1 − D) + RL R2 RS1 L1 Req 2π * L2 C2 IL1 Fig. 22: The Compensation network for current loop Where Rds(on1) is the on-resistance of control FET, Rds(on2) is the on-resistance of synchronous FET, RL is the DCR of output inductance and D is the duty cycle Req=3.7mOhm T (s) = Ve (s) ⎛ R ⎞ ⎛1 + sC2R2 ⎞ ⎟ = ⎜ gm * s1 ⎟⎟ * ⎜⎜ Rs2 ⎜⎝ Rs2 ⎠ ⎝ sC2 ⎟⎠ - - - -( 23 ) Set the zero of compensator at 10 times the dominant pole frequency FP, the compensator capacitor, C2 can be expressed as: The loop gain function is: Fz = 10 * FP H(s) = [G(s) * T (s) * Rs2 ] ⎛ R ⎞ ⎛1 + sR2C2 ⎞ ⎛ Vin ⎞ ⎟ ⎟*⎜ H(s) = Rs2 * ⎜⎜ gm * s1 ⎟⎟ * ⎜⎜ R sC2 ⎟⎠ ⎜⎝ sL2 * Vosc ⎟⎠ s2 ⎠ ⎝ ⎝ www.irf.com C2 = C2=1.8nF 1 2π * R2 * Fz All design should be tested for stability to verify the calculated values. 24 IR3622AMPbF Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (RSET) from drain of low side MOSFET to the OCSet pin. The resistor can be calculated by using equation (7). The Rds(on) has a positive temperature coefficient and it should be considered for the worse case operation. This resistor must be placed close to the IC, place a small ceramic capacitor from this pin to ground for noise rejection purposes. ISET = IL(critical) = ROCSet ∗ IOCSet Rds(on) - - - -(7 ) Rds ( on ) = 2.1mΩ ∗1.5 = 3.15 mΩ ISET ≅ Io ( LIM ) = 20 A ∗1.5 = 30 A (50% over nominal output current) ROCSet = R3 = R4 = 4KΩ www.irf.com Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor close to control FETs, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The exposed pad of IC should be connected to analog ground. 25 IR3622AMPbF Typical Application D1 C12 12V C11 C3 C4 R10 C5 VCL VcH1 VOUT3 VcH2 HDrv1 Vcc OCSet1 R2 C8 C9 R3 R4 U1 IR3622A Comp1 Comp2 SS1 / SD SS2 / SD Vout3 L3 Q3 R5 Vout C15 LDrv2 C16 R7 VSEN2 Fb1 Fb2 HDrv2 R7 R8 VSEN1 OCSet2 C10 Q2 C17 PGood1 PGood1 C14 PGnd1 VP2 Sync VREF VP1 Rt R1 LDrv1 Enable R11 C13 R6 Q4 R8 R9 C18 L4 Q5 PGnd2 Gnd Track Seq PGood2 Fig. 23: Application circuit for 12V to 1.8V @ 40A Note: To ensure correct start up Enable pin needs to be programmed (R10,R11) so the device turns on when the 12V rail is reached about 9-10V. www.irf.com 26 IR3622AMPbF Typical Application D1 BAT54S C12 L1 12V C11 C1 C2 C3 C4 R10 C5 VCL HDrv1 Vcc OCSet1 VREF VP2 R2 Rt C8 R3 C9 R4 Comp1 Comp2 PGood1 PGood2 PGood2 C15 Vout1 HDrv2 R6 VOUT3 D2 VSEN1 BAT54S VcH2 C30 R21 R7 R8 R5 C17 Q4 L4 R9 Vout2 C18 Q5 PGnd2 Gnd SS2 / SD C16 R20 LDrv2 SS1 / SD C10 Q3 VSEN1 VSEN1 VSEN2 VSEN2 Fb1 Fb2 OCSet2 L3 Vout1 PGnd1 Sync U1 IR3622A PGood1 Q2 R1 LDrv1 Enable VP1 R11 C14 C13 VcH1 VOUT3 VcH2 R22 VSEN2 R23 Seq RA Track RB Fig. 24: Application circuit for Dual output application Tracking and sequencing using Track pin Note: To ensure correct start up Enable pin needs to be programmed (R10,R11) so the device turns on when the 12V rail is reached about 9-10V. Track Pin Simultaneously Ratiometric www.irf.com RA=R9 , RB=R5 RA =R7 , RB=R8 27 IR3622AMPbF Typical Application for Fully Buffered DIMM P5V_STBY P12V D1 C11 C3 C4 VCL VcH1 VOUT3 VcH2 HDrv1 OCSet1 Track C5 R2 Seq LDrv1 Vcc PGnd1 VP2 Rt C8 R3 C9 R4 U1 IR3622A Comp1 Comp2 C13 R1 C14 Q2 L3 Q3 R5 C10 SS1 / SD SS2 / SD OCSet2 LDrv2 PGood1 PGood1 Enable PWERGD_P1V5_MCH VREF VP1 C16 R7 VSEN2 Fb1 Fb2 HDrv2 R7 R8 VSEN1 C17 R9 Vout C15 R6 Q4 R8 R9 C18 L4 Q5 PGnd2 Gnd PGood2 Sync Fig. 25: Application circuit for FBD P1V8 VREG(40A) P5V_P12V_STBY Note: see Figure26 for start up/down waveforms www.irf.com 28 IR3622AMPbF Typical start up /down waveforms for Fully Buffered DIMM P5V_STBY 3.9V P12V Enable SS Vo t0 t1 t2 t4 t3 t5 t6 Fig. 26 t0: 5V standby ramps up t1; 12V bus voltage ramps up t2: Enable pin pulls high by Power Good Signal of P1V5_MCH regulator t3: Soft start, Vo ramps up t4: Vo reaches the set voltage t4-t5: 12V rail shuts down, IC enters to standby mode (powered from 5V_STBY) t6: 5V standby shuts down, Vcc<3.9V, IC shuts down www.irf.com 29 IR3622AMPbF PCB Metal and Components Placement Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper). A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. www.irf.com 30 IR3622AMPbF Solder Resist The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. The single via in the land pad should be tented or plugged from bottom boardside with solder resist. www.irf.com 31 IR3622AMPbF Stencil Design The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. www.irf.com 32 IR3622AMPbF (IR3622AM) MLPQ Package; 5x5-32 Lead Feed Direction Figure A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 6/15/2007 www.irf.com 33