IRF IP2003PBF

NOT RECOMMENDED FOR NEW DESIGN
REPLACE WITH iP2003APBF
PD- 97071
iP2003PbF
Synchronous Buck
Multiphase Optimized LGA Power Block
Integrated Power Semiconductors, Drivers & Passives
Features:
•
•
•
•
•
•
•
•
•
Full function multiphase building block
Output current 40A continuous with no derating up to
TPCB = 100°C and TCASE = 100°C
Operating frequency up to 1.0 MHz
Efficient dual sided cooling
Small footprint low profile (11mm x 11mm x 2.2mm) package
iP2003PbF Power Block
Optimized for very low power losses
LGA interface
Ease of design
Proprietary packaging enables ultra low Rthj-case top
Description
The iP2003PbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin #
iP2003PbF Internal Block Diagram
1
VIN
PRDY
ENABLE
PWM
VDD
MOSFET
Driver with
dead time
control
VSW
SGND
PGND
PACKAGE
DESCRIPTION
INTERFACE
CONNECTION
PARTS PER
BAG
PARTS
PER
REEL
T&R
ORIENTATION
iP2003PbF
iP2003TRPbF
LGA
LGA
10
---
--1000
Fig 12
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2/15/06
Pin Name Pin Function
VDD
Supply voltage for the internal circuitry.
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current is less than 10µA.
2
ENABLE
3
PWM
TTL-level input signal to MOSFET drivers.
4
PRDY
Power Ready - This pin indicates the status of
ENABLE or VDD. This output will be driven
low when ENABLE is logic low or when VDD
is less than 4.4V (typ.). When ENABLE is
logic high and VDD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
5, 7
PGND
6
VSW
8
VIN
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Input voltage for the DC-DC converter.
1
iP2003PbF All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Symbol
Parameter
VIN
VIN to PGND
VDD
VDD to PGND
PWM to PGND
Enable to PGND
Output RMS Current
Block Temperature
PWM
ENABLE
IOUT
Min
-0.3
-0.3
-
Typ
-
TBLK
-40
-
Recommended Operating Conditions:
Parameter
Min
Symbol
Supply Voltage
Input Voltage
Output Voltage
Output Current
Operating Frequency
Operating Duty Cycle
VDD
VIN
VOUT
IOUT
fsw
D
4.6
3.0
0.8
300
-
Conditions
Max
Units
16
V
6.0
V
Not to exceed 6.0V
VDD +0.3
V
Not to exceed 6.0V
VDD +0.3
V
Measured at VSW
40
A
Capable of start up over full
125
°C
temperature range
Typ
Max
Units
5.0
-
5.5
13.2
3.3
40
1000
85
V
V
V
A
kHz
%
Electrical Specifications @ VDD = 5V (unless otherwise specified):
Symbol
Parameter
Min
Typ
Max
Units
PLOSS
9.4
11.7
W
Block Power Loss c
td(on)
Turn On Delay d
63
ns
td(off)
Turn Off Delay d
26
VIN Quiescent Current
IQ-VIN
1.0
mA
VDD Quiescent Current
IQ-VDD
10
µA
UVLO
Under-Voltage Lockout
V
Start Threshold
4.2
4.4
4.5
V
START
V
150
mV
Hysteresis
Hvs-UVLO
Enable
ENABLE
VIH
Input Voltage High
2.0
V
VIL
0.8
Input Voltage Low
Power Ready
PRDY
VOH
Logic Level High
4.5
4.6
V
V
Logic Level Low
0.1
0.2
OL
PWM Input
PWM
VOH
Logic Level High
2.0
V
VOL
0.8
Logic Level Low
Conditions
Conditions
VIN=12V, VOUT=1.3V
IOUT=40A, fSW=1MHz
L = 0.3µH
Enable = 0V, VIN=12V
Enable = 0V, VDD=5V
VDD=4.6V, ILoad=10mA
VDD <UVLO Threshold, ILoad = 1mA
 Measurement were made using four 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
‚ Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
2
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iP2003PbF
16
VIN = 12V
VOUT = 1.3V
14
f sw
12
L
Power Loss (W)
= 1MHz
T BLK = 125°C
= 0.30µH
10
Maximum
8
Typical
6
4
2
0
0
5
10
15
20
25
30
35
40
Output Current (A)
Fig. 1: Power Loss vs. Current
Case Temperature (°C)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
40
Safe
Operating
Area
36
Output Current (A)
32
28
Tx
24
20
16
VIN = 12V
VOUT = 1.3V
12
8
f sw
= 1MHz
L
= 0.30µH
4
0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
PCB Temperature (°C)
Fig. 2: Safe Operating Area (SOA) vs. TPCB & TCASE
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3
iP2003PbF
Typical Performance Curves
1.20
f sw
= 1MHz
5
1.16
L
= 0.3µH
T BLK = 125°C
4
6
1.12
3
1.08
2
1.04
1
1.00
0
-1
0.96
3
4
5
6
7
8
9
10
11
12
1.16
4.0
1.12
3.0
1.08
2.0
VIN = 12V
I OUT = 40A
1.04
f sw
1.00
-1.0
0.8
1.2
1.6
-1.0
-2.0
L = 0.30µH
T BLK = 125°C
-3.0
0.80
-4.0
0.75
-5.0
0.70
-6.0
0.65
-7.0
400
500
600
700
800
Power Loss (Normalized)
0.0
I OUT = 40A
300
2.8
3.2
3.6
VIN = 12V
VOUT = 1.3V
I OUT = 40A
1.04
f sw
1.0
= 1MHz
T BLK = 125°C
1.02
1.5
0.5
1.00
0.0
0.98
-0.5
0.1
900 1000
0.3
0.5
0.7
0.9
Output Inductance (µH)
Swiching Frequency (kHz)
Fig. 5: Normalized Power Loss vs. Frequency
Fig. 6: Normalized Power Loss vs. Inductance
80
Average IDD ( mA)
70
60
50
40
Does not include
PRDY current
T BLK = 25°C
30
20
250
500
750
1000
Switching Frequency (kHz)
4
Fig. 7: IDD (VDD current) vs. Frequency
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SOA Temp Adjustment (°C)
Power Loss (Normalized)
1.06
SOA Temp Adjustment (°C)
VIN = 12V
VOUT = 1.3V
200
2.4
Fig. 4: Normalized Power Loss vs. VOUT
1.0
0.85
2.0
Output Voltage (V)
1.05
0.90
0.0
0.96
13
Fig. 3: Normalized Power Loss vs. VIN
0.95
= 1MHz
L
= 0.30µH
T BLK = 125°C
Input Voltage (V)
1.00
1.0
SOA Temp Adjustment (°C)
1.24
Power Loss (Normalized)
7
VOUT = 1.3V
I OUT = 40A
SOA Temp Adjustment (°C)
Power Loss (Normalized)
1.28
iP2003PbF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum
current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn
out through the printed circuit board and the top of the case.
Case Temperature (ºC)
Procedure
0
30
40
50
60
70
80
90
100
110
120
36
34
32
Output Current (A)
3) Draw a horizontal line from the intersection of the vertical
line with the SOA curve to the Y-axis. The point at which
the horizontal line meets the Y-axis is the SOA current.
20
42
40
38
1) Draw a line from Case Temp axis at TCASE to the PCB
Temp axis at TPCB.
2) Draw a vertical line from the TX axis intercept to the SOA
curve.
10
30
28
26
24
22
20
TX
18
16
14
Safe
Operating
Area
VIN = 12V
VOUT = 1.3V
fSW = 1MHz
L=0.3uH
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
110
120
PCB Temperature (ºC)
Calculating Power Loss and SOA for Different Operating Conditions
To calculate power loss for a given set of operating conditions, the following procedure should be followed:
Determine the maximum current for each iP2003PbF and obtain the maximum power loss from Fig 1. Use the curves
in Figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. The
maximum power loss under the operating conditions is then the product of the power loss from Fig. 1 and the normalized values.
To calculate the SOA for a given set of operating conditions, the following procedure should be followed:
Determine the maximum PCB temperature and Case temperature at the maximum operating current of each
iP2003PbF. Obtain the SOA temperature adjustments that match the operating conditions in the application from Figs.
3, 4, 5 and 6. Then, add the sum of the SOA temperature adjustments to the Tx axis intercept in Fig 2.
The example below explains how to calculate maximum power loss and SOA.
Example:
Operating Conditions
Output Current = 40A
Sw Freq= 900kHz
Input Voltage = 10V
Inductor = 0.2µH
Output Voltage = 3.3V
TPCB = 100°C, TCASE = 110°C
Calculating Maximum Power Loss:
(Fig. 1)
(Fig. 3)
(Fig. 4)
(Fig. 5)
(Fig. 6)
Maximum power loss = 15W
Normalized power loss for input voltage ≈ 0.98
Normalized power loss for output voltage ≈ 1.14
Normalized power loss for frequency ≈ 0.94
Normalized power loss for inductor value ≈ 1.013
Calculated Maximum Power Loss for given conditions = 15W x 0.98 x 1.14 x 0.94 x 1.013 ≈ 15.96W
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iP2003PbF
Calculating SOA Temperature:
(Fig.
(Fig.
(Fig.
(Fig.
3)
4)
5)
6)
SOA Temperature Adjustment
SOA Temperature Adjustment
SOA Temperature Adjustment
SOA Temperature Adjustment
for
for
for
for
input voltage ≈ -0.5°C
output voltage ≈ 3.3°C
frequency ≈ -1.2°C
inductor value ≈ 0.25°C
TX axis intercept temp adjustment = - 0.5°C + 3.3°C - 1.2°C + 0.25°C ≈ 1.85°C
Assuming TCASE = 110°C & TPCB = 100°C:
The following example shows how the SOA current is adjusted for a TX increase of 1.85°C.
Case Temperature (°C)
Output Current (A)
0
10
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
20
30
40
50
60
70
80
90
100
110
120
TX
Safe
Operating
Area
VIN = 12V
VOUT = 1.3V
fSW = 1MHz
L=0.3uH
0
10
20
30
40
50
60
70
80
90
100
110
120
PCB Temperature (ºC)
PIN = VIN Average x IIN Average
PDD = VDD Average x IDD Average
POUT = VOUT Average x IOUT Average
PLOSS = (PIN + PDD) - POUT
Average
Input
Current
(IIN)
90%
A
DC
Average
VDD
Current
(IDD)
Average
VDD
Voltage
(VDD)
A
V
PRDY
VIN
ENABLE
PWM
VDD
V
PWM
10%
Average Output
Current (IOUT)
VSW
90%
A
PGND
DC
iP2003
iP2003PbF
VSW
Averaging
Circuit
V
Fig. 8: Power Loss Test Circuit
6
Average
Input
Voltage
(VIN )
Average
Output
Voltage
(VOUT)
10%
td(on)
td(off)
Fig. 9: Timing Diagram
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iP2003PbF
PCB Layout Guidelines
The PCB layout and bypassing issues have been addressed with the internal design of the iP2003PbF.
One of the most critical elements of proper PCB layout with iP2003PbF is the placement of the external
input bypass capacitors and the routing of the connecting power tracks. The iPOWIR Block will function
normally without any additional external input bypass capacitors. However, the addition of the external
capacitors will improve the long term reliable operation of the block.
It is recommended that the designer uses the following guidelines:
1.
2.
3.
4.
The diagram below suggests the addition of the input bypass capacitors either on the top side of
the PCB (capacitors C1-C4) or top and bottom side (C5, C6), if placement on the bottom side is
feasible. Although there is a certain degree of bypassing inside the iP2003PbF, these external
capacitors must be placed as close to the iPOWIR device as possible.
In the diagram below, observe the routing of the power tracks that connect the external bypass
capacitors.
Provide a mid-layer solid ground plane with connections to the top through vias.
Refer to IR application note AN-1029 to determine the size of the vias and the copper weight and
thickness when designing the PCB.
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7
iP2003PbF
4.8 [0.19]
2.0 [0.08]
iP2003PbF
iP2003
0408
Fig 10: Maximum TCASE measurement location
0.15 [.006] C
2X
11.00
[.433]
6
NOT ES :
A
B
ORIENT AT ION
CORNER ID
11.00
[.433]
1.
2.
3.
4.
5
DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994.
DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ].
CONT ROLLING DIMENS ION: MILLIMET ER
LAND DES IGNAT ION PER JES D MO 222, S PP-010.
PRIMARY DAT UM C IS S EAT ING PLANE.
6
BILAT ERAL T OLERANCE ZONE IS APPLIED T O EACH S IDE OF T HE
PACKAGE BODY.
LAYOUT NOT ES :
1. LAND PAT T ERN ON US ER’S PCB S HOULD BE AN IDENT ICAL MIRROR
IMAGE OF T HE PAT T ERN S HOWN IN T HE BOT T OM VIEW.
2. LANDS S HOULD BE S OLDER MAS K DEFINED.
0.15 [.006] C
T OP VIEW
2X
6
2.31 [.0909]
2.13 [.0839]
S IDE VIEW
C
L1
F1
5
L2
PRDY
X
1.1430
e
Y
2.1016
e1
(2),(3)
X
1.1430
e2
Y
1.1016
X
1.1430
D1
D2
Y
1.2827
E1
7.1167 BSC
X
Y
1.778
5.334
E2
F1
7.289 BSC
1.4732 BSC
X
5.715
Y
F2
L1
1.348 BSC
0.3556
X
2.921
5.588
Y
3.048
L2
L3
0.345
0.332
X
5.588
2.032
(4)
VSW
PWM
(1)
PGND
(5)
E1
ENABLE
D2
PGND
E2
L3
VDD
(6)
(7)
VIN
(8)
D1
Y
2.4384
3.8610
2.0193
3.023 BS C
5.945 BSC
F2
BOT T OM VIEW
Fig 11: Mechanical Drawing
8
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iP2003PbF
Refer to the following application notes for detailed guidelines and suggestions when
implementing iPOWIR Technology products:
AN-1030: Applying iPOWIR Products in Your Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
AN-1047: Graphical solution for two branch heatsinking Safe Operating Area
Detailed explanation of the dual axis SOA graph and how it is derived.
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
BGA and LGA Packages
This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on
printed circuit boards, accounting for thermal and electrical performance and assembly considerations .
Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as
soldering, pick and place, reflow, cleaning and reworking recommendations.
IRDCiP2003 : Reference design for iP2003PbF
0508
6B7D
iP2003A
iP2003PbF
0508
6B7D
iP2003A
iP2003PbF
12mm
24mm
FEED DIRECTION
NOTES :
1. OUT LINE CONFORMS T O EIA-481 & EIA-541.
iP2003PbF,
LGA
iP2003A, LGA
Fig. 12: Tape & Reel Information
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/06
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9