PD - 97110 iP2001PbF Synchronous Buck Multiphase Optimized BGA Power Block Integrated Power Semiconductors, Drivers & Passives Features: 20A continuous output current with no derating up to TPCB = 90°C Very small 11mm x 11mm x 3mm profile Internal features minimize layout sensitivity * Optimized for very low power losses 3.3 to 12V input voltage iP2001PbF Power Block Description The iP2001PbF is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 3mm BGA power block. The only additional components required for a complete multiphase converter are a PWM IC, the external inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP2001PbF Internal Block VIN PRDY ENABLE MOSFET Driver with dead t ime control PWM VDD VSW SGND PACKAGE DESCRIPTION PGND INTERFACE CONNECTION PARTS PER BAG PARTS PER REEL iP2001PbF BGA 10 --- iP2001TRPbF BGA --- 1000 T&R ORIENTATION Fig 12 * All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that the adequate amount of input decoupling is provided on the VIN pin. No additional bypassing is required on the VDD pin. www.irf.com 8/11/06 1 iP2001PbF All specifications @ 25°C (unless otherwise specified) Absolute Maximum Ratings : Parameter VIN to PGND Min - Typ - Max 16 Units V Conditions VDD to SGND PWM to SGND -0.3 - 6.0 VDD+0.3 V V Enable to SGND Output RMS Current -0.3 - - VDD+0.3 20 V A Storage Temperature -40 - 125 °C Symbol Min Typ Max Units VDD 4.6 5.0 5.5 V Input Voltage Range VIN 3.0 - 12.6 V Output Voltage Range VOUT 0.9 - 3.3 V see Figs. 2 & 4 see Fig. 2 not to exceed 6.0V not to exceed 6.0V Recommended Operating Conditions : Parameter Supply Voltage Output Current Range IOUT - - 20 A Operating Frequency fsw 150 - 1000 kHz Operating Duty Cycle D - - 85 % Conditions see Figs. 2 & 5 Electrical Specifications @ VDD = 5V (unless otherwise specified) : Parameter Block Power Loss Turn On Delay Turn Off Delay VIN Quiescent Current VDD Quiescent Current Under Voltage Lockout Start Threshold Hysteresis Enable Input Voltage High Input Voltage Low Power Ready Logic Level High Logic Level Low PWM nput Logic Level High Logic Level Low Symbol P BLK td(on) td(off) IQ-VIN IQ-VDD UVLO VSTART VHys-UVLO Enable VIH VIL PRDY VOH VOL PWM VOH VOL Min - Typ 3.1 63 26 - Max 3.8 1.0 10 Units W 4.2 - 4.4 .05 4.5 - V 2.0 - - 0.8 V 4.5 - 4.6 0.1 0.2 V 2.0 - - 0.8 V ns mA µA Conditions VIN = 12V, VOUT = 1.6V, IOUT = 20A, fSW = 500kHz Enable = 0V, VIN = 12V Enable = 0V, VDD = 5V VDD = 4.6V, ILoad = 10mA VDD < UVLO Threshold, ILoad = 1mA Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see Fig. 8). Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9). 2 www.irf.com iP2001PbF Pin Description Table Pin Name VDD SGND Ball Designator A1 – A3, B1 – B3 A5 – A12, B5 – B12, C5 - C10 C11, C12, D11, D12, E11, E12, F6, F7, F12, G6, G7, G12, H6, H7, H12, J6, J7, J12, K5 – K7, K12, L5, L6, L12, M5 – M7, M12 D5 – D10, E5 – E10, F8 – F11, G8 – G11, H8 – H11, J8 – J11, K8 – K11, L8 – L11, M8 – M11 C1 – C3, D1 –D3, E1 –E3 ENABLE F1 VIN PGND VSW PRDY PWM NC www.irf.com K1 Pin Function Supply voltage for the internal circuitry. Input voltage for the DC-DC converter. Power Ground - connection to the ground of bulk and filter capacitors. Switching Node - connection to the output inductor. Signal Ground. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current is less than 10µA. Power Ready - This pin indicates the status of ENABLE or VDD. This output will be driven low when ENABLE is logic low or when VDD is less than 4.4V (typ.). When ENABLE is logic high and VDD is greater than 4.4V (typ.), this output is driven high. This output has a 10mA source and 1mA sink capability. TTL-level input signal to MOSFET drivers. H1 B4, C4, D4, E4, F2 – F4, G2 – This pin is not for electrical connection. It G4, H2 – H4, J1, J2 – J4, K3, should be attached only to dead copper. L1, L2, M1 – M4 3 iP2001PbF 22 5.0 20 4.5 VIN = 12V VOUT = 1.6V TBLK = 125°C fSW = 500kHz Power Loss (W) 3.5 18 16 Output Current (A) 4.0 3.0 Maximum Typical 2.5 2.0 1.5 Safe Operating Area 14 12 10 8 VIN = 12V VOUT = 1.6V fSW = 500kHz 6 1.0 4 0.5 2 0 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 10 20 30 Output Current (A) 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) Fig 2. Safe Operating Area (SOA) vs. TPCB* (*see AN-1030 for details) Fig 1. Power Loss vs. Current Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required operating current. Then, add the correction temperature from the normalized curves in Figs. 3, 4, 5 or 6 to find the final maximum allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on all factors. Operating Conditions for the examples below: Output Current = 20A Output Voltage = 2.5V Input Voltage = 7V Sw Freq= 750kHz Adjusting for Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) (Fig. 5) Maximum power loss = 5W Normalized power loss for input voltage ≈ 0.925 Normalized power loss for output voltage ≈ 1.1 Normalized power loss for frequency ≈ 1.225 Adjusted Power Loss = 5W x 1.1 x 0.925 x 1.225 ≈ 6.23W Adjusting for SOA Temperature: (Fig. 2) (Fig. 3) (Fig. 4) (Fig. 5) SOA PCB Temperature = 90°C Normalized SOA PCB Temperature for input voltage ≈ 2.6°C Normalized SOA PCB Temperature for output voltage ≈ -3.5°C Normalized SOA PCB Temperature for frequency ≈ -7.5°C Adjusted SOA PCB Temperature = 90°C - 3.5°C + 2.6°C - 7.5° ≈ 81.6°C 4 www.irf.com iP2001PbF Typical Performance Curves 1.02 -0.7 0.4 0.98 0.7 0.97 1.1 0.96 1.4 0.95 1.8 0.94 2.1 0.93 2.5 0.92 2.8 3 5 7 9 11 1.12 -2.8 1.04 -1.4 1.00 0.0 0.96 1.4 1.7 2.1 2.5 2.9 3.3 1.2 -7.0 1.1 -3.5 1.0 0.0 0.9 3.5 0.8 7.0 500 1.4 1.3 -14 -10 1.2 -7 1.1 -4 1.0 0 3 0.9 10.5 1000 750 VIN = 12V VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125°C SOA Temperature Adjustment (°C) -10.5 Power Loss (Normalized) -14.0 -17 1.5 SOA Board Temperature Adjustment (ºC) Power Loss (Normalized) 1.3 Fig 4. Normalized Power Loss vs. VOUT -17.5 VIN = 12V VOUT = 1.6V IOUT = 20A TBLK = 125°C 250 2.8 0.9 Output Voltage (V) 1.5 0.7 100 -4.2 0.92 13 Fig 3. Normalized Power Loss vs. VIN 1.3 -5.6 1.08 Input Voltage (V) 1.4 -7.0 VIN = 12V IOUT = 20A fSW = 500kHz TBLK = 125°C 1.16 Power Loss (Normalized) Power Loss (Normalized) 0.99 0.0 1.20 SOA PCB Temperature Adjustment (ºC) 1.00 -0.4 SOA PCB Temperature Adjustment (ºC) VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125°C 1.01 0 5 Switchin Frequency (kHz) 10 15 20 25 Peak to Peak Inductor Ripple Current (A) Fig 5. Normalized Power Loss vs. Frequency Fig 6. Normalized Power Loss vs. Ripple Current 80 Average Current (mA) 70 60 50 40 30 Does not include PRDY current 20 10 0 0 200 400 600 Switching Frequency (kHz) 800 1000 Fig 7. IDD vs. Frequency www.irf.com 5 8 5 9 4 10 3 11 2 12 1 PGND +5V TP20 TP19 TP5 VOUT SENSE * 9 8 5 4 3 2 1 19 10 1K Cx GND VCC PWM4 ISEN4 PWM3 ISEN3 PWM2 ISEN2 PWM1 C1 18 17 11 12 14 13 15 16 20 0.022uF 22pF ISEN1 1k R1 HIP6311 FS/DIS VID0 VID1 VID2 VID3 VID4 PGOOD VSEN U1 4700pF C28 Note: Rx and Cx are add on components 10uF C27 R4 51K VID0 VID1 VID2 VID3 VID4 PGOOD +5V Freq. Set Resistor 7 6 +5V R6 10K R2 51 Rx R3 open 7 ENABLE *Rx &Cx are not parts of PCB 6 FB 6 COMP S1 0 R13 0 R12 0 R18 10K R11 0 R10 C2 10uF 0 R14 +5V R17 10K R16 10K R15 10K ENABLE +5V ENABLE +5V ENABLE +5V ENABLE +5V PGND PRDY U2 4-Phase Reference Design Schematic VSW4 PGND PRDY VIN ENABLE PWM4 SGND VDD U5 PGND VSW3 VIN iP2001PbF IP2001 PRDY ENABLE PWM3 SGND VDD U4 PGND VSW2 VIN IP2001 iP2001PbF PRDY ENABLE PWM2 SGND VDD IP2001 iP2001PbF U3 VSW1 ENABLE PWM1 SGND VIN iP2001PbF IP2001 VDD SWNODE4 C12 10uF SWNODE3 C9 10uF SWNODE2 C6 10uF SWNODE1 C3 10uF C13 10uF C10 10uF C7 10uF C4 10uF C14 10uF 10uF C11 C8 10uF C5 10uF Vin Vin Vin Vin C32 10uF C31 10uF C30 10uF C29 10uF TP18 Vin 0.54uH L4 R9 2K 1% TP9 SWNODE4 0.54uH L3 TP8 SWNODE3 R8 2K 1% 0.54uH L2 TP7 SWNODE2 R7 2K 1% 0.54uH L1 R5 2K 1% TP6 SWNODE1 C24 Open C21 Open Open C18 C15 Open C25 Open Open C22 Open C19 C16 Open C26 100uF C23 100uF 100uF C20 C17 100uF VOUT TP14 PGND TP15 PGND TP16 PGND TP17 PGND C33 VOUT SENSE 0.01uF X7R PGNDSENSE TP22 PGND SENSE VOUT SENSENE TP21 TP10 VOUT TP11 VOUT TP12 VOUT TP13 VOUT iP2001PbF www.irf.com iP2001PbF Designator C1 C2 - C14, C27, C29 - C32 C15, C16, C18, C19, C21, C22, C24, C25, D1 - D4, R3, R19 C17, C20, C23, C26 C28 C33 Cx L1 - L4 R1, R2 R10 - R14 R6, R15 - R18 R4 R5, R7, R8, R9 Rx S1 ST1 - ST4 U1 U2 - U5 Value 1 0.022uF 10.0uF Value 2 50V 16V Type X7R X5R Tolerance 10% 10% - - - - 100uF 22.0pF 0.010uF 4700pF 0.54uH 1K 0 10K 51K 2K 51 SPST 4-40 - 6.3V 50V 50V 50V 27A 1/8W 1/8W 1/8W 1/8W 1/8W 1/10W 6 position - X5R COG X7R X7R Ferrite Thick film Thick film Thick film Thick film Thick film Thick film Switch PWM controller DC-DC 10% 5% 10% 10% 20% 5% <50m 5% 5% 5% 5% 0 - 70°C - Package 0805 1210 Mfr. TDK TDK - - 2220 TDK 0805 TDK 0805 TDK 0603 TDK SMT Panasonic 0805 ROHM 0805 ROHM 0805 ROHM 0805 ROHM 0805 ROHM 0603 KOA SMT C&K Components Keystone SOIC20 Intersil 11 x 11 x 3mm IR Mfr. Part No. C2012X7R1H223K C3225X5R1C106K C5750X5R0J107K C2012COG1H220J C2012X7R1H103K C1608X7R1H472K ETQP6F0R6BFA MCR10EZHJ102 MCR10EZHJ000 MCR10EZHJ103 MCR10EZHJ513 MCR10EZHJ202 RM73B1J510J SD06H0SK 8412 HIP6311CB IP2001 iP2001PbF 4-Phase Reference Design Bill of Materials 90% PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT PRDY Average VDD Current Average VDD Voltage A V ENABLE PWM A DC V Average Input Voltage PWM 10% Average Output Current VSW 90% A VDD SGND DC VIN Average Input Current PGND iP2001PbF iP2001 Averaging Circuit V Average Output Voltage VSW 10% td(on) Fig 8. Power Loss Test Circuit www.irf.com td(off) Fig 9. Timing Diagram 7 iP2001PbF VDD NC VIN NC SGND PGND NC NC ENABLE NC NC PWM NC NC NC NC NC PRDY NC NC VSW PGND NC Dimensions shown in inches (millimeters) 8 Recommended PCB Footprint (Top View) www.irf.com iP2001PbF 0.15 [.006] C 2X 11.00 [.433] 6 B A 5 C 0.45 [.0177] 0.35 [.0138] 0.12 [.005] C BALL A1 CORNER ID NOT ES : 1. 2. 3. 4. 5 11.00 [.433] 6 7 0.15 [.006] C TOP VIEW 2X 133X Ø 0.40 [.016] 4X 0.80 [.032] BOTT OM VIEW DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMETERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMETER S OLDER BALL POS IT ION DES IGNAT ION PER JES D 95-1, S PP-010. PRIMARY DAT UM C (S EATING PLANE) IS DEFINED BY THE S PHERICAL CROWNS OF T HE S OLDER BALLS . BILAT ERAL TOLERANCE ZONE IS APPLIED TO EACH S IDE OF THE PACKAGE BODY. S OLDER BALL DIAMET ER IS MEAS URED AT THE MAXIMUM S OLDER BALL DIAMET ER, IN A PLANE PARALLEL T O DATUM C. 22X 6 0.55 [.0216] 0.45 [.0178] 7 0.15 [.006] C A B 0.08 [.003] C 2.66 [.1047] 2.46 [.0969] (4X 1.1 [.043]) 3.11 [.1224] 2.81 [.1107] S IDE VIEW Fig. 10: Mechanical Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iP0WIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers BGA and LGA Packages This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations . Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as soldering, pick and place, reflow, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. www.irf.com 9 iP2001PbF 0123 XXXX iP2001 iP2001PbF XX Fig.11: Part Marking xx 0123 XXXX iP2001 0123 XXXX iP2001 24mm iP2001PbF iP2001PbF 16mm FEED DIRECT ION NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. iP2001PbF, BGA Fig.12: Tape & Reel Information Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IRs Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.08/06 10 www.irf.com