Data Sheet No. PD60213 ADVANCE DATA IR2214SS/IR22141SS HALF-BRIDGE GATE DRIVER IC Features • • • • • • • • Product Summary Floating channel up to +1200V Soft overcurrent shutdown Synchronization signal to synchronize shut down with the other phases Integrated desaturation detection circuit Two stage turn on output for di/dt control Separate pull-up/pull-down output drive pins Matched delay outputs Under voltage lockout with hysteresis band VOFFSET 1200V max. IO+/- (typ.) 2.0 A / 3.0A VOUT 10.4V - 20V Deadtime matching (max) 75nsec Deadtime (typ) 330nsec Desat blanking time (typ) 3µsec DSH,DSL input voltage threshold (typ) 8.0V Soft shutdown time (typ) 9.6µsec Description LIN HIN Typical Connection DC BUS (1200V) uP, Control FAULT/SD FLT_CLR SY_FLT (Refer to Lead Assignments for correct pin configuration). This/ These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com VSS IR2214SS/IR22141SS IR2214 The IR2214SS/IR22141SS) is a gate driver suited to drive a single half bridge in power switching applications. The high gate driving capability (2A source, 3A sink) and the low quiescent current enable bootstrap supply techniques in medium power systems. The IR2214SS/IR22141SS driver features full short circuit protection by means of the power transistor desaturation detection. The IR2214SS/IR22141SS manages all the half-bridge faults by turning off smoothly the desaturated transistor through the dedicated soft shut down pin, therefore preventing over-voltages and reducing EM emissions. In multi-phase system IR2214SS/IR22141SS drivers communicate using a dedicated local network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase short circuits. The system controller may force shutdown or read device fault state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the control and power ground use dedicated pins enabling low-side emitter current sensing as well. Under voltage conditions in floating and low VCC VB 15 V voltage circuits are managed HOP independently. HON Package 24-Lead SSOP DC+ SSDH DSH Motor VS LOP LON SSDL DSL COM DC- 1 IR2214/IR22141(SS) ADVANCE DATA Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VS High side offset voltage VB High side floating supply voltage Min. Max. VB - 25 VB + 0.3 Units -0.3 1225 VS - 0.3 VB + 0.3 -0.3 25 VCC - 25 VCC + 0.3 VCOM -0.3 VCC + 0.3 VHO High side floating output voltage (HOP, HON and SSDH) V CC Low side and logic fixed supply voltage COM Power ground VLO Low side output voltage (LOP, LON and SSDL) VIN Logic input voltage (HIN, LIN and FLT_CLR) -0.3 VCC + 0.3 V VFLT FAULT input/output voltage (FAULT/SD and SY_FLT) -0.3 VCC + 0.3 VDSH High side DS input voltage VB -25 VB + 0.3 VDSL Low side DS input voltage VCC - 25 VCC + 0.3 dVs/dt Allowable offset voltage slew rate — 50 V/ns Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient — 1.5 W — 65 °C/W TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 PD RthJA °C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absoute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential. Symbol Definition VB High side floating supply voltage (Note 1) VS High side floating supply offset voltage Min. Max. Units VS + 11.5 VS + 20 Note 2 1200 VHO High side output voltage (HOP, HON and SSDH) VS VS + 20 VLO Low side output voltage (LOP, LON and SSDL) VCOM VCC VCC Low side and logic fixed supply voltage (Note 1) 11.5 20 COM Power ground -5 5 VIN Logic input voltage (HIN, LIN and FLT_CLR) 0 VCC 0 VCC VFLT Fault input/output voltage (FAULT/SD and SY_FLT) VDSH High side DS pin input voltage VB - 20 VB VDSL Low side DS pin input voltage VCC - 20 VCC -40 125 TA Ambient temperature V °C Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached. Note 2: Logic operational for VS from VSS-5 to VSS+1200V. Logic state held for VS from VSS-5V to VSS-VBS. (Please refer to the Design Tip DT97-3 for more details). 2 www.irf.com IR2214/IR22141(SS) ADVANCE DATA Static Electrical Characteristics VCC = 15 V, VSS = COM = 0 V, VS = 0 ÷ 1200 V and TA = 25 oC unless otherwise specified. Pin: V CC , V SS , V B , VS Symbol V CCUV+ V CCUVVCCUVH VBSUV+ VBSUVV BSUVH ILK IQBS IQCC Definition Min Typ Max Units Test Conditions Vcc supply undervoltage positive going threshold Vcc supply undervoltage negative going threshold Vcc supply undervoltage lockout hysteresis (VB -VS ) supply undervoltage positive going threshold (VB -VS ) supply undervoltage negative going threshold (VB -VS ) supply undervoltage lockout hysteresis Offset supply leakage current Quiescent V BS supply current Quiescent Vcc supply current 9.3 8.7 9.3 8.7 - 10.2 9.3 0.9 10.2 9.3 0.9 400 0.7 11.4 10.3 11.4 10.3 50 800 2.5 V V S =0V, V S=1200V V S =0V, V S=1200V µA mA V B = VS = 1200V V IN = 0V or 3.3V (No load) comparator VCC/VB UV internal signal VCCUV/VBSUV VSS/VS Figure 1: Undervoltage diagram Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT Symbol VIH VIL Definition Logic "1" input voltage Logic "0" input voltage VIHSS Logic input hysteresis Logic "1" input bias current Logic "0" input bias current RON,FLT FAULT/SD open drain resistance RON,SY SY_FLT open drain resistance IIN+ IIN- Min Typ Max Units Test Conditions 2.0 - - 0.8 0.2 -1 - 0.4 370 60 60 0 - V µA µA Ω VCC = VCCUV- to 20V VIN = 3.3V VIN = 0V PW ≤ ? 7 µs schmitt trigger internal signal HIN/LIN/ FLTCLR 10k VSS Figure 2: HIN, LIN and FLTCLR diagram www.irf.com 3 IR2214/IR22141(SS) ADVANCE DATA FAULT/SD SY_FLT fault/hold internal signal schmitt trigger R ON hard/soft shutdown internal signal VSS Figure 3: FAULT/SD and SY_FLT diagram Pin: DSL, DSH The active bias is present only in IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS respectively for DSL and DSH. Symbol Definition Min Typ Max Units Test Conditions VDESAT+ VDESATVDSTH IDS+ IDSIDSB High desat input threshold voltage Low desat input threshold voltage Desat input voltage hysteresis High DSH or DSL input bias current Low DSH or DSL input bias current DSH or DSL input bias current (IR22141 only) 7.2 6.3 - 8.0 8.8 7.0 7.7 1.0 21 -160 -20 - V µA mA See Fig. 16, 4 VDESAT = VCC or VBS VDESAT = 0V VDESAT = (VCC or VBS) - 2V VCC/VBS 100k active bias comparator DSL/DSH VDESAT SSD internal signal 700k COM/VS Figure 4: DSH and DSL diagram 4 www.irf.com IR2214/IR22141(SS) ADVANCE DATA Pin: HOP, LOP Symbol Definition Min Typ Max Units Test Conditions VOH IO1+ High level output voltage, VB – VHOP or Vcc –VLOP Output high first stage short circuit pulsed current - 20 2 100 - IO2+ Output high second stage short circuit pulsed current - 1 - 200ns oneshot mV A IO = 1mA VHOP/LOP=0V, HIN or LIN= 1, ≤ PW?200ns, resistive load, see Fig. 8 VHOP/LOP=0V, HIN or LIN = 1, ≤ ≤ 400ns?PW?10µs, resistive load, see Fig. 8 VCC/VB VOH on/off internal signal LOP/HOP Figure 5: HOP and LOP diagram Pin: HON, LON, SSDH, SSDL Symbol VOL RON,SSD IO- Definition Min Typ Max Units Test Conditions Low level output voltage, VHON or VLON Soft Shutdown on resistance (Note 1) Output low short circuit pulsed current - 2.3 90 3 15 - mV Ω A IO = 1mA PW ≤? 7 µs VHOP/LOP=15V, HIN or LIN = 0, ≤ PW?10µs Note 1: SSD operation only. LON/HON SSDL/SSDH on/off internal signal VOL desat internal signal RON,SSD COM/VS Figure 6: HON, LON, SSDH and SSDL diagram www.irf.com 5 IR2214/IR22141(SS) ADVANCE DATA AC Electrical Characteristics VCC = VBS = 15V, VS = VSS and TA = 25°C unless otherwise specified. Symbol Definition Min. Typ. Max. Units ton toff Turn on propagation delay Turn off propagation delay 220 440 220 440 tr tf ton1 Turn on rise time (CLOAD=1nF) Turn off fall time (CLOAD=1nF) Turn on first stage duration time DSH to HO soft shutdown propagation delay at HO turn on DSH to HO soft shutdown propagation delay after Blanking DSL to LO soft shutdown propagation delay at LO turn on DSL to LO soft shutdown propagation delay after Blanking Soft shutdown minimum pulse width of desat Soft shutdown duration period — 24 — — 7 — 120 200 280 2000 3300 4600 tDESAT1 tDESAT2 tDESAT3 tDESAT4 tDS tSS 1050 — 660 660 VIN = 0 & 1 VS = 0 to 1200V HOP shorted to HON, LOP shorted to LON, Figure 7, 10 Figure 8 VHIN= 1 VDESAT = 15V,Fig.10 — 2000 3300 4600 1050 — VLIN = 1 VDESAT = 15V,Fig.10 — 1000 — — 5700 9600 13500 ns tSY_FLT, DSH to SY_FLT propagation delay at HO turn on — 3600 DSH to SY_FLT propagation delay after blanking 1300 — Figure 9 CL=TBD µF, VDS=15V, Fig 9 VDS=15V,Fig. 9 — DESAT1 tSY_FLT, Test Conditions — VHIN = 1 VDS = 15V, Fig. 10 DESAT2 tSY_FLT, DSL to SY_FLT propagation delay at LO turn on — 3050 — DESAT3 tSY_FLT, DSL to SY_FLT propagation delay after blanking 1050 — — VLIN = 1 VDESAT=15V,Fig.10 DESAT4 tBL DS blanking time at turn on — 3000 — VHIN = VLIN = 1 VDESATT=15V,Fig.10 Figure 11 External DT=0nsec Figure 11 External DT> 500nsec, Fig.7 Dead-time/Delay Matching Characteristics 6 DT MDT Dead-time Dead-time matching, MDT=DTH-DTL — — 330 — — 75 PDM Propagation delay matching, Max(ton, toff) - Min(ton, toff) — — 75 www.irf.com ADVANCE DATA IR2214/IR22141(SS) 3.3V HIN LIN 50% ton 50% PW in toff tr tf PW out HO (HOP=HON) LO (LOP=LON) 90% 90% 10% 10% Figure 7: Switching Time Waveforms Ton1 Io1+ Io2+ Figure 8: Output Source Current www.irf.com 7 IR2214/IR22141(SS) ADVANCE DATA 3.3V HIN/LIN tDS DSH/DSL VDESAT+ VDESAT- SSD Driver Enable tDESAT tSS HO/LO Figure 9: Soft Shutdown Timing Waveform 8 www.irf.com IR2214/IR22141(SS) ADVANCE DATA HIN 50% 50% LIN 50% 8V 8V DSH 8V DSL SY_FLT 50% 8V 50% tSY_FLT,DESAT1 50% tSY_FLT,DESAT2 50% tSY_FLT,DESAT3 tSY_FLT,DESAT4 FAULT/SD FLTCLR HON 90% SoftShutdown 50% 10% tBL LON 90% SoftShutdown 50% tBL 90% tDESAT2 ton tDESAT1 90% 50% 10% SoftShutdown tBL ton 90% 50% tBL toff SoftShutdown tDESAT4 tDESAT3 Figure 10: Desat Timing LIN HIN 50% HO (HOP=HON) 50% 50% 50% DTH DTL 50% LO (LOP=LON) 50% MDT=DTH-DTL Figure 11: Internal Dead-Time Timing www.irf.com 9 IR2214/IR22141(SS) ADVANCE DATA Lead Assignments HIN 1 24 VB LIN 24-Lead SSOP – IR2214SS DSH FLT_CLR N.C. SY_FLT HOP FAULT/SD HON SSOP24 VSS SSDL VS SSDH COM N.C. LON N.C. LOP N.C. VCC N.C. DSL 12 13 N.C. Lead Definitions Symbol Description VCC VSS HIN LIN Low side gate driver supply Logic Ground Logic input for high side gate driver outputs (HOP/HON) Logic input for low side gate driver outputs (LOP/LON) Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault FAULT/SD condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status. Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD SY_FLT sequence is occurring. As an input, an active low signal freezes both output status. FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17) LOP Low side driver sourcing output LON Low side driver sinking output DSL Low side IGBT desaturation protection input SSDL Low side soft shutdown COM Low side driver return VB High side gate driver floating supply HOP High side driver sourcing output HON High side driver sinking output DSH High side IGBT desaturation protection input SSDH High side soft shutdown VS High side floating supply return 10 www.irf.com IR2214/IR22141(SS) ADVANCE DATA Functional Block Diagram VCC VB on/off SCHMITT TRIGGER INPUT HIN on/off (HS) SHOOT THROUGH PREVENTION LIN INPUT HOLD LOGIC OUTPUT SHUTDOWN LOGIC on/off (LS) on/off LEVEL SHIFTERS LATCH LOCAL DESAT PROTECTION desat soft di/dt control Driver HOP HON shutdown SOFT SHUTDOWN SSDH UV_VBS DETECT (DT) Deadtime UV_VCC DETECT Hard ShutDown internal Hold DSH VS UV_VCC on/off DesatHS SY_FLT FAULT/SD SSD HOLD FAULT SD FLT_CLR VSS www.irf.com FAULT LOGIC managemend (See figure 14) LOCAL DESAT PROTECTION SOFTSHUTDOWN soft di/dt control Driver LOP LON shutdown SSDL DesatLS DSL COM 11 IR2214/IR22141(SS) ADVANCE DATA State Diagram SY _ FL T Start-Up Sequence FL T_ CC UV_V HI N/ LI N FAU LT/S D DESAT EVENT D /S UnderVoltage VBS HO=0, LO=LIN UV_VCC T HO/LO=1 UnderVoltage VCC HO=LO=0 T UL FA L _F SY HIN /LIN FAULT BS _V UV CL R FAULT /SD ShutDown HO=LO=0 C _V C UV FA UL T FAU LT/S D Freeze DS H/ L L H/ DS FLT SY_ Soft ShutDown /S D UV_VBS Stable State Temporary State System Variable − − − − − − − − − − − − − − − − FAULT HO=LO=0 (Normal operation) HO/LO=1 (Normal operation) UNDERVOLTAGE VCC SHUTDOWN (SD) UNDERVOLTAGE VBS FREEZE SOFT SHUTDOWN START UP SEQUENCE FLT_CLR HIN/LIN UV_VCC UV_VBS DSH/L SY_FLT FAULT/SD NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event happens in HIN. 12 www.irf.com IR2214/IR22141(SS) ADVANCE DATA IR2214 Logic Table Output drivers status description HO/LO status HOP/LOP HON/LON SSDH/SSDL 0 1 SSD LO/HO HiZ 1 HiZ 0 HiZ HiZ HiZ HiZ 0 Output follows inputs (in=1->out=1, in=0->out=0) LOn-1/HOn-1 Output keeps previous status Under Voltage INPUTS FAULT/SD SY_FLT Operation Hin Lin FLT_CLR X Shut Down X X Fault Clear HIN LIN 1 0 0 Normal Operation 0 1 0 0 Anti Shoot Through 1 1 Soft Shut Down (entering) Soft Shut Down (finishing) Freeze Under Voltage Yes: V< UV threshold No : V> UV threshold X : don’t care INPUT/OUTPUT SSD: desat (out) HOLD: freezing (in) SD: shutdown (in) FAULT: diagnostic (out) X 0 (SD) VCC VBS OUTPUTS HO LO X X 0 0 (FAULT) No No HO LO 1 1 No No 1 0 0 1 1 No No 0 1 0 1 1 No No 0 0 0 1 0 NOTE1 1 No No 0 1 0 0 (SSD) 1 No No SSD 0 0 1 0 (SSD) 1 No No 0 SSD X X 0 (SSD) (FAULT) No No 0 0 0 (SSD) (FAULT) No No 0 0 X X X X X 0 (HOLD) 1 No No HOn-1 LOn-1 X LIN X 1 1 No Yes 0 LO X X X 1 0 (FAULT) Yes X 0 0 NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required. In order to avoid FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active. www.irf.com 13 IR2214/IR22141(SS) ADVANCE DATA FEATURES DESCRIPTION 1. Start-up sequence At power supply start-up it is recommended to keep FLT_CLR pin active until supply voltages are properly established. This prevents spurious diagnostic signals being generated. All protection functions are operating independently from FLT_CLR status and output driver status reflects the input commands. When bootstrap supply topology is used for supplying the floating high side stage, the following start-up sequence is recommended (see also figure 12): 1. Set Vcc 2. Set FLT_CLR pin to HIGH level 3. Set LIN pin to HIGH level and let the bootstrap capacitor be charged 4. Release LIN pin to LOW level 5. Release FLT_CLR pin to LOW level 2. Normal operation mode After start-up sequence has been terminated, the device becomes fully operative (see grey blocks in the State Diagram). HIN and LIN produce driver outputs to switch accordingly, while the input logic checks the input signals preventing shoot-through events and including DeadTime (DT). 3. Shut down The system controller can asynchronously command the Hard ShutDown (HSD) through the 3.3 V compatible CMOS I/O FAULT/SD pin. This event is not latched. In a multi-phase system, FAULT/SD signals are or-wired so the controller or one of the gate drivers can force simultaneous shutdown to the other gate drivers through the same pin. 4. Fault management IR2214 is able to manage both the supply failure (undervoltage lock out on both low and high side circuits) and the desaturation of both power transistors. VCC FLT_CLR LIN LO Figure 12 Start-up sequence A minimum 15µs LIN and FLT-CLR pulse is required. 14 4.1 Undervoltage (UV) The Undervoltage protection function disables the driver’s output stage preventing the power device being driven with too low voltages. Both the low side (VCC supplied) and the floating side (VBS supplied) are controlled by a dedicate undervoltage function. Undervoltage event on the V CC (when VCC < UVVCC-) generates a diagnostic signal by forcing FAULT/SD pin low (see FAULT/SD section and figure 14). This event disables both low side and floating drivers and the diagnostic signal holds until the under voltage condition is over. Fault condition is not latched and the FAULT/SD pin is released once VCC becomes higher than UVVCC+. www.irf.com ADVANCE DATA The undervoltage on the VBS works disabling only the floating driver. Undervoltage on VBS does not prevent the low side driver to activate its output nor generate diagnostic signals. VBS undervoltage condition (VBS < UVVBS-) latches the high side output stage in the low state. VBS must be reestablished higher than UVVBS+ to return in normal operating mode. To turn on the floating driver HIN must be re-asserted high (rising edge event on HIN is required). 4.2 Power devices desaturation Different causes can generate a power inverter failure: phase and/or rail supply short-circuit, overload conditions induced by the load, etc… In all these fault conditions a large current increase is produced in the IGBT. The IR2214 fault detection circuit monitors the IGBT emitter to collector voltage (VCE) by means IR2214/IR22141(SS) of an external high voltage diode. High current in the IGBT may cause the transistor to desaturate, i.e. VCE to increase. Once in desaturation, the current in power transistor can be as high as 10 times the nominal current. Whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltages). The IR2214 gate driver accomplish the transients control by smoothly turning off the desaturated transistor by means of the SSD pin activating a so called Soft ShutDown sequence (SSD). 4.2.1 Desaturation detection: DSH/L function Figure 13 shows the structure of the desaturation sensing and soft shutdown block. This configuration is the same for both high and low side output stages. VB/Vcc PreDriver on/off sensing diode HOP/LOP ONE SHOT (ton1) HON/LON tss One Shot DesatHS/LS SSDH/L RDSH/L Ron,ss tBL Blanking DSH/L tDS filter desat comparator VDESAT VS/COM Figure 13: high and low side output stage www.irf.com 15 IR2214/IR22141(SS) internal HOLD ADVANCE DATA internal FAULT (hard shutdown) SY_FLT (external hold) FAULT/SD (external hard shutdown) Q Q SET CLR S DesatHS R DesatLS UVCC FLTCLR Figure 14: fault management diagram The external sensing diode should have BV>1200V and low stray capacitance (in order to minimize noise coupling and switching delays). The diode is biased by an internal pull-up resistor RDSH/L (equal to VCC/IDS- or VBS/IDS- for IR2214) or by a dedicated circuit (see the activebias section for the IR22141). When VCE increases, the voltage at DSH/L pin increases too. Being internally biased to the local supply, DSH/L voltage is automatically clamped. When DSH/L exceeds the VDESAT+ threshold the comparator triggers (see figure 13). Comparator output is filtered in order to avoid false desaturation detection by externally induced noise; pulses shorter than tDS are filtered out. To avoid detecting a false desaturation during IGBT turn on, the desaturation circuit is disabled by a Blanking signal (TBL, see Blanking block in figure 13). This time is the estimated maximum IGBT turn on time and must be not exceeded by proper gate resistance sizing. When the IGBT is 16 not completely saturated after TBL, desaturation is detected and the driver will turn off. Eligible desaturation signals initiate the Soft Shutdown sequence (SSD). While in SSD, the output driver goes in high impedance and the SSD pull-down is activated to turn off the IGBT through SSDH/L pin. The SY_FLT output pin (active low, see figure 14) reports the IR2214 status all the way long SSD sequence lasts (tSS). Once finished SSD, SYS_FLT releases, and IR2214 generates a FAULT signal (see the FAULT/SD section) by activating FAULT/SD pin. This generates a hard shut down for both high and low output stages (HO=LO=low). Each driver is latched low until the fault is cleared (see FLT_CLR). Figure 14 shows the fault management circuit. In this diagram DesatHS and DesatLS are two internal signals that come from the output stages (see figure 13). www.irf.com IR2214/IR22141(SS) ADVANCE DATA FAULT FAULT/SD DSH LOP FAULT/SD COM phase U DSH LOP HOP HON FLT_CLR SY_FLT VS LON SSL VB LIN HIN SSH DSL VSS VCC HOP HON FLT_CLR SY_FLT VS LON SSL VB LIN HIN SSH IR2214 FLT_CLR SY_FLT VCC HOP HON SSH IR2214 VB LIN HIN IR2214 VCC FAULT/SD COM VS LOP LON SSL DSL VSS DSH DSL VSS phase V COM phase W Figure 15: IR2214 application in 3ph system. It must be noted that while in Soft Shut Down, both Under Voltage fault and external Shut Down (SD) are masked until the end of SSD. Desaturation protection is working independently by the other entire control pin and it is disabled only when the output status is off. 4.2.2 Fault management in multi-phase systems In a system with two or more gate drivers the IR2214 devices must be connected as in figure 15. SY_FLT. The bi-directional SY_FLT pins communicate each other in the local network. The logic signal is active low. The device that detects the IGBT desaturation activates the SY_FLT, which is then read by the other gate drivers. When SYS_FLT is active all the drivers hold their output state regardless the input signals (HIN, LIN) they receive from the controller (freeze state). This feature is particularly important in phasewww.irf.com to-phase short circuit where two IGBTs are involved; in fact, while one is softly shutting-down, the other must be prevented from hard shutdown to avoid vanishing SSD. In the Freeze state the frozen drivers are not completely inactive because desaturation detection still takes the highest priority. SY_FLT communication has been designed for creating a local network between the drivers. There is no need to wire SY_FLT to the controller. FAULT/SD The bi-directional FAULT/SD pins communicates each other and with the system controller. The logic signal is active low. When low, the FAULT/SD signal commands the outputs to go off by hard shutdown. There are three events that can force FAULT/SD low: 1. Desaturation detection event: the FAULT\SD pin is latched low when SSD is over, and only a FLT_CLR signal can reset it. 17 ADVANCE DATA 5. Active bias For the purpose of sensing the power transistor desaturation the collector voltage is read by an external HV diode. The diode is normally biased by an internal pull up resistor connected to the local supply line (VB or VCC). When the transistor is “on” the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. In the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see figure 19). In fact, too low pull up resistor value may result in high current discharging significantly the bootstrap capacitor. For that reason typical pull up resistor are in the range of 100 kΩ. This is the value of the internal pull up. While the impedance of DSH/DSL pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. In that case relevant dV/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (DSH/L). This coupled noise may be easily reduced using an active bias for the sensing diode. 18 An Active Bias structure is available only for IR22141 version for DSH/L pin. The DSH/L pins present an active pull-up respectively to VB/VCC, and a pull-down respectively to VS/COM. The dedicated biasing circuit reduces the impedance on the DSH/L pin when the voltage exceeds the VDESAT threshold (see figure 16). This low impedance helps in rejecting the noise providing the current inject by the parasitic capacitance. When the power transistor is fully on, the sensing diode gets forward biased and the voltage at the DSH/L pin decreases. At this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in figure 16. RDSH/L 100K ohm 100 ohm VDSH/L VDESAT+ 2. Undervoltage on VCC: the FAULT\SD pin is forced low and held until the undervoltage is active (not latched). 3. FAULT/SD is externally driven low either from the controller or from another IR2214 device. This event is not latched; therefore the FLT_CLR cannot disable it. Only when FAULT/SD becomes high the device returns in normal operating mode. VDESAT- IR2214/IR22141(SS) Figure 16: RDSH/L Active Biasing 6. Output stage The structure is shown in figure 13 and consists of two turns on stages and one turn off stage. When the driver turns on the IGBT (see figure 8), a first stage is constantly activated while an additional stage is maintained active only for a limited time (ton1). This feature boost the total driving capability in order to accommodate both fast gate charge to the plateau voltage and dV/dt control in switching. www.irf.com IR2214/IR22141(SS) ADVANCE DATA At turn off, a single n-channel sinks up to 3A (IO) and offers a low impedance path to prevent the self-turn on due to the parasitic Miller capacitance in the power switch. A B 7. Timing and logic state diagrams description The following figures show the input/output logic diagram. Figure 17 shows the SY_FLT and FAULT/SD signals as output, whereas figure 18 shows them as input. C D E F G HIN LIN DSH DSL SY_FLT FAULT/SD FLT_CLR HO(HOP/HON) LO(LOP/LON) Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output www.irf.com 19 IR2214/IR22141(SS) ADVANCE DATA A B C D E F HIN LIN SY_FLT FAULT/SD FLT_CLR HO (HOP/HON) LO (LOP/LON) Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input Referred to timing diagram of figure 17: A. When the input signals are on together the outputs go off (anti-shoot through). B. The HO signal is on and the high side IGBT desaturates, the HO turn off softly while the SY_FLT stays low. When SY_FLT goes high the FAULT/SD goes low. While in SSD, if LIN goes up, LO does not change (freeze). C. When FAULT/SD is latched low (see FAULT/ SD section) FLT_CLR can disable it and the outputs go back to follow the inputs. D. The DSH goes high but this is not read because HO is off. E. The LO signal is on and the low side IGBT desaturates, the low side behaviour is the same as described in point B. F. The DSL goes high but this is not read because LO is off. G. As point A (anti-shoot through). 20 Referred to logic diagram figure 18: A. The device is in hold state, regardless of input variations. Hold state is forced by SY_FLT forced low externally B. The device outputs goes off by hard shutdown, externally commanded. A through B is the same sequence adopted by another IR2214 device in SSD procedure. C. Externally driven low FAULT/SD (shutdown state) cannot be disabled by forcing FLT_CLR (see FAULT/SD section). D. The FAULT/SD is released and the outputs go back to follow the inputs. E. Externally driven low FAULT/SD: outputs go off by hard shutdown (like point B). F. As point A and B but for the low side output. www.irf.com ADVANCE DATA If VGEmin is the minimum gate emitter voltage we want to maintain, the voltage drop must be: Sizing tips ∆VBS ≤ VCC − VF − VGE min − VCEon Bootstrap supply The VBS voltage provides the supply to the high side driver circuitry of the IR2214. This supply sits on top of the VS voltage and so it must be floating. The bootstrap method to generate VBS supply can be used with IR2214. The bootstrap supply is formed by a diode and a capacitor connected as in figure 19. bootstrap resistor bootstrap diode Rboot VCC HOP IR2214 VBS bootstrap capacitor VGE ILOAD motor VS SSDH VCEon VFP COM Figure 19: bootstrap supply schematic This method has the advantage of being simple and low cost but may force some limitations on duty-cycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. Bootstrap capacitor sizing To size the bootstrap capacitor, the first step is to establish the minimum voltage drop (∆VBS) that we have to guarantee when the high side IGBT is on. www.irf.com VGE min > VBSUV − where VCC is the IC voltage supply, VF is bootstrap diode forward voltage, VCEon is emitter-collector voltage of low side IGBT and VBSUV- is the high-side supply undervoltage negative going threshold. Now we must consider the influencing factors contributing VBS to decrease: VF HON under the condition: DC+ VB VCC IR2214/IR22141(SS) - IGBT turn on required Gate charge (QG); - IGBT gate-source leakage current (ILK_GE); - Floating section quiescent current (IQBS); - Floating section leakage current (ILK) - Bootstrap diode leakage current (ILK_DIODE); - Desat diode bias when on (IDS- ) - Charge required by the internal level shifters (QLS); typical 20nC - Bootstrap capacitor leakage current (ILK_CAP); - High side on time (THON). ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution). Then we have: QTOT = QG + Q LS + ( I LK _ GE + I QBS + + I LK + I LK _ DIODE + I LK _ CAP + I DS − ) ⋅ THON 21 IR2214/IR22141(SS) ADVANCE DATA The minimum size of bootstrap capacitor is: C BOOT min Q = TOT ∆VBS NOTICE: Here above VCC has been cho- sen to be 15V. Some IGBTs may require higher supply to work correctly with the bootstrap technique. Also Vcc variations must be accounted in the above formulas. An example follows: a) using a 25A @ 125C IGBT (IRGP30B120KD): Some important considerations • IQBS = 800 µA (See Static Electrical Charact.); a. Voltage ripple There are three different cases making the bootstrap circuit gets conductive (see figure 19): • ILK = 50 µA (See Static Electrical Charact.); • QLS = 20 nC; • QG = 160 nC (Datasheet IRGP30B120KD); • ILK_GE = 100 nA (Datasheet IRGP30B120KD); • ILK_DIODE = 100 µA (with reverse recovery time <100 ns); • ILK_CAP = 0 (neglected for ceramic capacitor); • IDS- = 150 µA (see Static Electrical Charact.); • THON = 100 µs. • ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon VBS = VCC − VF − VCEon In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off the Vs node is pushed up by the load current until the high side freewheeling diode get forwarded biased And: • ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected • VCC = 15 V • VF = 1 V V BS = VCC − V F • VCEonmax = 3.1 V • VGEmin = 10.5 V • ILOAD > 0; the load current flows through the freewheeling diode the maximum voltage drop ∆VBS becomes ∆VBS ≤ VCC − VF − VGEmin − VCEon = = 15V − 1V − 10.5V − 3.1V = 0.4V and the boodstrap capacitor is: CBOOT ≥ 22 290 nC = 725 nF 0.4 V VBS = VCC − VF + VFP In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. To minimize the risk of undervoltage, bootstrap capacitor should be sized according to the ILOAD<0 case. www.irf.com IR2214/IR22141(SS) ADVANCE DATA b. Bootstrap Resistor A resistor (Rboot) is placed in series with bootstrap diode (see figure 19) so to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding some Ohms (typically 5, maximum 10 Ohm) to avoid increasing the VBS time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this timeconstant. c. Bootstrap Capacitor For high THON designs where is used an electrolytic tank capacitor, its ESR must be considered. This parasitic resistance forms a voltage divider with Rboot generating a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint: Gate resistances The switching speed of the output transistor can be controlled by properly size the resistors controlling the turn-on and turn-off gate current. The following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver (RDRp and RDRn). The examples always use IGBT power transistor. Figure 20 shows the nomenclature used in the following paragraphs. In addition, Vge* indicates the plateau voltage, Qgc and Qge indicate the gate to collector and gate to emitter charge respectively. VGE ESR ⋅ VCC ≤ 3V ESR + RBOOT Parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge thank for the gate charge only and limiting the dVBS/dt by reducing the equivalent resistance while the second keeps the VBS voltage drop inside the desired ∆VBS. d. Bootstrap Diode The diode must have a BV> 1200V and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to VCC supply IC CRES t1,QGE t2,QGC VCE dV/dt IC 90% CRESon CRES VGE Vge* CRESoff 10% 10% t,Q tSW tDon tR Figure 20: Nomenclature www.irf.com 23 IR2214/IR22141(SS) ADVANCE DATA Sizing the turn-on gate resistor When RGon > 7 Ohm, RDRp is defined by • Switching-time For the matters of the calculation included hereafter, the switching time tsw is defined as the time spent to reach the end of the plateau voltage (a total Qgc+Qge has been provided to the IGBT gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and Qgc, Vcc, Vge* (see figure 21): ton1 Vcc Vcc tSW −1 when tSW > ton1 ⋅ + tSW Io1+ Io2+ ton1 RDRp = Vcc when tSW ≤ ton1 Io1+ Qgc + Qge I avg = t sw and RTOT = Vcc − V ge* I avg Vcc/Vb (IO1+ ,IO2+ and ton1 from the IR2214 datasheet). Table 1 reports the gate resistance size for two commonly used IGBTs (calculation made using typical datasheet values and assuming Vcc=15V). • Output voltage slope Turn-on gate resistor RGon can be sized to control output slope (dVOUT/dt). While the output voltage has a non-linear behaviour, the maximum output slope can be approximated by: Iavg I avg dVout = dt C RESoff CRES RDRp RGon COM/Vs Figure 21: RGon sizing where RTOT = RDRp + RGon RGon = gate on-resistor RDRp = driver equivalent on-resistance 24 inserting the expression yielding I avg and rearranging: Vcc − Vge = dV C RESoff ⋅ out dt * RTOT As an example, table 2 shows the sizing of gate resistance to get dVout/dt=5V/ns when using two popular IGBTs, typical datasheet values and assuming Vcc=15V. NOTICE: Turn on time must be lower than TBL to avoid improper desaturation detection and SSD triggering. www.irf.com IR2214/IR22141(SS) ADVANCE DATA Translated into equations:: Sizing the turn-off gate resistor Vth ≥ (RGoff + RDRn )⋅ I = (RGoff + RDRn ) dVout ⋅ C RESoff dt The worst case in sizing the turn-off resistor RGoff is when the collector of the IGBT in off state is forced to commutate by external events (i.e. the turn-on of the companion IGBT). In this case the dV/dt of the output node induces a parasitic current through CRESoff flowing in RGoff and RDRn (see figure 22). If the voltage drop at the gate exceeds the threshold voltage of the IGBT, the device may self turn on causing large oscillation and relevant cross conduction. Rearranging the equation yields: RGoff ≤ CRESoff dV dt − RDRn NOTICE: the above-described equations are intended being an approximated way for the gate resistances sizing. More accurate sizing may account more precise device modelling and parasitic component dependent on the PCB and power section layout and related connections. RGoff OFF ON C RESoff ⋅ When R Goff > 4 Ohm, RDRn is well defined by Vcc/IO- (IO- from IR2214 datasheet). As an example, table 3 reports RGoff for two popular IGBT to withstand dVout/dt = 5V/ns. dV/dt HS Turning ON Vth RDRn Figure 22: RGoff sizing: current path when Low Side is off and High Side turns on Table 1: tsw driven RGon sizing IGBT Qge Qgc Vge* tsw Iavg Rtot RGon → std commercial value Tsw IRGP30B120K(D) IRG4PH30K(D) 19nC 10nC 82nC 20nC 9V 9V 400ns 200ns 0.25A 0.15A 24Ω 40Ω RTOT - RDRp = 12.7 Ω → 10 Ω RTOT - RDRp = 32.5 Ω → 33 Ω →420ns →202ns Table 2: dVOUT/dt driven RGon sizing IGBT Qge Qgc Vge* CRESoff Rtot RGon → std commercial value dVout/dt IRGP30B120K(D) IRG4PH30K(D) 19nC 10nc 82nC 20nC 9V 9V 85pF 14pF 14Ω 85Ω RTOT - RDRp = 6.5 Ω → 8.2 Ω RTOT - RDRp = 78 Ω → 82 Ω →4.5V/ns →5V/ns Table 3: RGoff sizing IGBT Vth(min) CRESoff RGoff IRGP30B120K(D) IRG4PH30K(D) 4 3 85pF 14pF RGoff ≥? 4 Ω RGoff ≥? 35 Ω www.irf.com 25 IR2214/IR22141(SS) ADVANCE DATA Supply capacitors: PCB LAYOUT TIPS Distance from H to L voltage: The IR2214 pin out maximizes the distance between floating (from DC- to DC+) and low voltage pins. It’s strongly recommended to place components tied to floating voltage in the high voltage side of device (VB, VS side) while the other components in the opposite side. Ground plane: Ground plane must not be placed under or nearby the high voltage floating side to minimize noise coupling. Gate drive loops: Current loops behave like an antenna able to receive and transmit EM noise. In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 23 shows the high and low side gate loops. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. For this reason is strongly recommended to place the three gate resistances close together and to minimize the loop area (see figure 23). IR2214 output stages are able to quickly turn on IGBT with up to 2 A of output current. The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/ resistance. Routing and placement example: Figure 24 shows one of the possible layout solutions using a 3 layer PCB. This example takes into account all the previous considerations. Placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize respectively supply path and gate drive loop. The bootstrap diode is placed under the device to have the cathode as close as possible to bootstrap capacitor and the anode far from high voltage and close to VCC. IGC VB/ VCC gate resistance CGC H/LOP H/LON SSDH/L Gate Drive Loop VGE VS/COM Figure 23: gate drive loop 26 www.irf.com IR2214/IR22141(SS) ADVANCE DATA R2 VGH D2 DC+ R3 C1 R4 VEH VGL D3 R5 R6 D1 IR2214 Phase VCC R1 C2 VEL R7 a) b) c) Figure 24: layout example: top (a), bottom (b) and ground plane (c) layer Referred to figure 24: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3 www.irf.com 27 IR2214/IR22141(SS) ADVANCE DATA Case outline 24-Lead SSOP 01 6076 01 01 5537 01 MO-150AH IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/17/2003 28 www.irf.com