IRF IRFU5305

PD - 91402A
IRFR/U5305
HEXFET® Power MOSFET
l
l
l
l
l
l
Ultra Low On-Resistance
Surface Mount (IRFR5305)
Straight Lead (IRFU5305)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
D
VDSS = -55V
RDS(on) = 0.065Ω
G
ID = -31A
S
Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
HEXFET® Power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable device
for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
D-Pak
IRFR5305
I-Pak
IRFU5305
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current †
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚†
Avalanche Current†
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt Ġ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
Units
-31
-22
-110
110
0.71
± 20
280
-16
11
-5.0
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient**
Typ.
Max.
Units
–––
–––
–––
1.4
50
110
°C/W
10/23/00
IRFR/U5305
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
IGSS
Min. Typ. Max. Units
Conditions
-55
––– –––
V
VGS = 0V, ID = -250µA
––– -0.034 ––– V/°C Reference to 25°C, ID = -1mA
–––
––– 0.065
Ω
VGS = -10V, ID = -16A „
-2.0
––– -4.0
V
VDS = VGS, ID = -250µA
8.0
––– –––
S
VDS = -25V, ID = -16A†
–––
––– -25
VDS = -55V, VGS = 0V
µA
–––
––– -250
VDS = -44V, VGS = 0V, TJ = 150°C
–––
––– 100
VGS = 20V
nA
–––
––– -100
VGS = -20V
–––
–––
63
ID = -16A
–––
–––
13
nC
VDS = -44V
–––
–––
29
VGS = -10V, See Fig. 6 and 13 „†
–––
14
–––
VDD = -28V
–––
66
–––
ID = -16A
ns
–––
39
–––
RG = 6.8Ω
–––
63
–––
RD = 1.6Ω, See Fig. 10 „†
D
Between lead,
4.5 –––
–––
6mm (0.25in.)
nH
G
from package
–––
7.5 –––
and center of die contact …
S
––– 1200 –––
VGS = 0V
–––
520 –––
pF
VDS = -25V
–––
250 –––
ƒ = 1.0MHz, See Fig. 5 †
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
-31
A
–––
–––
-110
–––
–––
–––
–––
71
170
-1.3
110
250
V
ns
nC
Conditions
D
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
S
TJ = 25°C, IS = -16A, VGS = 0V „
TJ = 25°C, IF = -16A
di/dt = -100A/µs „†
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
‚ VDD = -25V, starting TJ = 25°C, L = 2.1mH
RG = 25Ω, IAS = -16A. (See Figure 12)
ƒ ISD ≤ -16A, di/dt ≤ -280A/µs, VDD ≤ V(BR)DSS,
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact.
† Uses IRF5305 data and test conditions.
TJ ≤ 175°C
* When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
** Uses typical socket mount.
2
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IRFR/U5305
1000
1000
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOT TOM - 4.5V
VGS
- 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
TOP
-ID , D rain-to-S ourc e C urrent (A )
-ID , D rain-to-S ou rc e C urre nt (A )
TO P
100
10
-4.5 V
2 0µ s P U LS E W ID TH
T cJ = 2 5°C
A
1
0.1
1
10
100
10
-4 .5 V
20 µ s P U L S E W ID T H
TCJ = 17 5°C
1
0.1
100
1
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
2.0
R D S (on) , Drain-to-S ource O n Resistance
(N orm alized)
-I D , D rain-to -So urc e C urre nt (A )
100
TJ = 2 5°C
TJ = 17 5 °C
10
V DS = -2 5 V
2 0µ s P U L S E W ID TH
4
5
6
7
8
9
-V G S , G ate -to-Source Volta ge (V )
Fig 3. Typical Transfer Characteristics
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A
100
-VD S , D rain-to-S ource V oltage (V )
-VD S , D rain-to-S ourc e V oltage (V )
1
10
10
A
I D = -27 A
1.5
1.0
0.5
V G S = -10 V
0.0
-60
-40
-20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction T em perature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U5305
C, C apacitanc e (pF )
2000
C iss
V GS
C iss
C rs s
C o ss
=
=
=
=
20
0V ,
f = 1MHz
C g s + C g d , C d s S H O R TE D
C gd
C ds + C g d
-V G S , G ate -to-S ou rc e V oltage (V )
2500
V D S = -4 4V
V D S = -2 8V
16
C oss
1500
I D = -1 6A
12
1000
C rss
500
0
10
4
FO R TE S T C IR C U IT
S E E FIG U R E 1 3
0
A
1
8
100
0
-V D S , D rain-to-S ourc e V oltage (V )
30
40
50
A
60
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
O P E R A TIO N IN TH IS A R E A L IM ITE D
B Y R D S (o n)
-ID , D rain C urrent (A )
-IS D , R everse Drain C urrent (A )
20
Q G , Total G ate C harge (nC )
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
TJ = 17 5 °C
TJ = 25 °C
V G S = 0V
10
0.4
0.8
1.2
1.6
-VS D , S ourc e-to-D rain V oltage (V )
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
A
2.0
100
100µ s
10
1m s
10m s
T C = 25 °C
T J = 17 5°C
S ing le P u lse
1
1
10
100
-VD S , D rain-to-S ourc e V oltage (V )
Fig 8. Maximum Safe Operating Area
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A
IRFR/U5305
RD
VDS
35
VGS
30
D.U.T.
RG
-
-ID , Drain Current (A)
+
VDD
25
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
15
10
td(on)
tr
t d(off)
tf
VGS
5
10%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
90%
VDS
Fig 10b. Switching Time Waveforms
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
P DM
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U5305
L
VDS
+
-
D .U .T
RG
IA S
-2 0 V
tp
VD D
A
D R IV E R
0 .0 1 Ω
15V
Fig 12a. Unclamped Inductive Test
Circuit
IAS
E A S , S ingle Pulse Avalanc he E nergy (m J)
700
TO P
600
BOTTOM
ID
-6.6 A
-11 A
-1 6A
500
400
300
200
100
0
V D D = -2 5V
25
50
A
75
100
125
150
175
S tarting T J , J unc tion T em perature (°C )
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
tp
V (BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
-10V
QGS
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U5305
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
‚
-
-
„
+
**

• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS*
+
-
*
VDD
*
Reverse Polarity for P-Channel
** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive
P.W.
D=
Period
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
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7
IRFR/U5305
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
6 .7 3 (.2 6 5 )
6 .3 5 (.2 5 0 )
-A 1 .2 7 (.0 5 0 )
0 .8 8 (.0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
1 .1 4 (.0 4 5 )
0 .8 9 (.0 3 5 )
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
4
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
6 .2 2 (.2 4 5 )
5 .9 7 (.2 3 5 )
1.0 2 (.0 4 0 )
1.6 4 (.0 2 5 )
1
2
1 0 .4 2 (.4 1 0 )
9 .4 0 (.3 7 0 )
0 .5 1 (.0 2 0 )
M IN .
-B 1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
2X
1 .1 4 (.0 4 5 )
0 .7 6 (.0 3 0 )
L E A D A S S IG N M E N T S
1 - GATE
3
2 - D R A IN
3 - S OU R CE
4 - D R A IN
0 .8 9 (.0 3 5 )
3X
0 .6 4 (.0 2 5 )
0 .2 5 ( .0 1 0 )
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
M A M B
N O TE S :
2 .2 8 ( .0 9 0 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 .
4 .5 7 ( .1 8 0 )
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A .
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
D-Pak (TO-252AA) Part Marking Information
8
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IRFR/U5305
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 )
6 .3 5 (.25 0 )
2 .3 8 (.0 9 4 )
2 .1 9 (.0 8 6 )
-A 1 .2 7 ( .0 5 0 )
0 .8 8 ( .0 3 5 )
5 .4 6 (.2 1 5 )
5 .2 1 (.2 0 5 )
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
L E A D A S S IG N M E N T S
4
6 .4 5 (.2 4 5 )
5 .6 8 (.2 2 4 )
6 .2 2 ( .2 4 5 )
5 .9 7 ( .2 3 5 )
1 .5 2 (.0 6 0 )
1 .1 5 (.0 4 5 )
1
2
2.2 8 (.0 9 0)
1.9 1 (.0 7 5)
1 .1 4 (.0 45 )
0 .7 6 (.0 30 )
2 .28 (.0 9 0 )
2X
3 - SOURCE
4 - D R A IN
3
-B -
3X
1 - GATE
2 - D R A IN
3X
9 .6 5 ( .3 8 0 )
8 .8 9 ( .3 5 0 )
N O TE S :
1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 .
2 C O N T R O L L IN G D IM E N S IO N : IN C H .
3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A .
4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP ,
S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ).
0 .8 9 (.0 35 )
0 .6 4 (.0 25 )
1 .1 4 ( .0 4 5 )
0 .8 9 ( .0 3 5 )
0 .2 5 (.0 1 0 )
M A M B
0 .5 8 (.0 2 3 )
0 .4 6 (.0 1 8 )
I-Pak (TO-251AA) Part Marking Information
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9
IRFR/U5305
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
1 6 .3 ( .6 4 1 )
1 5 .7 ( .6 1 9 )
1 2 .1 ( .4 7 6 )
1 1 .9 ( .4 6 9 )
FE E D D IR E C TIO N
TR L
1 6 .3 ( .64 1 )
1 5 .7 ( .61 9 )
8 .1 ( .3 18 )
7 .9 ( .3 12 )
FE E D D IR E C T IO N
N O T ES :
1 . C O N T R O L L IN G D IM EN S IO N : M IL L IM ET E R .
2 . AL L D IM EN SIO N S AR E SH O W N IN M IL L IM ET E R S ( IN C H E S ).
3 . O U TL IN E C O N F O R M S T O E IA -4 81 & E IA -54 1 .
1 3 IN C H
16 m m
N O T ES :
1 . O U TL IN E C O N F O R M S T O E IA-4 8 1 .
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936
Data and specifications subject to change without notice. 10/00
10
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