INFINEON TLE4270

5-V Low-Drop Fixed Voltage Regulator
TLE 4270
Features
•
•
•
•
•
•
•
•
•
•
•
Output voltage tolerance ≤ ± 2 %
Low-drop voltage
Integrated overtemperature protection
Reverse polarity protection
Input voltage up to 42 V
Overvoltage protection up to 65 V (≤ 400 ms)
Short-circuit proof
Suitable for use in automotive electronics
Wide temperature range
Adjustable reset time
ESD protection > 4000 V
Type
Ordering Code
Package
TLE 4270
Q67000-A9209-A903 P-TO220-5-11
TLE 4270 S
Q67000-A9243-A904 P-TO220-5-12
TLE 4270 G
Q67006-A9201-A901 P-TO263-5-1
▼ TLE 4270
Q67000-A9209-A801 P-TO220-5-1
▼ TLE 4270 S
Q67000-A9243-A802 P-TO220-5-2
▼ TLE 4270 G
Q67006-A9201-A802 P-TO220-5-8
● TLE 4270 D
Q67006-A9360
▼ Not for new design
P-TO252-5-1
P-TO220-5-11
(P-TO220-5-1)
P-TO220-5-12
(P-TO220-5-2)
P-TO263-5-1
(P-TO220-5-8)
● New type
Functional Description
This device is a 5-V low-drop fixed-voltage regulator.
The maximum input voltage is 42 V (65 V, ≤ 400 ms).
Up to an input voltage of 26 V and for an output current
up to 550 mA it regulates the output voltage within a
P-TO252-5-1 (D-PAK)
2 % accuracy. The short circuit protection limits the
output current of more than 650 mA. The device incorporates overvoltage protection
and temperature protection that disables the circuit at unpermissibly high temperatures.
Semiconductor Group
1
1998-11-01
TLE 4270
Pin Configuration
(top view)
P-TO220-5-11
(P-TO220-5-1)
P-TO263-5-1
(P-TO220-5-8)
P-TO220-5-12
(P-TO220-5-2)
1
1
5
1
5
Ι
5
RO
D
GND Q
AEP01922
P-TO252-5-1 (D-PAK)
D
RO
Ι
GND Q
Ι
GND
GND Q
RO
D
AEP02172
AEP01923
1
5
Ι RO
D Q
AEP02580
Figure 1
Pin Definitions and Functions
Pin
Symbol
Function
1
I
Input; block to ground directly on the IC with ceramic capacitor
2
RO
Reset Output; the open collector output is connected to the 5 V output
via an integrated resistor of 30 kΩ.
3
GND
Ground; internally connected to heatsink.
4
D
Reset Delay; connect a capacitor to ground for delay time adjustment.
5
Q
5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω.
Semiconductor Group
2
1998-11-01
TLE 4270
Application Description
The IC regulates an input voltage in the range of 5.5 V < VI < 36 V to VQnom = 5.0 V. Up
to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. A reset signal is generated for an output voltage of VQ < 4.5 V. The delay for
power-on reset can be set externally with a capacitor.
Design Notes for External Components
An input capacitor CI is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of
< 3 Ω.
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
If the output voltage decreases below 4.5 V, an external capacitor CD on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a
reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above 4.5 V, CD will be charged with constant current. After the power-on-reset time
the voltage on the capacitor reaches VDU and the reset output will be set high again. The
value of the power-on-reset time can be set within a wide range depending of the
capacitance of CD.
The IC also incorporates a number of internal circuits for protection against:
•
•
•
•
Overload
Overvoltage
Overtemperature
Reverse polarity
Semiconductor Group
3
1998-11-01
TLE 4270
Saturation
Control and
Protection
Circuit
Temperature
Sensor
Input
5
1
Control
Amplifier
Adjustment
Bandgap
Reference
Buffer
+
-
Reset
Generator
Output
2 Reset
Output
4 Reset
Delay
3
GND
AEB01924
Figure 2
Block Diagram
Semiconductor Group
4
1998-11-01
TLE 4270
Absolute Maximum Ratings
Tj = – 40 to 150 °C
Parameter
Symbol
Limit Values
Unit
Notes
V
V
t ≤ 400 ms
min.
max.
VI
VI
II
– 42
42
65
VR
IR
– 0.3
VD
ID
– 0.3
VQ
IQ
– 1.0
IGND
– 0.5
–
A
–
°C
°C
–
– 50
150
150
Input
Voltage
Voltage
Current
internally limited
Reset Output
Voltage
Current
7
V
Internally limited
Reset Delay
Voltage
Current
7
V
Internally limited
Output
Voltage
Current
16
V
Internally limited
Ground
Current
Temperatures
Junction temperature
Storage temperature
Tj
Tstg
Optimum reliability and life time are guaranteed if the junction temperature does not
exceed 125 °C in operating mode. Operation at up to the maximum junction temperature
of 150 °C is possible in principle. Note, however, that operation at the maximum
permitted ratings could affect the reliability of the device.
Semiconductor Group
5
1998-11-01
TLE 4270
Operating Range
Parameter
Symbol
Input voltage
Junction temperature
Limit Values
Unit
Notes
min.
max.
VI
Tj
6
42
V
–
– 40
150
°C
–
Rthja
–
65
70
K/W
K/W
TO263, TO2521)
Rthjc
Zthjc
–
3
2
K/W
K/W
Thermal Resistance
Junction ambient
Junction case
1)
t < 1 ms
(TO-220/263
Packages)
Soldered in, min. footprint
Characteristics
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Output voltage
VQ
4.90
5.00
5.10
V
5 mA ≤ IQ ≤ 550 mA;
6 V ≤ VI ≤ 26 V
Output voltage
VQ
4.90
5.00
5.10
V
26 V ≤ VI ≤ 36 V;
IQ ≤ 300 mA
Output current
limiting
IQmax
650
850
–
mA
VQ = 0 V
Current
consumption
Iq = II − IQ
Iq
–
1
1.5
mA
IQ = 5 mA
Current
consumption
Iq = II – IQ
Iq
–
55
75
mA
IQ = 550 mA
Current
consumption
Iq = II – IQ
Iq
–
70
90
mA
IQ = 550 mA; VI = 5 V
Drop voltage
Vdr
–
350
700
mV
IQ = 550 mA1)
Semiconductor Group
6
1998-11-01
TLE 4270
Characteristics (cont’d)
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
IQ = 5 to 550 mA;
VI = 6 V
VI = 6 to 26 V
IQ = 5 mA
fr = 100 Hz;
Vr = 0.5 VSS
Load regulation
∆VQ
–
25
50
mV
Supply voltage
regulation
∆VQ
–
12
25
mV
Power supply
Ripple rejection
PSRR
–
54
–
dB
4.5
4.65
4.8
V
–
4.5
–
–
V
–
Reset low voltage
VRT
VROH
VROL
–
60
–
mV
Reset low voltage
VROL
–
200
400
mV
Rintern = 30 kΩ2);
1.0 V ≤ VQ ≤ 4.5 V
IR = 3 mA, VQ = 4.4 V
Reset pull-up
R
18
30
46
kΩ
internally connected
to Q
Lower reset timing
threshold
VDRL
0.2
0.45
0.8
V
VQ < VRT
Charge current
Id
VDU
8
14
25
µA
VD = 1.0 V
1.4
1.8
2.3
V
–
–
13
–
ms
–
–
3
µs
CD = 100 nF
CD = 100 nF
42
44
46
V
–
Reset Generator
Switching threshold
Reset High voltage
Upper timing
threshold
td
Reset reaction time tRR
Delay time
Overvoltage Protection
Turn-Off voltage
VI, ov
1)
Drop voltage = VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
2)
Reset peak is always lower than 1.0 V.
Semiconductor Group
7
1998-11-01
TLE 4270
ΙΙ
1
1000 µF
5
ΙQ
22 µF
470 nF
TLE 4270G
2
VΙ
4
VQ
3
ΙD
VD
ΙR
Ι GND
CD
VR
AES01925
Figure 3
Test Circuit
5 V-Output
TLE 4270
470 nF
Reset
to MC
5
1
Input
22 µF
4
2
100 nF
3
AES01926
Figure 4
Application Circuit
Semiconductor Group
8
1998-11-01
TLE 4270
VΙ
< t RR
VQ
V RT
dV Ι d
=
dt C d
V D V DU
V DRL
td
t RR
VR
Power-on-Reset
Thermal
Shutdown
Voltage Drop Undervoltage
at Input
Secondary
Spike
Load
Bounce
AES01927
Figure 5
Time Response
Semiconductor Group
9
1998-11-01
TLE 4270
Output Voltage VQ versus
Temperature Tj
AED01928
5.20
VQ
Output Voltage VQ versus
Input Voltage VI
AED01929
12
V
VQ
V
10
5.10
V Ι = 13.5 V
5.00
8
4.90
6
4.80
4
4.70
2
4.60
-40
0
0
40
80
120 C 160
Tj
Output Current IQ versus
Temperature Tj
ΙQ
0
2
4
6
8 V 10
VΙ
Output Current IQ versus
Input Voltage VI
AED01930
1200
R L = 25 Ω
AED01931
1.2
mA
ΙQ
1000
A
1.0
T j = 25 C
800
0.8
600
0.6
T j = 125 C
400
0.4
200
0.2
0
-40
0
0
Semiconductor Group
40
80
120 C 160
Tj
10
0
10
20
30
40 V 50
VΙ
1998-11-01
TLE 4270
Current Consumption Iq
versus Output Current IQ
Current Consumption Iq
versus Output Current IQ
AED01932
6
Ιq
AED01933
80
mA
Ι q 70
mA
5
60
4
50
3
V Ι = 13.5 V
40
V Ι = 13.5 V
30
2
20
1
0
0
10
20
40
60
80
mA
ΙQ
0
120
Current Consumption Iq
versus Input Voltage VI
100
200
400
300
mA
ΙQ
600
Drop Voltage Vdr versus
Output Current IQ
AED01934
120
Ιq
0
AED01935
800
mV
V Dr 700
mA
100
600
80
500
T j = 125 C
400
60
R L = 10 Ω
300
40
R L = 20 Ω
20
0
Tj
200
R L = 50 Ω
=25 C
100
0
0
10
Semiconductor Group
20
30
40 V 50
VΙ
11
0
200
400
600
mA
ΙQ
1000
1998-11-01
TLE 4270
Charge Current Id
versus Temperature Tj
Delay Switching threshold VDU
versus Temperature Tj
AED01936
8
µA
Ιd 7
Ιd
6
3.0
V Ι = 13.5 V
VD = 1 V
5
2.0
3
1.5
2
1.0
1
0.5
0
40
Semiconductor Group
80
V Ι = 13.5 V
2.5
4
0
-40
AED01937
4.0
V
V dT 3.5
0
-40
120 C 160
Tj
12
V DU
0
40
80
120 C 160
Tj
1998-11-01
TLE 4270
Package Outlines
P-TO220-5-1
(Plastic Transistor Single Outline)
10 +0.4
10.2 -0.2
1x45˚
+0.1
1.27
+0.1
2.6
5
15.4 ±0.3
0.4 +0.1
1.7
0.8
+0.1 1)
0.6
M
5x
4.5 ±0.4
8.4 ±0.4
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Semiconductor Group
13
GPT05107
1
8.6 ±0.3
10.2 ±0.3
8.8 -0.2
19.5 max
16 ±0.4
2.8
3.75
4.6 -0.2
Dimensions in mm
1998-11-01
TLE 4270
P-TO220-5-2
(Plastic Transistor Single Outline)
10 +0.4
10.2 -0.2
1x45˚
+0.1
1.27
+0.1
1
5
15.4 ±0.3
12.9 ±0.2
10.9 ±0.2
8.8 -0.2
2.8
3.75
4.6 -0.2
0.4 +0.1
1.7
0.8 +0.1 1)
0.6
M
2.6 ±0.15
GPT05256
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Semiconductor Group
14
Dimensions in mm
1998-11-01
TLE 4270
P-TO220-5-11
(Plastic Transistor Single Outline)
10 ±0.2
A
9.8 ±0.15
4.4
3.7 ±0.3
10.2 ±0.3
8.6 ±0.3
C
0.05
9.25 ±0.2
1.27 ±0.1
2.8 ±0.2
1)
13.4
15.65 ±0.3
17±0.3
8.5 1)
3.7-0.15
0.5 ±0.1
0...0.15
2.4
0.8 ±0.1
1.7
1)
3.9 ±0.4
0.25
M
A C
8.4 ±0.4
Typical
All metal surfaces tin plated, except area of cut.
GPT09064
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Semiconductor Group
15
Dimensions in mm
1998-11-01
TLE 4270
P-TO220-5-12
(Plastic Transistor Single Outline)
10 ±0.2
A
9.8 ±0.15
B
1)
0...0.15
13 ±0.5
0.05
0.5 ±0.1
6x
0.8 ±0.1
1.7
9.25 ±0.2
1.27 ±0.1
11±0.5
C
1)
4.4
2.8 ±0.2
1)
13.4
15.65 ±0.3
17±0.3
8.5
3.7 -0.15
2.4
0.25
M
A B C
Typical
All metal surfaces tin plated, except area of cut.
GPT09065
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Semiconductor Group
16
Dimensions in mm
1998-11-01
TLE 4270
P-TO263-5-1
(Plastic Transistor Single Outline)
10 ±0.2
4.4
9.8 ±0.15
1.27 ±0.1
B
0.1
0.05
2.7 ±0.3
8 1)
2.4
4.7 ±0.5
(15)
9.25 ±0.2
1±0.3
A
8.5 1)
0...0.15
5x0.8 ±0.1
0.5 ±0.1
4x1.7
8˚ max.
1)
M
A B
Typical
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
17
0.1
GPT09113
0.25
Dimensions in mm
1998-11-01
TLE 4270
P-TO220-5-8
(Plastic Transistor Single Outline)
4.6
1.27
10.2
0.2
8.0
2.6
8.8
1.5
3.5
10.1
1)
0.8
1.7
0.4
4 x 1.7 = 6.8
GPT05873
1) shear and punch direction burr free surface
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
18
Dimensions in mm
1998-11-01
TLE 4270
P-TO252-5-1
(Plastic Transistor Single Outline)
2.3 +0.05
-0.10
A
1 ±0.1
0...0.15
0.5 +0.08
-0.04
5x0.6 ±0.1
1.14
4.56
0.9 +0.08
-0.04
0.51 min
0.15 max
per side
B
5.4 ±0.1
0.8 ±0.15
(4.17)
9.9 ±0.5
6.22 -0.2
1 ±0.1
6.5 +0.15
-0.10
0.1
0.25
M
A B
GPT09161
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
19
Dimensions in mm
1998-11-01