5-V Low-Drop Fixed Voltage Regulator TLE 4271 Features • • • • • • • • • • Output voltage tolerance ≤ ± 2% Low-drop voltage Integrated overtemperature protection Reverse polarity protection Input voltage up to 42 V Overvoltage protection up to 65 V (≤ 400 ms) Short-circuit proof Suitable for use in automotive electronics Wide temperature range Adjustable reset and watchdog time Type Ordering Code Package TLE 4271 Q67000-A9210-A901 P-TO220-7-11 TLE 4271 S Q67000-A9244-A901 P-TO220-7-12 TLE 4271 G Q67006-A9195-A901 P-TO263-7-1 ▼ TLE 4271 Q67000-A9210-C801 P-TO220-7-1 ▼ TLE 4271 S Q67000-A9244-A801 P-TO220-7-2 ▼ TLE 4271 G Q67006-A9195-A801 P-TO220-7-8 P-TO220-7-11 (P-TO220-7-1) P-TO220-7-12 (P-TO220-7-2) ▼ Not for new design P-TO263-7-1 (P-TO220-7-8) Functional Description This device is a 5-V low-drop fixed-voltage regulator. The maximum input voltage is 42 V (65 V, ≤ 400 ms). Up to an input voltage of 26 V and for an output current up to 550 mA it regulates the output voltage within a 2 % accuracy. The short circuit protection limits the output current of more than 650 mA. The IC can be switched off via the inhibit input. An integrated watchdog monitors the connected controller. The device incorporates overvoltage protection and temperature protection that disables the circuit at unpermissibly high temperatures. Semiconductor Group 1 1998-11-01 TLE 4271 Pin Configuration (top view) P-TO220-7-11 (P-TO220-7-1) P-TO220-7-12 (P-TO220-7-2) P-TO263-7-1 (P-TO220-7-8) 1 7 Ι 1 7 1 7 RO D Q INH GND W AEP01938 Ι RO D Q INH GND W AEP01939 Ι RO D Q INH GND W AEP02017 Figure 1 Pin Definitions and Functions Pin Symbol Function 1 I Input; block to ground directly on the IC with ceramic capacitor. 2 INH Inhibit 3 RO Reset Output; the open collector output is connected to the 5 V output via an integrated resistor of 30 kΩ. 4 GND Ground 5 D Reset Delay; connect a capacitor to ground for delay time adjustment. 6 W Watchdog Input 7 Q 5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω. Semiconductor Group 2 1998-11-01 TLE 4271 Application Description The IC regulates an input voltage in the range of 5.5 V < VI < 36 V to VQnom = 5.0 V. Up to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the save-operating-area protection allows operation up to 36 V with a regulated output current of more than 300 mA. Overvoltage protection limits operation at 42 V. The overvoltage protection hysteresis restores operation if the input voltage has dropped below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent current to drop below 50 µA. A reset signal is generated for an output voltage of VQ < 4.5 V. The watchdog circuit monitors a connected controller. If there is no positivegoing edge at the watchdog input within a fixed time, the reset output is set to low. The delay for power-on reset and the maximum permitted watchdog-pulse period can be set externally with a capacitor. Design Notes for External Components An input capacitor CI is necessary for compensation of line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of < 3 Ω. Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the output voltage decreases below 4.5 V, an external capacitor CD on pin 4 (D) will be discharged by the reset generator. If the voltage on this capacitor VD drops below VDRL, a reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage rises above 4.5 V, CD will be charged with constant current. After the power-on-reset time VD reaches VDU and the reset output will be set high again. The value of the power-onreset time can be set within a wide range depending on the capacity of CD. The value of the pull-up resistor at reset output is typically 30 kΩ. After VD has reached the voltage VDU and reset was set to high, the watchdog circuit is enabled and discharges CD with a constant current. If there is no positive-going edge observed at watchdog input, CD will be discharged down to VDWL. Then reset will be set low and the watchdog circuit will be disabled. CD will be charged with the current as at power-on reset until VD reaches VDU and reset will be set high again. If a watchdog pulse will be observed before CD is discharged down to VDWL, the watchdog circuit will be enabled and CD will be charged too, but reset will not be set low. After VD has reached VDU, the periodical behavior starts again. Semiconductor Group 3 1998-11-01 TLE 4271 The IC also incorporates a number of internal circuits for protection against: • • • • Overload Overvoltage Overtemperature Reverse polarity Saturation Control and Protection Circuit Temperature Sensor Ι 7 1 Control Amplifier Adjustment Bandgap Reference 3 Buffer + - Reset Generator Watchdog 2 INH 4 GND 5 6 Q R D W AEB01940 Figure 2 Block Diagram Semiconductor Group 4 1998-11-01 TLE 4271 Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes t ≤ 400 ms min. max. VI VI II – 42 – – 42 65 – V V mA VE VE IE – 42 – – 42 65 – V V mA internally limited VR IR – 0.3 – 42 – V mA – internally limited VD ID – 0.3 –5 7 5 V mA – – VW IW – 0.3 –5 7 5 V mA – – VQ IQ – 1.0 –5 16 – V mA – internally limited IGND – 0.5 – A – Tj Tstg – – 50 150 150 °C °C – – Input Voltage Voltage Current – internally limited Inhibit Voltage Voltage Current – t ≤ 400 ms Reset Output Voltage Current Reset Delay Voltage Current Watchdog Voltage Current Output Voltage Current Ground Current Temperatures Junction temperature Storage temperature Semiconductor Group 5 1998-11-01 TLE 4271 Optimum reliability and life time are guaranteed if the junction temperature does not exceed 125 °C in operating mode. Operation at up to the maximum junction temperature of 150 °C is possible in principle. Note, however, that operation at the maximum permitted ratings could affect the reliability of the device. Operating Range Parameter Symbol Limit Values Unit Notes min. max. VI Tj 6 40 V – – 40 150 °C – Junction ambient Rthja – 65 70 K/W K/W – SMD version Junction case Rthjc – – – 3 6 2 K/W K/W K/W – P-TO220-7-8 t < 1 ms Input voltage Junction temperature Thermal Resistance Zthjc Semiconductor Group 6 1998-11-01 TLE 4271 Characteristics VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Output voltage VQ 4.90 5.00 5.10 V 5 mA ≤ IQ ≤ 550 mA; 6 V ≤ VI ≤ 26 V Output voltage VQ 4.90 5.00 5.10 V Output current limiting IQmax 650 800 – mA 26 V ≤ VI ≤ 36 V; IQ ≤ 300 mA; VQ = 0 V Current consumption Iq = II Iq – – 50 µA Ve = 0 V; IQ = 0 mA Current consumption Iq = II Iq – 800 – µA Ve = 5 V; IQ = 0 mA Current consumption Iq = II – IQ Iq – 1 1.5 mA IQ = 5 mA Current consumption Iq = II – IQ Iq – 55 75 mA IQ = 550 mA Current consumption Iq = II – IQ Iq – 70 90 mA IQ = 550 mA; VI = 5 V Drop voltage Vdr ∆VQ – 350 700 mV – 25 50 mV Supply voltage regulation ∆VQ – 12 25 mV Power supply Ripple rejection PSRR – 54 – dB IQ = 550 mA1) IQ = 5 to 550 mA; VI = 6 V VI = 6 to 26 V IQ = 5 mA fr = 100 Hz; Vr = 0.5 VSS Load regulation 1) Drop voltage = VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input) Semiconductor Group 7 1998-11-01 TLE 4271 Characteristics (cont’d) VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified) Parameter Symbol Limit Values Unit Test Condition min. typ. max. 4.5 4.65 4.8 V – 4.5 – – V – Reset low voltage VRT VROH VROL – 60 – mV Reset low voltage VROL – 200 400 mV Rintern = 30 kΩ2); 1.0 V ≤ VQ ≤ 4.5 V IR = 3 mA, VQ = 4.4 V Reset pull-up R 18 30 46 KΩ internally connection to Q3 Lower reset timing threshold VDRL 0.2 0.45 0.8 V VQ < VRT Charge current Id VDU 8 14 25 µA VD = 1.0 V 1.4 1.8 2.3 V – td tRR 8 13 18 ms – – 3 µs CD = 100 nF CD = 100 nF VI, ov 40 44 46 V – VINH VINH IINH 1.0 2.0 3.5 V 0.8 1.3 3.3 V 8 12 25 µA VQ = high (> 4.5 V) VQ = low (< 0.8 V) VINH = 5 V Upper timing threshold VDU 1.4 1.8 2.3 V – Lower watchdog timing threshold VDWL 0.2 0.45 0.8 V – Discharge current Idis 1.5 2.7 3.5 µA VD = 1 V Reset Generator Switching threshold Reset high voltage Upper timing threshold Delay time Reset reaction time Overvoltage Protection Turn-Off voltage Inhibit Inhibit ON voltage Inhibit OFF voltage Inhibit current Watchdog Semiconductor Group 8 1998-11-01 TLE 4271 Characteristics (cont’d) VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified) Parameter Charge current Watchdog period Watchdog trigger time Watchdog pulse slew rate 2) Symbol Id tw twt Limit Values Unit Test Condition VD = 1 V CD = 100 nF CD = 100 nF min. typ. max. 8 14 25 µA 40 55 75 ms 30 45 66 ms see diagram VW 5 – – V/µs from 20% to 80% VQ Reset peak is always lower than 1.0 V. Semiconductor Group 9 1998-11-01 TLE 4271 ΙΙ 1000 µF 1 ΙQ 7 22 µF 470 nF TLE 4271 Ι 3 R 2 VΙ 5 6 ΙD V INH VD CD VQ 4 Ι GND VW VR AES01941 Figure 3 Test Circuit 7 1 Input 5 V-Output 470 nF Input e.g. KL 15 2 Reset to MC 3 TLE 4271 22 µF 5 4 6 100 nF AES01942 Figure 4 Application Circuit Semiconductor Group 10 1998-11-01 TLE 4271 VΙ < t RR VQ V RT dV Ι d = dt C d V D V DU V DRL td t RR VR Power-on-Reset Thermal Shutdown Voltage Drop Undervoltage at Input Secondary Spike Load Bounce AES01927 Figure 5 Time Response VW VΙ VQ t wt tw V D V DU V DWL t wr VR tw = t wt = (V DU - VDWL ) ( Ι dis + Ι d ) CD Ι d x Ι dis V DU - V DWL Ι dis CD t wr = V DU - V DWL C D = (Watchdog Reset Time) Ιd AES01943 Figure 6 Time Response, Watchdog Behavior Semiconductor Group 11 1998-11-01 TLE 4271 Output Voltage VQ versus Temperature Tj AED01928 5.20 VQ Output Voltage VQ versus Input Voltage VI (VI = Ve) AED01929 12 V VQ 5.10 V 10 V Ι = 13.5 V 5.00 8 4.90 6 4.80 4 4.70 2 4.60 -40 0 40 80 0 120 C 160 Tj Output Current IQ versus Temperature Tj ΙQ 0 2 4 6 8 V 10 VΙ Output Current IQ versus Input Voltage VI AED01930 1200 R L = 25 Ω AED01931 1.2 mA ΙQ 1000 A 1.0 T j = 25 C 800 0.8 600 0.6 T j = 125 C 400 0.4 200 0.2 0 -40 0 Semiconductor Group 40 80 0 120 C 160 Tj 12 0 10 20 30 40 V 50 VΙ 1998-11-01 TLE 4271 Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Output Current IQ AED01932 6 Ιq AED01933 80 mA Ι q 70 mA 5 60 4 50 3 V Ι = 13.5 V 40 V Ι = 13.5 V 30 2 20 1 10 0 0 20 40 60 80 mA ΙQ 0 120 Current Consumption Iq versus Input Voltage VI 100 200 400 300 mA ΙQ 600 Drop Voltage Vdr versus Output Current IQ AED01934 120 Ιq 0 AED01935 800 mV V Dr 700 mA 100 600 80 500 T j = 125 C 400 60 R L = 10 Ω 300 40 R L = 20 Ω 20 0 Tj 200 R L = 50 Ω =25 C 100 0 0 10 20 Semiconductor Group 30 40 V 50 VΙ 13 0 200 400 600 mA ΙQ 1000 1998-11-01 TLE 4271 Inhibit Current IE versus Inhibit Voltage VE AED01944 12 ΙE Output Voltage VQ versus Inhibit Voltage VE Ι e, high µA AED01945 6 VQ V 5 10 V Ι = 13.5 V T j = 25 C Ι e, on 4 8 3 6 V Ι = 13.5 V T j = 25 C 2 4 2 0 1 Ι e, off 0 0 1 3 2 4 5 V 6 VE Inhibit Current Consumptions Ie versus Temperature Tj Ιe 1 3 2 5 V 6 VE 4 Inhibit Voltages Ve versus Temperature Tj AED01946 14 0 AED01947 6 µA 12 Ve Ι e, high V 5 10 4 8 Ι e, on 3 6 V e, on 2 4 1 2 V e, off Ι e, off 0 -40 0 40 Semiconductor Group 80 120 Tj 0 -40 160 14 0 40 80 120 C 160 Tj 1998-11-01 TLE 4271 Switching Voltage VDU and VDWL versus Temperature Tj Charge Current Id and Discharge Current Idis versus Temperature Tj AED01948 2.4 V V Ι = 13.5 V V Ι 2.0 AED01949 16 µA 14 Ιd 12 V DU 1.6 10 1.2 V Ι = 13.5 V VD = 1 V 8 6 0.8 Ι dis 4 0.4 2 V DWL 0 -40 0 40 80 8 -40 120 C 160 Tj 0 40 80 120 C 160 Tj Watchdog Pulse Time Tw versus Temperature Tj AED01950 80 ms T W 70 60 50 V Ι = 13.5 V C D = 100 nF 40 30 20 10 0 -40 0 Semiconductor Group 40 80 120 C 160 Tj 15 1998-11-01 TLE 4271 Package Outlines P-TO220-7-1 (Plastic Transistor Single Outline Package) 10 +0.4 10.2 -0.2 1 x 45˚ +0.1 1.27 +0.1 8.6 ±0.3 0.4 +0.1 1.27 0.6 +0.1 1) 4.5 ±0.4 0.6 M 7x 8.4 ±0.4 1) 0.75 -0.15 at dam bar (max 1.8 from body) 1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Körper) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 15.4 ±0.3 8.8 -0.2 2.6 7 10.2 ±0.3 1 16 ±0.4 19.5 max 2.8 3.75 4.6 -0.2 16 GPT05108 Dimensions in mm 1998-11-01 TLE 4271 P-TO220-7-2 (Plastic Transistor Single Outline Package) 10 +0.4 10.2 -0.2 1 x 45˚ +0.1 1.27 +0.1 7 0.4 +0.1 0.6 +0.1 1) 0.6 M 7x 1) 0.75 -0.15 at dam bar (max 1.8 from body) 1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Körper) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. 17 2.6 GPT05257 1.27 Semiconductor Group 15.4 13 1 11 8.8 -0.2 2.8 3.75 4.6 -0.2 Dimensions in mm 1998-11-01 TLE 4271 P-TO220-7-11 (Plastic Transistor Single Outline Package) 10 ±0.2 A 9.8 ±0.15 0...0.15 3.7 ±0.3 10.2 ±0.3 0.05 0.25 0.5 ±0.1 2.4 7x 0.6 ±0.1 1.27 9.25 ±0.2 1.27 ±0.1 8.6 ±0.3 C 1) 4.4 2.8 ±0.2 1) 13.4 15.65 ±0.3 17 ±0.3 8.5 1) 3.7 -0.15 3.9 ±0.4 M A C 8.4 ±0.4 Typical All metal surfaces tin plated, except area of cut. GPT09083 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 18 Dimensions in mm 1998-11-01 TLE 4271 P-TO220-7-12 (Plastic Transistor Single Outline Package) 10 ±0.2 A 9.8 ±0.15 B 0...0.15 13 ±0.5 0.05 0.5 ±0.1 7x 0.6 ±0.1 1.27 9.25 ±0.2 1.27 ±0.1 11±0.5 C 1) 4.4 2.8 ±0.2 1) 13.4 17 ±0.3 15.65 ±0.3 8.5 1) 3.7 -0.15 2.4 0.25 M A B C Typical All metal surfaces tin plated, except area of cut. GPT09084 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 19 Dimensions in mm 1998-11-01 TLE 4271 P-TO263-7-1 (Plastic Transistor Single Outline Package) 10 ±0.2 4.4 9.8 ±0.15 1.27 ±0.1 B 0.1 A 0.05 2.4 4.7 ±0.5 2.7 ±0.3 8 1) 9.25 ±0.2 (15) 1±0.3 8.5 1) 0...0.15 7x0.6 ±0.1 0.5 ±0.1 6x1.27 1) M A B 0.1 Typical All metal surfaces tin plated, except area of cut. P-TO220-7-8 (Plastic Transistor Single Outline Package) GPT09114 8˚ max. 0.25 4.6 1.27 10.2 0.2 8.0 2.6 8.8 1.5 3.5 10.1 1) 0.6 1.27 0.4 6 x 1.27 = 7.62 GPT05874 1) shear and punch direction burr free surface Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 20 Dimensions in mm 1998-11-01