Window Discriminator TCA 965 B Preliminary Bipolar IC Features ● ● ● ● Two window settings – direct setting of lower and upper edge voltage (window edges) – indirect setting by window center voltage and half window width Adjustable hysteresis Digital outputs with open collectors for currents up to 50 mA Adjustable reference voltage VStab Type ■ TCA 965 B P-DIP-14-1 Ordering Code Package Q67000-A8338 P-DIP-14-1 ■ Not for new design The window discriminator compares an input voltage to a defined voltage window. The digital outputs show whether the input voltage is below, within or above this window. The TCA 965 B window discriminator is especially suitable as a tracking or compensating controller with a dead band in control engineering and for the selection of DC voltages within a certain tolerance of the required setpoint value in measurement engineering. When it is used as a Schmitt trigger, switching frequencies up to a typical value of 50 kHz are possible. Semiconductor Group 1 1998-02-10 TCA 965 B Functional Description Amplifier Amp 3 increases the voltage of the reference source R to VStab = 2 x VREF. The amplification factor can be altered by external wiring. With direct setting of the window, the input voltage appears on amplifier Amp 1 (V8), the upper edge voltage on comparator K2 (V6) and the lower edge voltage on comparator K1 (V7). With indirect setting of the window, the input voltage appears on inputs V6 and V7, while the center voltage is connected to amplifier A1 (V8). The voltage applied to the input (V9) of amplifier Amp 2 is subtracted symmetrically from the output voltage of amplifier Amp 1 and added. The comparators switch with hysteresis. The logic gates have open-collector outputs. If the inhibit input A or B is connected to ground, output A or B will always be high. + VS VREF 11 1 20 k Ω 5 20 k Ω _ V7 7 1 + _ 10 +Amp 3 R 2 _ K1 VStab A + 4 <_ 1 Amp 1 V8 13 1 3 12 Amp 2 V6 C 8 V=1 V9 Inhibit A Inhibit B + 9 _ 6 D V=1 1 + _ K2 14 B IEB00091 Outputs A, B, C, D are open-collector Block Diagram Semiconductor Group 2 1998-02-10 TCA 965 B Pin Configuration (top view) TCA 965 B GND 1 14 B A 2 13 C D 3 12 Inhibit B Inhibit A 4 11 +V S V REF 5 10 V Stab V6 6 9 V9 V7 7 8 V8 IEP00292 Pin Definitions and Functions Pin Symbol Pin Function in Direct Setting Indirect Setting of Window 1 2 3 4 5 GND A D Inhibit A 6 7 8 9 V6 V7 V8 V9 10 11 12 13 14 VStab + VS VREF Inhibit B C B Semiconductor Group GND Logic output A Logic output D = A @ B (AND) Connected to GND: logic output A = HIGH Internal VREF = 3 V Upper edge voltage Lower edge voltage Input voltage GND Input voltage V6/7 Input voltage V6/7 Center voltage Half window width Internal VStab = 6 V Supply voltage Connected to GND: logic output B = HIGH Logic output C = A @ B (NAND) Logic output B 3 1998-02-10 TCA 965 B Absolute Maximum Ratings Maximum ratings for ambient temperature TA = – 25 to 85 °C Parameter Symbol Limit Values min. max. Unit Supply voltage (pin 11) Difference in input voltage between pins 6, 7, 8 Input voltage (pins 6, 7, 8, 9) VS VI VI – – – 30 15 30 V V V Output current (pins 2, 3, 13, 14) IQ – 50 mA Output voltage (pins 2, 3, 13, 14) independent of VS Voltage on VREF (pin 5) VQ VR – – – 30 8 V V Output current of stabilized voltage (pin 10) I10 – 10 mA Inhibit input voltage (pins 4, 12) VIH – 7 V Junction temperature Storage temperature Tj Tstg – 55 150 125 °C °C Rth SA – 80 K/W Supply voltage VS 4.5 30 V Ambient temperature TA – 25 85 °C Thermal resistance system - air P-DIP-14-1 Operating Range Semiconductor Group 4 1998-02-10 TCA 965 B Characteristics VS = 10 V; TA = 25 °C Parameter Symbol Limit Values Unit Test Condition Test Circuit mA V2, V13 = VQH 1 min. typ. max. Current consumption Input current (pins 6, 7, 8) Input current, pin 9 Input offset voltage in direct setting of window Input offset voltage in indirect setting of window Input-voltage range on pins 6, 7, 8 Input-voltage range on pin 9 Differential input voltage IS – 5 II – II – – nA 50 20 400 3000 nA VIO – 20 20 mV 1 VIO – 50 50 mV 2 VI 1.5 VS – 1 V VI 50 VS/2 13 13 mV V V V6 – (V8 – V9) (V8 + V9) – V7 7 1 1 ∆VI < 13 V 2 Reference voltage Stabilized voltage on pin 10 TC of reference voltage Sensitivity of reference voltage to supply-voltage variation V5 2.8 3 3.2 V V10 αV5 5.5 6 0.4 6.5 V VS > 7.9 V mV/K Output reverse current IQH ∆V5/∆VS µA – 100 200 500 800 mV mV IQ = 10 mA 1 IQ = 50 mA 35 1.8 mV V – Output saturation voltage VQL IREF = 0 mV/V 2 – 1 10 – Hysteresis of window edges Inhibit threshold VU – VL V4, 12 18 1 22 Inhibit current I4, 12 – – 100 – µA – – Switching frequency fdir find – – 20 50 kHz kHz – – 1 2 Semiconductor Group 5 – – 1998-02-10 TCA 965 B VS Ι S11 11 Ι Ι6 Ι Ι7 RL 6 7 TCA 965B 2 Ι QH2 3 Ι QH3 13 Ι QH13 14 Ι QH14 RL RL RL 10 Ι Ι8 = V6 = V7 = 8 V8 5 9 Ι Ι9 1 4 12 V5 V10 VQL14 VQL13 VQL3 VQL2 IES00086 = V4 = V12 Test Circuit 1 Direct Setting of Window Semiconductor Group 6 1998-02-10 TCA 965 B VS Ι S11 11 RL 6 7 TCA 965B 2 Ι QH2 3 Ι QH3 13 Ι QH13 14 Ι QH14 RL RL RL 8 10 9 = = V8 = V9 5 1 4 12 V5 V10 VQL14 VQL13 VQL3 VQL2 V6/7 IES00087 = V4 = V12 Test Circuit 2 Indirect Setting of Window by Center Voltage and Half Window Width Semiconductor Group 7 1998-02-10 TCA 965 B Inhibit Inputs 4,12 VS V4,12 100 Ω 1 kΩ Inputs 6, 7, 8 V6,7,8 V4,12 Outputs A, B GND High >7V Not permitted open Normal function > 1.8 V Low Input 9 1 kΩ V9 Outputs VREF , VStab Outputs 2, 3, 13, 14 VStab R VREF Q IES00088 Schematic Circuit Diagrams Semiconductor Group 8 1998-02-10 TCA 965 B VS C1 R1 10 11 6 V 6 R4 2 R2 3 A D TCA 965 B R5 7 V 7 13 8 V 8 14 C C2 R6 VΙ C3 B R3 V9 9 1 4 12 R7 IES00294 To increase the switching frequency, pin 9 may be grounded via R 7 ( V9 approx. 30...40 mV). Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages V6 – V9 = Upper edge voltage V7 + V9 = Lower edge voltage V8 = Input voltage Semiconductor Group 9 1998-02-10 TCA 965 B V10 A VL VU t V7 IES00296 Definition of the Offset Voltage VIO VL + VU V 10 = --------------------– V7 2 Semiconductor Group 10 1998-02-10 TCA 965 B V8 Upper Edge V6 Lower Edge V7 t t L U t A B C D Inhibit A Pin 4 on GND 1.8 V < Pin A 1 0 4<7V 1 0 A B B C 1 0 1 0 C D D Inhibit B Pin 12 on GND 1.8 V < Pin A B 12 < 7 V A 1 0 C B C D D 1 0 1 0 1 0 IES00295 t L t t U L t U Application Circuit 1 Direct Setting of Lower and Upper Edge Voltages Semiconductor Group 11 1998-02-10 TCA 965 B VS C1 10 R1 C2 11 R3 R5 R6 8 V 8 2 9 V 9 3 A D TCA 965 B R7 VΙ 6 V 6 13 7 V 7 14 C C3 1 R2 4 B 12 R4 IES00297 Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V V6 = V7 = Input voltage V8 = Center voltage V9 = Half window width Semiconductor Group 12 1998-02-10 TCA 965 B V10 B VL VU t V8 - V9 V10 = VL - VU 2 - (V 8 - V 9 ) IES00299 Definition of the Offset Voltage VIO VL + VU V 10 = --------------------– (V 8 – V 9 ) 2 Semiconductor Group 13 1998-02-10 TCA 965 B V8 Upper Edge V6 Lower Edge V7 t t L U t A B C D Inhibit A Pin 4 on GND 1.8 V < Pin A 1 0 4<7V 1 0 A B B C 1 0 1 0 C D D Inhibit B Pin 12 on GND 1.8 V < Pin A 12 < 7 V A B 1 0 1 0 1 0 1 0 B C C D D t L t t U L t U IED00298 Application Circuit 2 Indirect Setting of Window by Center Voltage and Half-Window Width V Semiconductor Group 14 1998-02-10 TCA 965 B VS 10 RL 11 R1 VΙ RL RL 13 6 14 8 2 TCA 965B R2 R4 7 3 9 R3 P = R5 1 V3 VH VH V8 0 V7 V6 IES00089 Application Circuit 3 Symmetrically Enlarged Edge Hysteresis in Direct Setting of Window Calculation of Hysteresis VH R5 V H = V 10 -----------------R4 + R5 V V 10 10 ------------------- + -------------------------------- ≤ 10 mA R4 + R5 R1 + R2 + R3 Semiconductor Group 15 1998-02-10 TCA 965 B VS 10 RL 11 RL RL 2 R1 14 8 13 6 VΙ TCA 965B 3 7 R5 R3 9 1 R2 R4 V3 VH = V9/2 - V9/1 V9/1 V9/2 V8 0 V6/7 IES00090 Application Circuit 4 Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window Calculation of Hysteresis VH VH = V9/2 – V9/1 R 4 || R 5 V 9/1 = V 10 ------------------------------R 3 + R 4 || R 5 R4 V 9/2 = V 10 -----------------R3 + R4 Semiconductor Group 16 1998-02-10 TCA 965 B GPD05005 P-DIP-14-1 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 17 Dimensions in mm 1998-02-10