HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: -8 -8B -10 Units fCKmax. 125 100 100 MHz tCK3 8 10 10 ns tAC3 6 6 7 ns tCK2 10 12 15 ns tAC2 6 7 8 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature • Four Banks controlled by BA0 & BA1 • Programmable CAS Latency: 2 & 3 • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 • full page (optional) for sequential wrap around • Multiple Burst Read with Single Write Operation • Automatic Command • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • 4096 refresh cycles / 64 ms • Random Column Address every CLK ( 1-N Rule) • Single 3.3V +/- 0.3V Power Supply • LVTTL Interface version • Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) • -8 version for PC100 2-2-2 applications -8B version for PC100 3-2-3 applications and Controlled Precharge The HYB39S64400/800/160AT are four bank Synchronous DRAM’s organized as 4 banks x 4MBit x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’ advanced quarter micron 64MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages. The -8 version of this product is best suited for use on a 100 Mhz bus for both CAS latencies 2 & 3. Semiconductor Group 1 10.98 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Ordering Information Type Ordering Code Package Description HYB 39S64400AT-8 P-TSOP-54-2 (400mil) 4B x 4M x 4 SDRAM PC100-222 HYB 39S64400AT-8B P-TSOP-54-2 (400mil) 4B x 4M x 4 SDRAM PC100-323 HYB 39S64400AT-10 P-TSOP-54-2 (400mil) 4B x 4M x 4 SDRAM PC66-222 HYB 39S64800AT-8 P-TSOP-54-2 (400mil) 4B x 2M x 8 SDRAM PC100-222 HYB 39S64800AT-8B P-TSOP-54-2 (400mil) 4B x 2M x 8 SDRAM PC100-323 HYB 39S64800AT-10 P-TSOP-54-2 (400mil) 4B x 2M x 8 SDRAM PC66-222 HYB 39S64160AT-8 P-TSOP-54-2 (400mil) 4B x 1M x 16 SDRAM PC100-222 HYB 39S64160AT-8B P-TSOP-54-2 (400mil) 4B x 1M x 16 SDRAM PC100-323 HYB 39S64160AT-10 P-TSOP-54-2 (400mil) 4B x 1M x 16 SDRAM PC66-222 HYB 39S64xxx0ATL-8/-10 P-TSOP-54-2 (400mil) Low Power (L-versions) LVTTL-version: Pin Description and Pinouts: CLK Clock Input DQ Data Input /Output CKE Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select Vdd Power (+3.3V) RAS Row Address Strobe Vss Ground CAS Column Address Strobe Vddq Power for DQ’s (+ 3.3V) WE Write Enable Vssq Ground for DQ’s A0-A11 Address Inputs NC not connected BA0, BA1 Bank Select Semiconductor Group 2 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 4M x 16 8M x 8 16M x 4 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch) Pinout for x4, x8 & x16 organised 64M-SDRAMs Semiconductor Group 3 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Column Addresses A0 - A9, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1 Column address buffer Row address buffer Bank 0 4096 x 1024 x 4 bit Row decoder Column decoder Sense amplifier & I(O) bus Memory array Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Row decoder Refresh Counter Memory array Bank 1 4096 x 1024 x 4 bit Input buffer Row decoder Column decoder Sense amplifier & I(O) bus Column address counter Memory array Bank 2 4096 x 1024 x 4 bit Output buffer Memory array Bank 3 4096 x 1024 x 4 bit Control logic & timing generator Block Diagram for 4 bank x 4M x 4 SDRAM Semiconductor Group 4 DQM WE CAS RAS CS CKE CLK DQ0-DQ3 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Column Addresses A0 - A8, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1 Column address buffer Row address buffer Bank 0 4096 x 512 x 8 bit Row decoder Column decoder Sense amplifier & I(O) bus Memory array Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Row decoder Refresh Counter Memory array Bank 1 4096 x 512 x 8 bit Input buffer Row decoder Column decoder Sense amplifier & I(O) bus Column address counter Memory array Bank 2 4096 x 512 x 8 bit Output buffer Memory array Bank 3 4096 x 512 x 8 bit Control logic & timing generator Block Diagram for 4 banks x 2M x 8 SDRAM Semiconductor Group 5 DQM WE CAS RAS CS CKE CLK DQ0-DQ7 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Column Addresses A0 - A7, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1 Column address buffer Row address buffer Bank 0 4096x256 x16 bit Row decoder Column decoder Sense amplifier & I(O) bus Memory array Row decoder Column decoder Sense amplifier & I(O) bus Column decoder Sense amplifier & I(O) bus Row decoder Refresh Counter Memory array Bank 1 4096x256 x16 bit Input buffer Row decoder Column decoder Sense amplifier & I(O) bus Column address counter Memory array Bank 2 4096x256 x16 bit Output buffer Memory array Bank 3 4096x256 x16 bit Control logic & timing generator Semiconductor Group 6 DQML DQMU WE CAS RAS CS CLK Block Diagram for 4 banks x 1M x16 SDRAM CKE DQ0-DQ15 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. Positive The system clock input. All of the SDRAM inputs are sampled on the Edge rising edge of the clock. During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organisation: 16M x 4 SDRAM CAn = CA9 (Page Length = 1024 bits) 8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits) 4M x 16 SDRAM CAn = CA7 (Page Length = 256 bits) A0 - A11 Input Level — In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0,BA1 Input Level — Bank Select (BS) Inputs. Selects which bank is to be active. DQx Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. DQM LDQM UDQM Input Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. VDD,VSS Supply VDDQ VSSQ Supply Power and ground for the input buffers and the core logic. — Semiconductor Group — Isolated power supply and ground for the output buffers to provide improved noise immunity. 7 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device State CKE n-1 CKE n CS RAS CAS WE Idle3 DQM A0-9, A10 A11 BS0 BS1 H X L L H H X V V V Active 3 H X L H L H X V L V Read w/ Autoprecharge (READA) Active 3 H X L H L H X V H V Write (WRITE) Active3 H X L H L L X V L V 3 H X L H L L X V H V Row Activate (ACT) Read (READ) Write w/ Autoprecharge (WRITEA) Active Row Precharge (PRE) Any H X L L H L X X L V Precharge All (PREA) Any H X L L H L X X H X Mode Register Set (MRS) Idle H X L L L L X V V V No Operation (NOP) Any H X L H H H X X X X Device Deselect (INHBT) Any H X H X X X X X X X Auto Refresh (REFA) Idle H H L L L H X X X X Self Refresh Entry (REFS-EN) Idle H L X X X X X X X X X X X X X X X X Self Refresh Exit (REFS-EX) Idle (Self Refr.) L L L H H X X X L H H X H X X X L H H X H X X X L H H L L H H L Any (Power Down) L H Data Write/Output Enable Active H X X X X X L X X X Data Write/Output Disable Active H X X X X X H X X X Power Down Entry (PDN-EN) Power Down Exit (PDN-EX) Idle Active5 Note: 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BS0, BS1 signals. 4. Device state is Full Page Burst operation 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. Semiconductor Group 8 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Address Input for Mode Set (Mode Register Operation) BA1 BA0 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 A2 CAS Latency BT Burst Length Operation Mode 0 0 0 0 0 0 0 A0 Address Bus (Ax) Mode Register (Mx) Burst Type BA1 BA0 M11 M10 M9 M8 M7 0 A1 0 1 0 0 Mode M3 Type 0 burst read / burst write 0 Sequential 1 Interleave 0 burst read / single write Burst Length CAS Latency M6 M5 M4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 1 0 1 1 1 0 1 1 1 Reserved M2 M1 M0 0 0 0 0 Length Sequential Interleave 0 1 1 0 1 2 2 1 0 4 4 0 1 1 8 8 1 0 0 1 0 1 1 1 0 1 1 1 Reserved Reserved Full Page *) *) optional Semiconductor Group 9 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Semiconductor Group 10 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages. Burst Length and Sequence: Burst Starting Address Length (A2 A1 A0) Sequential Burst Addressing (decimal) 2 xx0 xx1 0, 1 1, 0 4 x00 x01 x10 x11 0, 1, 2, 1, 2, 3, 2, 3, 0, 3, 0, 1, 8 000 001 010 011 100 101 110 111 Full Page nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 Interleave Burst Addressing (decimal) 0, 1 1, 0 4 5 6 7 0 1 2 3 3 0 1 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 Cn, Cn+1, Cn+2,..... 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported (optional) Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. Semiconductor Group 11 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to „high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE „high“. One clock delay is required for mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2 and two clocks for CAS latencies 3. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the precharge command. Semiconductor Group 12 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Bank Selection by Address Bits : A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 x x all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Semiconductor Group 13 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 °C Storage temperature range......................................................................................– 55 to + 150 °C Input/output voltage .............................................................................................– 0.3 to Vdd+0.3 V Power supply voltage VDD / VDDQ.......................................................................... – 0.3 to + 4.6 V Power Dissipation............................................. ..........................................................................1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and Characteristics for LV-TTL versions: TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. Unit Notes max. Input high voltage VIH 2.0 Vdd+0.3 V 1, 2 Input low voltage VIL – 0.3 0.8 V 1, 2 Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < Vddq, all other inputs = 0 V) II(L) –5 5 µA Output leakage current (DQ is disabled, 0 V < VOUT < Vdd) IO(L) –5 5 µA Notes: 1. All voltages are referenced to VSS. 2. Vih may overshoot to Vdd + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Values Unit min. max. Input capacitance (CLK) CI1 2.5 4.0 pF Input capacitance CI2 2.5 5.0 pF CIO 4.0 6.5 pF (A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM) Input / Output capacitance (DQ) Semiconductor Group 14 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Operating Currents (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -8/-8B -10 Note max. ICC1 OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) x4 x8 x16 tck = min. tck = Infinity tck = min. tck = Infinity 100 110 130 70 75 90 mA mA mA 3 ICC2P 2 2 mA 3 ICC2PS 1 1 mA 3 ICC2N 35 30 mA 3 ICC2NS 5 5 mA 3 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 45 40 mA 3 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P 8 8 mA 3 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 x4 x8 x16 60 70 100 40 50 70 mA mA mA 3,4 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 130 90 mA 3 1 1 mA 3 500 500 µA 3 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V standard version ICC6 L-version Notes: 3. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and at 66 MHz for -10 parts. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. Semiconductor Group 15 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AC Characteristics 1)2) TA = 0 to 70 °C; VSS = 0 V; Vdd = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -8 Unit -8B -10 min. max. min. max. min. max. CAS Latency = 3 tCK CAS Latency = 2 8 10 – – 10 12 – – 10 15 – – CAS Latency = 3 tCK CAS Latency = 2 – – 125 100 – – 100 83 – – Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 6 6 6 7 – – 7 8 ns ns Clock High Pulse Width tCH 3 – 3 – 3 – ns Clock Low Pulse Width tCL 3 – 3 – 3 – ns Transition time tT 0.5 10 0.5 10 0.5 10 ns Input Setup Time tIS 2 – 2 – 2.5 – ns 4 Input Hold Time tIH 1 – 1 – 1 – ns 4 CKE Setup Time tCKS 2 – 2 – 2.5 – ns 4 CKE Hold Time tCKH 1 – 1 – 1 – ns 4 Mode Register Set-up time tRSC 16 – 20 – 20 – ns Power Down Mode Entry Time tSB 0 8 0 10 0 10 ns Row to Column Delay Time tRCD 20 – 20 – 30 – ns 5 Row Precharge Time tRP 20 – 30 – 30 – ns 5 Row Active Time tRAS 50 100k 60 100k 60 100k ns 5 Row Cycle Time tRC 70 – 80 – 90 – ns 5 Activate(a) to Activate(b) Command period tRRD 16 – 20 – 20 – ns 5 CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – CLK Clock and Clock Enable Clock Cycle Time ns ns Clock Frequency 100 MHz 66 MHz 2, 3 Setup and Hold Times Common Parameters Semiconductor Group 16 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Parameter Limit Values Symbol -8 Unit -8B -10 min. max. min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 – 64 ms Self Refresh Exit Time tSREX 10 – 10 – 10 – ns Data Out Hold Time tOH 3 – 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 8 3 10 3 10 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK Read Cycle Write Cycle Semiconductor Group 17 2 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Notes for AC Parameters: 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.5 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V.. tCH + 1.5 V 2.4 V CLOCK 0.4 V tCL tSETUP 50 Ohm tT Z=50 Ohm tHOLD I/O 50 pF 1.5V INPUT I/O tAC tAC tLZ 50 pF tOH 1.5V OUTPUT Measurement conditions for tac and toh fig.1 tHZ 3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. Semiconductor Group 18 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Package Outlines Plastic Package P-TSOPII-54 ( 400mil, 0.8mm lead pitch) 0.8 0.6 0.4 +0.05 -0.1 0.2 0.1 M 54x 54 -0.2 11.76 +- 0.2 28 1 27 22.38 1) -0.25 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side Semiconductor Group 19 TSOPII-54 ( 400 mil ) TSOP54-2.DRW O 5 max. +0.06 -0.03 10.16 +- 0.13 0.15 1 + 0.05 1.2 max. 0.15 max. Thin small outline package, SMD HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a full Page Burst Write Operation 8.2 Termination of a full Page Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Clock Suspension (using CKE) 12. 1 Clock Suspension During Burst Read CAS Latency = 2 12. 2 Clock Suspension During Burst Read CAS Latency = 3 12. 3 Clock Suspension During Burst Write CAS Latency = 2 12. 4 Clock Suspension During Burst Write CAS Latency = 3 13. Power Down Mode and Clock Suspend 14. Self Refresh ( Entry and Exit ) 15. Auto Refresh ( CBR ) 16. Random Column Read ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Column Write ( Page within same Bank) 17.1 CAS Latency = 2 17.2 CAS Latency = 3 Semiconductor Group 20 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Timing Diagrams (cont’d) 18. Random Row Read ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Random Row Write ( Interleaving Banks) with Precharge 19.1 CAS Latency = 2 19.2 CAS Latency = 3 20. Full Page Read Cycle 20.1 CAS Latency = 2 20.2 CAS Latency = 3 21. Full Page Write Cycle 21.1 CAS Latency = 2 21.2 CAS Latency = 3 22. Precharge Termination of a Burst 22.1 CAS Latency = 2 22.2 CAS Latency = 3 Semiconductor Group 21 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 1. Bank Activate Command Cycle (CAS latency = 3) T0 T1 T T T T T CLK .......... ADDRESS Bank A Col. Addr. Bank A Row Addr. .......... tRCD COMMAND Bank A Activate NOP Bank A Row Addr. Bank B Row Addr. tRRD NOP Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate : “H” or “L” tRC 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A CAS latency = 2 tCK2, DQ’s CAS latency = 3 tCK3, DQ’s Semiconductor Group NOP NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 22 NOP DOUT A3 NOP NOP HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQ’s NOP NOP NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 NOP NOP CAS latency = 3 tCK3, DQ’s DOUT B3 4.1 Read to Write Interval (Burst Length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Minimum delay between the Read and Write Commands = 4+1 = 5 cycles tDQW DQM tDQZ COMMAND NOP READ A NOP NOP NOP DQ’s Must be Hi-Z before the Write Command 23 WRITE B DIN B0 DOUT A0 : “H” or “L” Semiconductor Group NOP NOP NOP DIN B1 DIN B2 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 4 2. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tDQW DQM tDQZ 1 Clk Interval NOP COMMAND NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP DIN A1 DIN A2 DIN A3 Must be Hi-Z before the Write Command CAS latency = 2 DIN A0 tCK2, DQ’s : “H” or “L” 4. 3. Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP CLK tDQW DQM tDQZ COMMAND NOP CAS latency = 2 tCK2, DQ’s READ A NOP NOP READ A WRITE B Must be Hi-Z before the Write Command DOUT A0 CAS latency = 3 tCK3, DQ’s : “H” or “L” Semiconductor Group NOP 24 DOUT A1 DIN B0 DIN B1 DIN B2 DOUT A0 DIN B0 DIN B1 DIN B2 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP DQ’s WRITE A DIN A0 NOP NOP NOP DIN A1 DIN A2 DIN A3 The first data element and the Write are registered on the same clock edge. NOP NOP NOP NOP don’t care Extra data is ignored after termination of a Burst. 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 WRITE A WRITE B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 1 Clk Interval DQ’s Semiconductor Group DIN A0 DIN B0 25 NOP NOP NOP HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3 T0 T1 T2 WRITE A READ B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP CAS latency = 2 tCK2, DQ’s CAS latency = 3 tCK3, DQ’s DIN A0 don’t care DIN A0 don’t care NOP NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care Input data for the Write is ignored. NOP Input data must be removed from the DQ’s at least one clock cycle before the Read data appears on the outputs to avoid data contention. 7.1 Burst Write with Auto-Precharge Burst Length = 2, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND BANK A ACTIVE NOP NOP WRITE A Auto-Precharge NOP NOP DIN A0 DIN A1 NOP NOP tWR DQ’s NOP tRP * Begin Autoprecharge Bank can be reactivated after trp Semiconductor Group DOUT B3 26 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 7.2 Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A with AP CAS latency = 2 tCK2, DQ’s CAS latency = 3 tCK3, DQ’s NOP NOP DOUT A0 NOP NOP NOP DOUT A1 DOUT A0 * DOUT A2 * DOUT A1 NOP NOP NOP tRP DOUT A3 tRP DOUT A2 DOUT A3 tRP * Begin Autoprecharge Bank can be reactivated after trp Semiconductor Group 27 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 8.1 Termination of a Full Page Burst Read Operation (CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, DQ’s NOP NOP Burst Stop NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 CAS latency = 3 tCK3, DQ’s NOP NOP NOP DOUT A3 The burst ends after a delay equal to the CAS latency. 8.2 Termination of a Full Page Burst Write Operation (CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP CAS latency = 2,3,4 DQ’s WRITE A DIN A0 NOP NOP DIN A1 DIN A2 Burst Stop NOP don’t care Input data for the Write is masked. Semiconductor Group 28 NOP NOP NOP \ Semiconductor Group 9.1 AC Parameters for Write Timing T0 T1 T2 T3 T4 Burst Length = 4, CAS Latency = 2 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCH tCK2 tCL tCS CKE tCKS Begin Auto Precharge Bank A tCH Begin Auto Precharge Bank B tCKH CS RAS CAS 29 WE BS tAH AP RAx RBx RAy RBy RAz RBy tAS Addr RAx CAx RBx CBx RAy RAy DQM tRCD tDS tRC DQ Hi-Z Ax0 Ax1 Ax2 tWR tDH Ax3 Bx0 Bx1 Bx2 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B Bx3 Ay0 Write Command Bank A Ay1 Ay2 tRP tRRD Ay3 Precharge Command Bank A Activate Command Bank A Activate Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM RAz \ Semiconductor Group 9.2 AC Parameters for Read Timing T0 T1 Burst Length = 2, CAS Latency = 2 T2 T3 T4 T5 T7 T6 T8 T9 T10 T12 T11 T13 CLK tCK2 tCH tCL tCS CKE Begin Auto Precharge Bank A tCH tCKS Begin Auto Precharge Bank B tCKH CS RAS CAS 30 WE BS tAH AP RAx RBx RAy Addr RAx CAx RBx RBx RAy tRRD tRAS DQM tRC tAC2 tRCD DQ tLZ Hi-Z tAC2 tOH Ax0 Activate Command Bank A Read with Auto Precharge Command Bank A Activate Command Bank B tRP tHZ Ax1 Read with Auto Precharge Command Bank B tHZ Bx0 Precharge Command Bank A Bx1 Activate Command Bank A HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM tAS \ Semiconductor Group 10. Mode Register Set T0 T1 CAS Latency = 2 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE tRSC CS RAS CAS 31 WE BS0,BS1 A10,A11 A0-A9 Precharge Command All Banks Mode Register Set Command Any Command HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Address Key \ Semiconductor Group 11. Power on Sequence and Auto Refresh (CBR) T0 T T T T T T T T T T1 T T T T T T T T T T T T CLK High level is required CKE 2 Clock min. Minimum of 8 Refresh Cycles are required CS RAS CAS 32 WE BS AP Addr DQM tRP DQ tRC Hi-Z Precharge 1st Auto Refresh Command Command All Banks Inputs must be stable for 200µs 8th Auto Refresh Command Mode Register Set Command Any Command HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Address Key \ Semiconductor Group 12.1 Clock Suspension During Burst Read (Using CKE) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 4, CAS Latency = 2 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS 33 WE BS RAx Addr RAx CAx tCSL DQM tCSL tCSL tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 12.2 Clock Suspension During Burst Read (Using CKE) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 Burst Length = 4, CAS Latency = 3 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS RAS CAS 34 WE BS RAx Addr RAx CAx tCSL DQM tCSL tCSL tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 12.3 Clock Suspension During Burst Write (Using CKE) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 4, CAS Latency = 2 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS 35 WE BS RAx Addr RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 12.4 Clock Suspension During Burst Write (Using CKE) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 4, CAS Latency = 3 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS RAS CAS 36 WE BS RAx Addr RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 13. Power Down Mode and Clock Suspend T0 T1 T2 T3 T4 T5 T6 Burst Length = 4, CAS Latency = 2 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 tCKS tCKS CKE CS RAS CAS 37 WE BS RAx Addr RAx CAx DQM tHZ DQ Hi-Z Ax0 Activate Command Bank A ACTIVE STANDBY Clock Suspend Mode Entry Ax1 Ax2 Ax3 PRECHARGE STANDBY Read Command Bank A Clock Suspend Mode Exit Clock Mask Start Clock Mask End Precharge Command Bank A Power Down Mode Entry Power Down Mode Exit Any Command HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 14. Self Refresh (Entry and Exit) T0 T1 T2 T3 T4 T5 T T T T T T T T T T T T T T T T T CLK tCKS CKE tCKS CS RAS CAS 38 WE BS AP tSREX DQM DQ tRC Hi-Z All Banks must be idle Self Refresh Entry Any Command Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Addr \ Semiconductor Group 15. Auto Refresh (CBR) T0 T1 T2 Burst Length = 4, CAS Latency = 2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS 39 WE BS RAx Addr RAx tRP DQM DQ tRC CAx tRC (Minimum Interval) Hi-Z Ax0 Precharge Command All Banks Auto Refresh Command Auto Refresh Command Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 16.1 Random Column Read (Page within same Bank) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 Burst Length = 4, CAS Latency = 2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS 40 WE BS RAw Addr RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Ax0 Read Command Bank A Ax1 Ay0 Ay1 Ay2 Precharge Command Bank A Ay3 Az0 Activate Command Bank A Read Command Bank A Az1 Az2 Az3 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 16.2 Random Column Read (Page within same Bank) T0 T1 T2 T3 T4 T5 T6 T7 T8 Burst Length = 4, CAS Latency = 3 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS RAS CAS 41 WE BS RAw Addr RAw RAz CAw CAx CAy RAz CAz Activate Command Bank A Read Command Bank A DQM DQ Hi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Read Command Bank A Aw2 Aw3 Read Command Bank A Ax0 Ax1 Ay0 Ay1 Ay2 Precharge Command Bank A Ay3 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 17.1 Random Column Write (Page within same Bank) T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 Burst Length = 4, CAS Latency = 2 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS RAS CAS 42 WE BS RBz Addr RBz RAw RBz CBz CBx CBy RAw RBz CAx CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B DBz0 DBz1 DBz2 DBz3 Precharge Command Bank B Activate Command Bank B Write Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP Semiconductor Group 17.2 Random Column Write (Page within same Bank) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Burst Length = 4, CAS Latency = 3 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS RAS CAS 43 WE BS RBz Addr RBz RBz CBz CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B DBz0 DBz1 Precharge Command Bank B Activate Command Bank B Write Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP Semiconductor Group 18.1 Random Row Read (Interleaving Banks) with Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 8, CAS Latency = 2 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS RAS CAS 44 WE BS RBx Addr RBx CBx Hi-Z Activate Command Bank B RBy CAx RAx tRP Bx0 Read Command Bank B CBy RBy tAC2 tRCD DQM DQ RAx Bx1 Bx2 Bx3 Bx4 Activate Command Bank A Bx5 Bx6 Bx7 Precharge Command Bank B Read Command Bank A Ax0 Ax1 Activate Command Bank B Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Read Command Bank B By0 By1 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP Semiconductor Group 18.2 Random Row Read (Interleaving Banks) with Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 8, CAS Latency = 3 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS RAS CAS 45 WE BS RBx Addr RBx CBx Hi-Z Activate Command Bank B RBy RAx CAx tRP Bx0 Read Command Bank B CBy RBy tAC3 tRCD DQM DQ RAx Bx1 Bx2 Activate Command Bank A Bx3 Bx4 Bx5 Read Command Bank A Bx6 Bx7 Precharge Command Bank B Ax0 Ax1 Ax2 Activate Command Bank B Ax3 Ax4 Ax5 Ax6 Read Command Bank B Ax7 By0 Precharge Command Bank A HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP Semiconductor Group 19.1 Random Row Write (Interleaving Banks) with Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Burst Length = 8, CAS Latency = 2 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS RAS CAS 46 WE BS RAx Addr RAx RBx CAy CAX RBx tRCD Hi-Z Activate Command Bank A CBx RAy tWR DQM DQ RAy CAy tWR tRP DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP Semiconductor Group 19.2 Random Row Write (Interleaving Banks) with Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Burst Length = 8, CAS Latency = 3 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS RAS CAS 47 WE BS RAx Addr RAx RBx CAX RBx tRCD RAy CBx RAy tWR tRP CAy tWR DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 20.1 Full Page Read Cycle T0 T1 T2 Burst Length = Full Page, CAS Latency = 2 T3 T4 T5 T6 T T T T T T T T T T T T T T T T CLK tCK2 CKE High CS RAS CAS 48 WE BS RAx Addr RAx RBx CAx RBy CBx RBx RBy tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Ax+1 Ax+2 Activate Command Bank B Ax-2 Ax-1 Ax Ax+1 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval. Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Burst Stop Command Activate Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 20.2 Full Page Read Cycle T0 T1 T2 Burst Length = Full Page, CAS Latency = 3 T3 T4 T5 T6 T7 T8 T T T T T T T T T T T T T T CLK tCK3 CKE High CS RAS CAS 49 WE BS RAx Addr RAx RBx CAx RBy CBx RBx RBy tRRD DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Activate Command Bank B Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Full Page burst operation does not terminate when the length is Precharge satisfied; the burst counter Command increments and continues Bank B The burst counter wraps bursting beginning with from the highest order the starting address. page address back to zero Burst Stop during this time interval. Command Read Command Bank B Activate Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 21.1 Full Page Write Cycle T0 T1 T2 Burst Length = Full Page, CAS Latency = 2 T3 T4 T5 T T T T T T T T T T T T T T T T T CLK tCK2 CKE High CS RAS CAS 50 WE BS RAx Addr RAx RBx CAx RBx RBy CBx RBy DQM DQ Hi-Z Activate Command Bank A DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Write Command Bank A Activate Write Command Precharge Command Data is ignored. Bank B Command Bank B Bank B The burst counter wraps Full Page burst operation does not from the highest order terminate when the burst length is satisfied; page address back to zero Burst Stop the burst counter increments and continues during this time interval. bursting beginning with the starting address. Command Activate Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP \ Semiconductor Group 21.2 Full Page Write Cycle T0 T1 T2 Burst Length = Full Page, CAS Latency = 3 T3 T4 T5 T6 T T T T T T T T T T T T T T T T CLK tCK3 CKE High CS RAS CAS 51 WE BS RAx Addr RAx RBx CAx RBx RBy CBx RBy DQM DQ Hi-Z Activate Command Bank A Data is ignored. DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Write Command Bank A Activate Write Command Precharge Command Full Page burst operation does not Bank B Command terminate when the length is Bank B Bank B satisfied; the burst counter The burst counter wraps increments and continues from the highest order bursting beginning with page address back to zero Burst Stop the starting address. during this time interval. Command Activate Command Bank B HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 \ Semiconductor Group Burst Length = 8 or Full Page, CAS Latency = 2 22.1 Precharge Termination of a Burst T22 CLK tCK2 CKE High CS RAS CAS 52 WE BS RAx Addr RAx RAy CAx RAy RAz CAy RAz CAz tRP tRP tRP DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. Ay0 Activate Command Bank A Read Command Bank A Ay1 Precharge Command Bank A Ay2 Activate Command Bank A Az0 Read Command Bank A Az1 Precharge Command Bank A Precharge Termination of a Read Burst. Az2 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM AP HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM Change List: Rev. 10.98 Semiconductor Group ICC6 for L-version changed from 400 µA to 500 µA 20 10.98