MOSEL V54C365164VD

MOSEL VITELIC
V54C365164VD(L)
HIGH PERFORMANCE 225/200/166/143 MHz
3.3 VOLT 4M X 16 SYNCHRONOUS DRAM
4 BANKS X 1Mbit X 16
PRELIMINARY
45
5
6
7
System Frequency (fCK)
225 MHz
200 MHz
166 MHz
143 MHz
Clock Cycle Time (tCK3)
4.5 ns
5 ns
6 ns
7 ns
Clock Access Time (tAC3) CAS Latency = 3
4.5 ns
5 ns
5.4 ns
5.4 ns
Clock Access Time (tAC2) CAS Latency = 2
4.5 ns
5 ns
5.5 ns
5.5 ns
Clock Access Time (tAC1) CAS Latency = 1
12 ns
12 ns
12 ns
12 ns
Features
Description
■ 4 banks x 1Mbit x 16 organization
■ High speed data transfer rates up to 225 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for byte Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Suspend Mode and Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 54 Pin 400 mil TSOP-II
■ LVTTL Interface
■ Single +3.3 V ±0.3 V Power Supply
The V54C365164VD(L) is a four bank Synchronous DRAM organized as 4 banks x 1Mbit x 16. The
V54C365164VD(L) achieves high speed data transfer rates up to 225 MHz by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
225 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
T
45
5
6
7
Std.
L
Temperature
Mark
0°C to 70°C
•
•
•
•
•
•
•
Blank
V54C365164VD(L) Rev. 1.3 September 2001
Access Time (ns)
1
Power
MOSEL VITELIC
Description
TSOP-II
V54C365164VD(L)
Pkg.
Pin Count
T
54
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
VCCQ
I/O2
I/O3
VSSQ
I/O4
I/O5
VCCQ
I/O6
I/O7
VSSQ
I/O8
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Pin Names
VSS
I/O16
VSSQ
I/O15
I/O14
VCCQ
I/O13
I/O12
VSSQ
I/O11
I/O10
VCCQ
I/O9
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
365164VA 01
V54C365164VD(L) Rev. 1.3 September 2001
2
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A0–A11
Address Inputs
BA0, BA1
Bank Select
I/O1–I/O16
Data Input/Output
LDQM, UDQM
Data Mask
VCC
Power (+3.3V)
VSS
Ground
VCCQ
Power for I/O’s (+3.3V)
VSSQ
Ground for I/O’s
NC
Not connected
MOSEL VITELIC
V54C365164VD(L)
56 Ball Grid Array (or BGA)
WBGA SDRAM (X4/X8/X16) 56 PINS ASSIGNMENT (Top View)
X4
X8
NC
VSS
DQ7
VSS
DQ15
VSS
NC
VSSQ
NC
VSSQ
DQ14
VDDQ
DQ3
VDDQ
DQ6
NC
NC
DQ5
NC
VSSQ
VDDQ
X16
VDD
NC
VDD
NC
VDD
NC
VSSQ
VDDQ
DQ0
VDDQ
DQ0
VDDQ
NC
VDDQ
DQ13
DQ2
DQ1
DQ1
NC
DQ1
NC
NC
DQ11
DQ12
DQ3
VSSQ
NC
VSSQ
NC
VSSQ
NC
VSSQ
DQ10
VSSQ
VDDQ
DQ4
VDDQ
DQ2
VDDQ
NC
DQ2
VDDQ
DQ4
VDDQ
DQ9
DQ6
DQ5
DQ3
NC
DQ1
NC
VSS
NC
VSS
NC
VSS
DQ8
DQ7
VSSQ
NC
VSSQ
NC
VSSQ
DQM
NC
DQM
NC
UDQM
NC
LDQM
VDD
NC
VDD
NC
VDD
CKE
CLK
CKE
CLK
CKE
CLK
CAS
WE
CAS
WE
CAS
WE
A11
–
A11
–
A11
–
CS
RAS
CS
RAS
CS
RAS
A8
A9
A8
A9
A8
A9
BA1
BA0
BA1
BA0
BA1
BA0
A6
A7
A6
A7
A6
A7
A0
A10
A0
A10
A0
A10
A4
A5
A4
A5
A4
A5
A2
A1
A2
A1
A2
A1
NC
VSS
NC
VSS
NC
VSS
VDD
A3
VDD
A3
VDD
A3
V54C365164VD(L) Rev. 1.3 September 2001
3
MOSEL VITELIC
V54C365164VD(L)
Bottom View (FROM SOLDER BALL SIDE)
X4
X8
NC
VDD
NC
VDD
NC
VDD
NC
VDDQ
DQ0
VDDQ
DQ0
VDDQ
NC
DQ0
NC
DQ1
DQ1
VSSQ
NC
VSSQ
NC
NC
VDDQ
DQ3
NC
DQ1
VSSQ
X16
VSS
DQ7
VSS
NC
VSSQ DQ14
VSSQ
NC
VSSQ
NC
DQ2
DQ13 VDDQ
DQ6
VDDQ
DQ3
VDDQ
VSSQ
DQ3
DQ12 DQ11
NC
DQS
NC
NC
VDDQ
DQ4
VDDO
VSSQ DQ10
VSSQ
NC
VSSQ
NC
NC
DQ3
DQ5
DQ6
DQ9
VDDQ
DQ4
VDDQ
DQ2
VDDQ
NC
VSSQ
NC
VSSQ
DQ7
DQ8
VSS
NC
VSS
NC
VSS
VDD
NC
VDD
NC
VDD
LDQM
NC
UDQM
NC
DQM
NC
DQM
WE
CAS
WE
CAS
WE
CAS
CLK
CKE
CLK
CKS
CLK
CKE
RAS
CS
RAS
CS
RAS
CS
–
A11
–
A11
–
A11
BA0
BA1
BA0
BA1
BA0
BA1
A9
A8
A9
A8
A9
A8
A10
A0
A10
A0
A10
A0
A7
A6
A7
A6
A7
A6
A1
A2
A1
A2
A1
A2
A5
A4
A5
A4
A5
A4
A3
VDD
A3
VDD
A3
VDD
VSS
NC
VSS
NC
VSS
NC
V54C365164VD(L) Rev. 1.3 September 2001
4
VSS
DQ15
MOSEL VITELIC
V54C365164VD(L)
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Max. Unit
Symbol
Parameter
C I1
Input Capacitance (A0 to A11)
5
pF
C I2
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
5
pF
C IO
Output Capacitance (I/O)
6.5
pF
C CLK
Input Capacitance (CLK)
4
pF
*Note:Capacitance is sampled and not 100% tested.
Block Diagram
Row Addresses
Column Addresses
A0 - A7, AP, BA0, BA1
Row address
buffer
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Memory array
Memory array
Memory array
Memory array
Bank 0
4096 x 256
x 16 bit
Bank 1
4096 x 256
x 16 bit
Input buffer
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Row decoder
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column address
counter
A0 - A11, BA0, BA1
Bank 2
4096 x 256
x 16 bit
Output buffer
Bank 3
4096 x 256
x 16 bit
Control logic & timing generator
V54C365164VD(L) Rev. 1.3 September 2001
5
UDQM
LDQM
WE
CAS
CS
RAS
CKE
CLK
I/O1-I/O16
MOSEL VITELIC
V54C365164VD(L)
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
4M x 16 SDRAM CA0–CA7 (Page Length = 256 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
LDQM and UDQM controls the lower and upper bytes in a x16 SDRAMs.
VCC, VSS Supply
VCCQ
VSSQ
Supply
Power and ground for the input buffers and the core logic.
—
V54C365164VD(L) Rev. 1.3 September 2001
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
6
MOSEL VITELIC
V54C365164VD(L)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Device
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Idle3
H
X
L
L
H
H
X
V
V
V
Active3
H
X
L
H
L
H
X
V
L
V
Active
3
H
X
L
H
L
H
X
V
H
V
Write
Active
3
H
X
L
H
L
L
X
V
L
V
Write with Autoprecharge
Active3
H
X
L
H
L
L
X
V
H
V
Row Precharge
Any
H
X
L
L
H
L
X
X
L
V
Precharge All
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set
Idle
H
X
L
L
L
L
X
V
V
V
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
Idle
H
L
L
L
L
H
X
X
X
X
Idle
(Self Refr.)
H
X
X
X
L
H
L
H
H
X
X
X
X
X
Idle
Active5
H
X
X
X
H
L
L
H
H
X
X
X
X
X
Any
(Power
Down)
H
X
X
X
L
H
L
H
H
L
X
X
X
X
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
Operation
Row Activate
Read
Read w/Autoprecharge
Self Refresh Exit
Power Down Entry
Power Down Exit
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock
suspend mode.
V54C365164VD(L) Rev. 1.3 September 2001
7
MOSEL VITELIC
V54C365164VD(L)
mode set command. All banks must be in precharged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table.
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 225 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial
data accesses are done within this boundary. The
first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are
generated automatically by the programmed burst
length and its sequence. For example, in a burst
length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3,
0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using
the sequential burst type and page length is a function of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate command after the initial power up. Any content of the
mode register can be altered by re-executing the
V54C365164VD(L) Rev. 1.3 September 2001
8
MOSEL VITELIC
V54C365164VD(L)
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 A11 A10 A9
A8
Operation Mode
A7
A6
A5
A4
A3
A2
CAS Latency
BT
Burst Length
0
0
0
0
Mode Register
Mode
A3
Type
0
Burst Read/Burst
Write
0
Sequential
1
Interleave
0
Burst Read/Single
Write
BA1 BA0 A11 A10 A9 A8 A7
0
Address Bus (Ax)
A0
Burst Type
Operation Mode
0
A1
0
0
0
1
0
0
Burst Length
CAS Latency
A6
A5
A4
Latency
0
0
0
Reserve
0
0
0
0
1
1
1
0
1
Length
A2
A1
A0
Sequential
Interleave
0
0
0
1
1
2
0
0
1
2
2
3
0
1
0
4
4
1
1
8
8
1
1
0
0
Reserve
0
1
0
1
Reserve
1
0
0
Reserve
Reserve
1
1
0
Reserve
1
0
1
Reserve
Reserve
1
1
1
Reserve
1
1
0
Reserve
Reserve
1
1
1
Full Page
Reserve
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two or more
banks are activated
sequentially, interleaved bank read or write
operations are possible. With the programmed burst
length, alternate access and precharge operations
on two or more banks can realize fast serial data
access modes among many different pages. Once
two or more banks are activated, column to column
interleave operation can be done between different
pages.
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies
V54C365164VD(L) Rev. 1.3 September 2001
9
MOSEL VITELIC
V54C365164VD(L)
Burst Length and Sequence:
Burst Starting Address
Length
(A2 A1 A0)
2
xx0
xx1
4
x00
x01
x10
x11
8
000
001
010
011
100
101
110
111
Full
Page
nnn
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
0, 1
1, 0
0,
1,
2,
3,
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
0, 1
1, 0
1,
2,
3,
0,
2,
3,
0,
1,
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
0,
1,
2,
3,
3
0
1
2
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
Cn, Cn+1, Cn+2,.....
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
1,
0,
3,
2,
2,
3,
0,
1,
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
3
2
1
0
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
not supported
a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any refresh mode. An on-chip address counter increments
the word and the bank addresses and no bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay
is required prior to any access command.
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for
mode entry and exit.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ ). It also provides
V54C365164VD(L) Rev. 1.3 September 2001
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
10
MOSEL VITELIC
V54C365164VD(L)
operation. If CA10 is high when a Read Command is
issued, the Read with Auto-Precharge function is
initiated. The SDRAM automatically enters the precharge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3
and three clocks for CAS latencies 4. If CAS10 is
high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time)
after the last data in.
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These
methods include using another Read or Write Command to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation but
leave the bank open for future Read or Write Commands to the same page of the active bank. When
interrupting a burst with another Read or Write Command care must be taken to avoid I/O contention.
The Burst Stop Command, however, has the fewest
restrictions making it the easiest method to use
when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual data
from the burst write cycle will be ignored. Data that
is presented on the I/O pins before the Burst Stop
Command is registered will be written to the
memory.
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list.
The precharge command can be imposed one clock
before the last data out for CAS latency = 2, two
clocks before the last data out for CAS latency = 3
and three clocks before the last data out for CAS latency= 4. Writes require a time delay twr from the
last data out to apply the precharge command.
Bank Selection by Address Bits:
A10
BA0 BA1
0
0
0
Bank 0
0
0
1
Bank 1
0
1
0
Bank 2
0
1
1
Bank 3
1
X
X
all Banks
V54C365164VD(L) Rev. 1.3 September 2001
11
MOSEL VITELIC
V54C365164VD(L)
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 °C
Storage temperature range ............... -55 to 150 °C
Input/output voltage .................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ............................................. 1 W
Data out current (short circuit) ...................... 50 mA
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Recommended Operation and Characteristics for LV-TTL
TA = 0 to 70 °C; VSS = 0 V; VCC,VCCQ = 3.3 V ± 0.3 V
Limit Values
Parameter
Symbol
min.
max.
Unit
Notes
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 2.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < V IN < 3.6 V, all other inputs = 0 V)
II(L)
–5
5
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC )
IO(L)
–5
5
µA
Note:
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
V54C365164VD(L) Rev. 1.3 September 2001
12
MOSEL VITELIC
V54C365164VD(L)
Operating Currents (TA = 0 to 70°C, VCC = 3.3V ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max.
Symbol
Parameter & Test Condition
-45
-5
-6
-7
Unit
Note
188
180
165
150
mA
7
ICC1
Operating Current
tRC = tRCMIN., tRC = tCKMIN.
Active-precharge command
cycling,
without Burst Operation
1 bank operation
ICC2P
Precharge Standby Current
in Power Down Mode
CS =VIH, CKE≤ VIL(max)
tCK = min.
2
2
2
2
mA
7
tCK = Infinity
1
1
1
1
mA
7
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
tCK = min.
70
65
55
45
mA
tCK = Infinity
5
5
5
5
mA
No Operating Current
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE ≥ VIH(MIN.)
80
75
65
55
mA
CKE < VIL(MAX.)
(Power down mode)
8
8
8
8
mA
ICC2PS
ICC2N
ICC2NS
ICC3
ICC3P
ICC4
Burst Operating Current
tCK = min
Read/Write command cycling
145
140
130
120
mA
7,8
ICC5
Auto Refresh Current
tCK = min
Auto Refresh command cycling
180
175
165
150
mA
7
ICC6
Self Refresh Current
Self Refresh Mode, CKE<0.2V
1
1
1
1
mA
500
500
500
500
µA
L-version
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
8. These parameter depend on output loading. Specified values are obtained with output open.
V54C365164VD(L) Rev. 1.3 September 2001
13
MOSEL VITELIC
V54C365164VD(L)
AC Characteristics 1,2, 3
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-45
#
Symbol
Parameter
-5
-6
-7
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock and Clock Enable
1
2
3
tCK
tCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
4.5
10
12
–
–
–
5
10
12
–
–
–
6
10
12
–
–
–
7
10
12
–
–
–
s
ns
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
225
100
83
–
–
–
200
100
83
–
–
–
166
100
83
–
–
–
143
100
83
MHz
MHz
MHz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
4.5
4.5
11
–
_
–
5
5
11
–
_
–
5.4
5.5
11
–
_
–
5.4
5.5
11
ns
ns
ns
2, 4
4
tCH
Clock High Pulse Width
2.5
–
2.5
–
2.5
–
2.5
–
ns
5
tCL
Clock Low Pulse Width
2.5
–
2.5
–
2.5
–
2.5
–
ns
6
tT
Transition Tim
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.2
ns
Setup and Hold Times
7
tIS
Input Setup Time
1.5
–
1.5
–
1.5
–
1.5
–
ns
5
8
tIH
Input Hold Time
0.8
–
0.8
–
0.8
–
0.8
–
ns
5
9
tCKS
CKE Setup Time
1.5
–
1.5
–
1.5
–
1.5
–
ns
5
10
tCKH
CKE Hold Time
0.8
–
0.8
–
0.8
–
0.8
–
ns
5
11
tRSC
Mode Register Set-up Time
9
–
10
–
12
–
14
–
ns
12
tSB
Power Down Mode Entry Time
0
45
0
5
0
6
0
7
ns
Row to Column Delay Time
14
–
15
–
20
–
20
–
ns
6
Common Parameters
13
tRCD
14
tRP
Row Precharge Time
14
–
15
–
20
–
20
–
ns
6
15
tRAS
Row Active Time
38
100K
40
100K
40
100K
42
100K
ns
6
16
tRC
Row Cycle Time
60
–
60
–
60
–
60
–
ns
6
17
tRRD
Activate(a) to Activate(b) Command
Period
9
–
10
–
12
–
14
–
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
1
–
1
–
1
–
CLK
Refresh Period (4096 cycles)
–
64
—
64
—
64
—
64
ms
Self Refresh Exit Time
10
–
10
—
10
—
10
—
ns
Refresh Cycle
19
tREF
20
tSREX
V54C365164VD(L) Rev. 1.3 September 2001
14
MOSEL VITELIC
V54C365164VD(L)
AC Characteristics (Cont’d)
Limit Values
-45
#
Symbol
Parameter
-5
-6
-7
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Read Cycle
21
tOH
Data Out Hold Time
2.5
-1
2.5
–
2.5
–
2.7
–
ns
22
tLZ
23
tHZ
24
tDQZ
2
Data Out to Low Impedance Time
1
–
1
–
1
–
1
–
ns
Data Out to High Impedance Time
–
4.5
–
5
–
5.4
–
5.4
ns
DQM Data Out Disable Latency
–
2
–
2
–
2
–
2
CLK
Write Recovery Time
2
–
2
–
2
–
2
–
CLK
DQM Write Mask Latency
0
1
0
1
0
–
0
–
CLK
7
Write Cycle
25
tWR
26
tDQW
Frequency vs. AC Parameter Relationship Table
-45 / -5 / -6 / -7
Frequency
CAS
Latency
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
Unit
83 MHz (12 ns)
1
5
4
2
2
2
1
1
1
CLK
V54C365164VD(L) Rev. 1.3 September 2001
15
MOSEL VITELIC
V54C365164VD(L)
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have VIL = 0.8V and V IH = 2.0V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown
in Figure 1.
tCK
VIH
CLK
VIL
+ 1.4 V
tT
tCS
tCH
50 Ohm
1.4V
COMMAND
Z=50 Ohm
tAC
tAC
tLZ
I/O
50 pF
tOH
1.4V
OUTPUT
tHZ
Figure 1.
4. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
V54C365164VD(L) Rev. 1.3 September 2001
16
MOSEL VITELIC
V54C365164VD(L)
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Full Page Burst Write Operation
8.2 Termination of a Full Page Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Clock Suspension (using CKE)
12.1 Clock Suspension During Burst Read CAS Latency = 2
12. 2 Clock Suspension During Burst Read CAS Latency = 3
12. 3 Clock Suspension During Burst Write CAS Latency = 2
12. 4 Clock Suspension During Burst Write CAS Latency = 3
13. Power Down Mode and Clock Suspend
14. Self Refresh (Entry and Exit)
15. Auto Refresh (CBR)
V54C365164VD(L) Rev. 1.3 September 2001
17
MOSEL VITELIC
V54C365164VD(L)
Timing Diagrams (Cont’d)
16. Random Column Read ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Column Write ( Page within same Bank)
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Read ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Random Row Write ( Interleaving Banks) with Precharge
19.1 CAS Latency = 2
19.2 CAS Latency = 3
20. Full Page Read Cycle
20.1 CAS Latency = 2
20.2 CAS Latency = 3
21. Full Page Write Cycle
21.1 CAS Latency = 2
21.2 CAS Latency = 3
22. Precharge Termination of a Burst
22.1 CAS Latency = 2
22.2 CAS Latency = 3
V54C365164VD(L) Rev. 1.3 September 2001
18
MOSEL VITELIC
V54C365164VD(L)
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
..........
ADDRESS
Bank A
Col. Addr.
Bank A
Row Addr.
Bank A
Row Addr.
Bank B
Row Addr.
..........
tRCD
COMMAND
Bank A
Activate
tRRD
NOP
Write A
with Auto
Precharge
NOP
Bank B
Activate
..........
Bank A
Activate
NOP
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3, 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
NOP
DOUT A0
NOP
NOP
DOUT A1
DOUT A2
DOUT A0
NOP
NOP
NOP
DOUT A3
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
CAS latency = 4
tCK4, I/O’s
V54C365164VD(L) Rev. 1.3 September 2001
19
DOUT A3
NOP
MOSEL VITELIC
V54C365164VD(L)
3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3, 4)
T0
T1
READ A
READ B
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
NOP
DOUT A0
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
T4
T5
T6
NOP
CAS latency = 4
tCK4, I/O’s
DOUT B3
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
I/O’s
NOP
NOP
NOP
WRITE B
DIN B0
DOUT A0
Must be Hi-Z before
the Write Command
: “H” or “L”
V54C365164VD(L) Rev. 1.3 September 2001
NOP
20
NOP
NOP
DIN B1
DIN B2
MOSEL VITELIC
V54C365164VD(L)
4.2 Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
COMMAND
NOP
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
Must be Hi-Z before
the Write Command
CAS latency = 2
DIN A0
tCK2, I/O’s
: “H” or “L”
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3, 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
DIN B0
DIN B1
DIN B2
DIN B0
DIN B1
DIN B2
DIN B0
DIN B1
DIN B2
CLK
tDQW
DQM
tDQZ
COMMAND
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
CAS latency = 2
tCK1, I/O’s
DOUT A0
DOUT A1
Must be Hi-Z before
the Write Command
CAS latency = 3
DOUT A0
tCK2, I/O’s
CAS latency = 4
tCK3, I/O’s
: “H” or “L”
V54C365164VD(L) Rev. 1.3 September 2001
21
MOSEL VITELIC
V54C365164VD(L)
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3, or 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
I/O’s
WRITE A
DIN A0
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
NOP
NOP
NOP
NOP
don’t care
Extra data is ignored after
termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3, or 4)
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
1 Clk Interval
I/O’s
DIN A0
V54C365164VD(L) Rev. 1.3 September 2001
DIN B0
22
NOP
NOP
NOP
MOSEL VITELIC
V54C365164VD(L)
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3, 4)
T0
T1
T2
WRITE A
READ B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
CAS latency = 4
tCK4, I/O’s
NOP
NOP
DIN A0
don’t care
DIN A0
don’t care
don’t care
DIN A0
don’t care
don’t care
DOUT B0
NOP
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
don’t care
Input data for the Write is ignored.
NOP
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3, 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
BANK A
ACTIVE
NOP
NOP
WRITE A
NOP
Auto-Precharge
NOP
tWR
CAS latency = 2
I/O’s
DIN A0
DIN A1
tWR
CAS latency = 3
I/O’s
DIN A0
DIN A1
tWR
NOP
tRP
*
tRP
*
tRP
CAS latency = 4
I/O’s
DIN A0
DIN A1
NOP
*
*
Begin Autoprecharge
Bank can be reactivated after trp
V54C365164VD(L) Rev. 1.3 September 2001
23
NOP
MOSEL VITELIC
V54C365164VD(L)
7.2 Burst Read with Auto-Precharge
Burst Length = 4, CAS latency = 2, 3, 4)
T0
T1
T2
WRITE A
READ B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
CAS latency = 2
tCK2, I/O’s
CAS latency = 3
tCK3, I/O’s
DOUT A0
NOP
NOP
DOUT A1
DOUT A0
*
*
DOUT A1
DOUT A0
tCK4, I/O’s
NOP
NOP
NOP
tRP
DOUT A2
*
CAS latency = 4
NOP
DOUT A3
tRP
DOUT A2
DOUT A3
tRP
DOUT A1
DOUT A2
*
DOUT A3
Begin Autoprecharge
Bank can be reactivated after tRP
V54C365164VD(L) Rev. 1.3 September 2001
24
MOSEL VITELIC
V54C365164VD(L)
8.1 Termination of a Full Page Burst Read Operation
(CAS latency = 2, 3, 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, I/O’s
NOP
NOP
Burst
Stop
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
CAS latency = 3
tCK3, I/O’s
NOP
NOP
NOP
NOP
CAS latency = 4
tCK4, I/O’s
DOUT A3
The burst ends after a delay equal to the CAS latency.
8.2 Termination of a Full Page Burst Write Operation
(CAS latency = 2, 3, 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
NOP
NOP
DIN A1
DIN A2
Burst
Stop
NOP
CAS latency = 2,3,4
I/O’s
DIN A0
don’t care
Input data for the Write is masked.
V54C365164VD(L) Rev. 1.3 September 2001
25
NOP
NOP
NOP
T0
T1
T2
T3
T4
Burst Length = 4, CAS Latency = 2
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
CLK
tCH
tCK2
tCL
tCS
CKE
tCKS
Begin Auto Precharge
Bank A
tCH
Begin Auto Precharge
Bank B
tCKH
T21
T22
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
9.1 AC Parameters for Write Timing
CS
RAS
CAS
WE
26
BA
tAH
AP
RAx
RBx
RAy
RAz
RBy
RAz
RBy
tAS
Addr
CAx
RAx
RBx
CBx
RAy
RAy
DQM
tDS
tRC
I/O
Hi-Z
Ax0
Ax1
Ax2
tWR
tDH
Ax3
Bx0
Bx1
Bx2
Activate
Write with
Activate
Write with
Activate
Command Auto Precharge Command Auto Precharge Command
Bank A
Command
Bank B
Command
Bank A
Bank A
Bank B
Bx3
Ay0
Write
Command
Bank A
Ay1
Ay2
tRP
tRRD
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
V54C365164VD(L)
tRCD
T0
T1
Burst Length = 2, CAS Latency = 2
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
CLK
tCK2
tCH tCL
tCS
CKE
Begin Auto
Precharge
Bank B
tCH
tCKS
tCKH
T13
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
9.2 AC Parameters for Read Timing
CS
RAS
CAS
27
WE
BA
tAH
AP
RAx
RBx
RAy
tAS
Addr
RAx
CAx
RBx
RBx
RAy
tRRD
tRAS
tRC
tAC2
tRCD
I/O
tLZ
Hi-Z
tAC2
tOH
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
tRP
tHZ
Ax1
Read with
Auto Precharge
Command
tHZ
Bx0
Precharge
Command
Bank A
Bx1
Activate
Command
Bank A
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
2 Clock min.
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
10. Mode Register Set
CS
RAS
CAS
28
WE
BA
AP
Address Key
Addr
Mode Register
Set Command
Any
Command
V54C365164VD(L)
Precharge
Command
All Banks
T0
T
T
T
T
T
T
T
T
T
T1
T
T
T
T
T
T
T
T
T
CLK
High level
is required
CKE
2 Clock min.
Minimum of 2 Refresh Cycles are required
T
T
T
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
11. Power on Sequence and Auto Refresh (CBR)
CS
RAS
CAS
WE
29
BA
AP
Address Key
Addr
DQM
tRC
Hi-Z
Precharge 1st Auto Refresh
Command
Command
All Banks
Inputs must be
stable for 200µs
2nd Auto Refresh
Command
Mode Register
Set Command
Any
Command
V54C365164VD(L)
tRP
I/O
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Burst Length = 4, CAS Latency = 1
T11
T12
CLK
tCK1
CKE
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
12.1 Clock Suspension During Burst Read (Using CKE) (1 of 3)
CS
RAS
CAS
30
WE
BA
AP
RAx
Addr
RAx
CAx
tHZ
I/O
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Burst Length = 4, CAS Latency = 2
T11
T12
T13
CLK
tCK2
CKE
T14
T15
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
12.2 Clock Suspension During Burst Read (Using CKE) (2 of 3)
CS
RAS
CAS
31
WE
BA
AP
RAx
Addr
RAx
CAx
tHZ
I/O
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
Burst Length = 4, CAS Latency = 3
T12
T13
T14
T15
CLK
tCK3
CKE
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
)
V54C365164VD(L) Rev. 1.3 September 2001
12.3 Clock Suspension During Burst Read (Using CKE) (3 of 3)
CS
RAS
CAS
32
WE
BA
AP
RAx
Addr
RAx
CAx
tHZ
I/O
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Burst Length = 4, CAS Latency = 1
T11
T12
CLK
tCK1
CKE
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
12.4 Clock Suspension During Burst Write (Using CKE) (1 of 3)
CS
RAS
CAS
33
WE
BA
AP
RAx
Addr
RAx
CAx
I/O
Hi-Z
DAx0
Activate
Command
Bank A
DAx1
Clock Suspend
1 Cycle
Write
Command
Bank A
DAx2
Clock Suspend
2 Cycles
DAx3
Clock Suspend
3 Cycles
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
Burst Length = 4, CAS Latency = 2
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
tCKSP
tCKSP
CKE
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
13. Power Down Mode and Clock Suspend
CS
RAS
CAS
34
WE
BA
AP
RAx
Addr
RAx
CAx
tHZ
I/O
Hi-Z
Ax0
Activate
Command
Bank A
Clock Suspend
Mode Entry
Read
Command
Bank A
Clock Suspend
Mode Exit
Ax1
Clock Mask
Start
Ax2
Clock Mask
End
Ax3
Precharge
Command
Bank A
Power Down
Mode Entry
Power Down
Mode Exit
Any
Command
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T
T
T
T
T
T
T
T
CLK
t CKS
tSREX
CKE
T
T
T
T
T
T
T
T
T
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
14. Self Refresh (Entry and Exit)
CS
RAS
CAS
35
WE
BA
AP
Addr
tRC
I/O
Hi-Z
All Banks
must be idle
Self Refresh
Entry
Begin Self Refresh
Exit Command
Self Refresh Exit
Command issued
Self Refresh
Exit
V54C365164VD(L)
DQM
T0
T1
T2
Burst Length = 4, CAS Latency = 2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
T21
T22
CLK
tCK2
CKE
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
15. Auto Refresh (CBR)
CS
RAS
CAS
36
WE
BA
AP
RAx
Addr
RAx
I/O
tRC
tRC
(Minimum Interval)
Hi-Z
Ax0
Precharge
Command
All Banks
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
V54C365164VD(L)
tRP
DQM
CAx
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
Burst Length = 4, CAS Latency = 2
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
16.1 Random Column Read (Page within same Bank) (1 of 2)
CS
RAS
CAS
37
WE
BA
AP
RAw
Addr
RAw
RAz
CAw
CAx
CAy
RAz
CAz
I/O
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Read
Command
Bank A
Aw3
Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
Az0
Activate
Command
Bank A
Read
Command
Bank A
Az1
Az2
Az3
V54C365164VD(L)
DQM
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
16.2 Random Column Read (Page within same Bank) (2 of 2)
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
T22
CS
RAS
CAS
38
WE
BA
AP
RAw
Addr
RAw
RAz
CAw
CAx
CAy
CAz
Activate
Command
Bank A
Read
Command
Bank A
DQM
I/O
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Read
Command
Bank A
Aw2
Aw3
Read
Command
Bank A
Ax0
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
V54C365164VD(L)
RAz
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
Burst Length = 4, CAS Latency = 2
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
CLK
tCK2
CKE
T21
T22
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
17.1 Random Column Write (Page within same Bank) (1 of 2)
CS
RAS
CAS
39
WE
BA
AP
RBz
Addr
RBz
RAw
RBz
CBz
CBx
CBy
RAw
RBz
CAx
CBz
I/O
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1 DBz2 DBz3
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
V54C365164VD(L)
DQM
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
17.2 Random Column Write (Page within same Bank) (2 of 2)
CS
RAS
CAS
40
WE
BA
AP
RBz
Addr
RBz
RBz
CBz
CBx
CBy
RBz
CBz
I/O
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 2
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK2
CKE
High
T22
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
18.1 Random Row Read (Interleaving Banks) (1 of 2)
CS
RAS
CAS
WE
41
A11(BS)
A10
RBx
A0 - A9
RBx
CAx
tRP
Bx1
Bx2
Bx3
Bx4
Activate
Command
Bank A
Bx5
Bx6
Bx7
Precharge
Command
Bank B
Read
Command
Bank A
Ax0
Ax1
Activate
Command
Bank B
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
Read
Command
Bank B
By0
By1
V54C365164VD(L)
Bx0
Read
Command
Bank B
CBy
RBy
tAC2
Hi-Z
Activate
Command
Bank B
RBy
RAx
CBx
tRCD
DQM
I/O
RAx
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 3
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
High
T22
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
18. 2 Random Row Read (Interleaving Banks) (2 of 2)
CS
RAS
CAS
42
WE
A11(BS)
A10
RBx
A0 - A9
RBx
CAx
tRP
Bx1
Bx2
Activate
Command
Bank A
Bx3
Bx4
Bx5
Read
Command
Bank A
Bx6
Bx7
Precharge
Command
Bank B
Ax0
Ax1
Ax2
Activate
Command
Bank B
Ax3
Ax4
Ax5
Ax6
Read
Command
Bank B
Ax7
By0
Precharge
Command
Bank A
V54C365164VD(L)
Bx0
Read
Command
Bank B
CBy
RBy
tAC3
Hi-Z
Activate
Command
Bank B
RBy
RAx
CBx
tRCD
DQM
I/O
RAx
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 2
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
High
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
19.1 Random Row Write (Interleaving Banks) (1 of 2)
CS
RAS
CAS
43
WE
A11(BS)
A10
RAx
A0 - A9
RAx
CAy
CAX
RBx
tRCD
Activate
Command
Bank A
RAy
CAy
tDPL
tRP
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
V54C365164VD(L)
Hi-Z
CBx
tDPL
DQM
I/O
RAy
RBx
T0
T1
T2
T3
T4
T5
T6
T7
T8
Burst Length = 8, CAS Latency = 3
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
19.2 Random Row Write (Interleaving Banks) (2 of 2)
CS
RAS
CAS
44
WE
A11(BS)
A10
RAx
A0 - A9
RAx
RAy
RBx
CAX
RBx
tDPL
tRP
CAy
tDPL
DQM
I/O
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank B
V54C365164VD(L)
tRCD
RAy
CBx
T0
T1
T2
T3
Burst Length = Full Page, CAS Latency = 2
T4
T5
T6
T
T
T
T
T
T
T
T
T
T
T
T
T
CLK
tCK2
CKE
High
T
T
T
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
20.1 Full Page Read Cycle (1 of 2)
CS
RAS
CAS
45
WE
BA
AP
RAx
Addr
RAx
RBx
CAx
RBy
CBx
RBx
RBy
tRP
DQM
Hi-Z
Activate
Command
Bank A
Ax
Read
Command
Bank A
Ax+1
Activate
Command
Bank B
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Bx+5
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Bx+6
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
V54C365164VD(L)
I/O
T0
T1
T2
T3
Burst Length = Full Page, CAS Latency = 3
T4
T5
T6
T7
T8
T
T
T
T
T
T
T
T
T
T
T
T
CLK
tCK3
CKE
High
T
T
CILETIV LESOM
\
V54C365164VD(L) Rev. 1.3 September 2001
20.2 Full Page Read Cycle (2 of 2)
CS
RAS
CAS
WE
46
BA
AP
RAx
Addr
RAx
RBx
CAx
RBy
CBx
RBx
RBy
tRRD
DQM
Hi-Z
Activate
Command
Bank A
Ax
Read
Command
Bank A
Activate
Command
Bank B
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Bx+3
Bx+4
Bx+5
Full Page burst operation does not
terminate when the length is
Precharge
satisfied; the burst counter
Command
increments and continues
Bank B
The burst counter wraps bursting beginning with
from the highest order
the starting address.
page address back to zero
Burst Stop
during this time interval.
Command
Read
Command
Bank B
Activate
Command
Bank B
V54C365164VD(L)
I/O
T0
T1
T2
T3
T4
Burst Length = Full Page, CAS Latency = 2
T5
T
T
T
T
T
T
T
T
T
T
T
T
T
T
CLK
tCK2
CKE
High
T
T
T
CILETIV LESOM
\)
V54C365164VD(L) Rev. 1.3 September 2001
21.1 Full Page Write Cycle (1 of 2)
CS
RAS
CAS
WE
47
BA
AP
RAx
Addr
RAx
RBx
CAx
RBx
DAx
DAx+1 DAx+2 DAx+3
RBy
CBx
RBy
DQM
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
DAx-1
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Activate
Write
Command
Precharge
Command
Data is ignored.
Bank B
Command
Bank B
Bank B
The burst counter wraps
Full Page burst operation does not
from the highest order
terminate when the burst length is satisfied;
page address back to zero
the burst counter increments and continues
Burst Stop
during this time interval.
bursting beginning with the starting address.
Command
Activate
Command
Bank B
V54C365164VD(L)
I/O
T0
T1
T2
T3
Burst Length = Full Page, CAS Latency = 3
T4
T5
T6
T
T
T
T
T
T
T
T
T
T
T
T
T
T
CLK
tCK3
CKE
High
T
T
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
21.2 Full Page Write Cycle (2 of 2)
CS
RAS
CAS
WE
48
BA
AP
RAx
Addr
RAx
RBy
RBx
CAx
RBx
DAx
DAx+1 DAx+2 DAx+3
RBy
CBx
DQM
Hi-Z
Activate
Command
Bank A
Data is ignored.
Write
Command
Bank A
DAx-1
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Activate
Write
Command
Precharge
Command Full Page burst operation does not
Bank B
Command
Bank B terminate when the length is
Bank B
satisfied;
the
burst
counter
The burst counter wraps
increments and continues
from the highest order
bursting beginning with
page address back to zero
Burst Stop
the starting address.
during this time interval.
Command
Activate
Command
Bank B
V54C365164VD(L)
I/O
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
T21
CLK
tCK2
CKE
High
T22
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
Burst Length = 8 or Full Page, CAS Latency = 2
22.1 Precharge Termination of a Burst (1 of 2)
CS
RAS
CAS
49
WE
BA
AP
RAx
Addr
RAx
RAy
RAy
CAx
RAz
RAz
CAy
CAz
tRP
tRP
tRP
I/O
Hi-Z
Activate
Command
Bank A
DAx0 DAx1 DAx2 DAx3
Write
Precharge
Command
Command
Bank A
Bank A
Precharge Termination
of a Write Burst. Write
data is masked.
Ay0
Activate
Command
Bank A
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Az0
Read
Command
Bank A
Az1
Precharge
Command
Bank A
Precharge Termination
of a Read Burst.
Az2
V54C365164VD(L)
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
High
T22
CILETIV LESOM
V54C365164VD(L) Rev. 1.3 September 2001
Burst Length = 4,8 or Full Page, CAS Latency = 3
22.2 Precharge Termination of a Burst (2 of 2)
CS
RAS
CAS
WE
50
BA
AP
RAx
Addr
RAx
RAy
RAy
CAx
RAz
RAz
CAy
tRP
tRP
DQM
Hi-Z
Activate
Command
Bank A
DAx0
Write
Command
Bank A
Write Data
is masked
Ay0
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst.
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Precharge Termination
of a Read Burst.
V54C365164VD(L)
I/O
MOSEL VITELIC
V54C365164VD(L)
Complete List of Operation Commands
SDRAM Function Truth Table
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
L
H
H
L
L
X
H
L
X
H
L
H
L
X
X
BS
BS
BS
BS
X
Op-
X
X
X
X
RA
AP
X
Code
NOP or Power Down
NOP
ILLEGAL2
ILLEGAL2
Row (&Bank) Active; Latch Row Address
NOP4
Auto-Refresh or Self-Refresh5
Mode reg. Access5
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
L
L
H
H
L
X
X
H
L
H
L
X
X
X
BS
BS
BS
BS
X
X
X
CA,AP
CA,AP
X
AP
X
NOP
NOP
Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP
ILLEGAL2
Precharge
ILLEGAL
Read
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, New Read, DetermineAP3
Term Burst, Start Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge
ILLEGAL
Write
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
BS
BS
BS
X
X
X
X
CA,AP
CA,AP
X
AP
X
NOP (Continue Burst to End;>Row Active)
NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active
Term Burst, Start Read, DetermineAP3
Term Burst, New Write, DetermineAP3
ILLEGAL2
Term Burst, Precharge3
ILLEGAL
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Idle
Row Active
Read
with
Auto
Precharge
V54C365164VD(L) Rev. 1.3 September 2001
51
MOSEL VITELIC
V54C365164VD(L)
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT
STATE1
CS
RAS
CAS
WE
BS
Addr
ACTION
Write
with
Auto
Precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
BS
BS
X
BS
BS
X
X
X
X
X
X
X
AP
X
NOP (Continue Burst to End;> Precharge)
NOP (Continue Burst to End;> Precharge)
ILLEGAL2
ILLEGAL2
ILLEGAL
ILLEGAL2
ILLEGAL2
ILLEGAL
Precharging
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Idle after tRP
NOP;> Idle after tRP
ILLEGAL2
ILLEGAL2
ILLEGAL2
NOP4
ILLEGAL
Row
Activating
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP;> Row Active after tRCD
NOP;> Row Active after tRCD
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Write
Recovering
H
L
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
H
H
L
X
H
L
X
H
L
X
X
X
BS
BS
BS
BS
X
X
X
X
X
X
AP
X
NOP
NOP
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL2
ILLEGAL
Refreshing
H
L
L
L
L
L
X
H
H
H
L
L
X
H
H
L
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP;> Idle after tRC
NOP;> Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
Accessing
V54C365164VD(L) Rev. 1.3 September 2001
52
MOSEL VITELIC
V54C365164VD(L)
Clock Enable (CKE) Truth Table:
CKE
n-1
CKE
n
CS
RAS
CAS
WE
Addr
Self-Refresh6
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Self-Refresh, Idle after tRC
EXIT Self-Refresh, Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self-Refresh)
Power-Down
H
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
INVALID
EXIT Power-Down, > Idle.
EXIT Power-Down, > Idle.
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low-Power Mode)
All. Banks
Idle7
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
X
X
X
H
H
H
L
L
L
X
X
X
H
H
L
H
L
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Enter Power- Down
Enter Power- Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self-Refresh
ILLEGAL
NOP
Any State
other than
listed above
H
H
L
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Refer to the function truth table
Begin Clock Suspend next cycle8
Exit Clock Suspend next cycle8.
Maintain Clock Suspend.
STATE(n)
ACTION
Abbreviations:
RA = Row Address
CA = Column Address
BS = Bank Address
AP = Auto Precharge
Notes for SDRAM function truth table:
1.
2.
3.
4.
5.
6.
Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
Illegal if any bank is not Idle.
CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.
V54C365164VD(L) Rev. 1.3 September 2001
53
MOSEL VITELIC
V54C365164VD(L)
Package Diagram
54-Pin Plastic TSOP-II (400 mil)
0.047 [1.20] MAX
0.400 ±0.005
[10.16 ±0.13]
0.04 ±0.002
[1 ±0.05]
0°–5°
.004 [0.1]
0.031
[0.80]
+0.002
0.016 -0.004
+0.05
0.40 -0.10
0.006 [0.15] MAX
0.463 ± 0.008
[11.76 ± 0.20]
.008 [0.2] M 54x
54
28
Index Marking
27
1
1
0.881 -0.01
[22.38 -0.25]
1 Does not include plastic or metal protrusion of 0.15 max. per side
V54C365164VD(L) Rev. 1.3 September 2001
+0.004
0.006 -0.002
+0.01
0.15 -0.05
54
Unit in inches [mm]
0.024 ± 0.008
[0.60 ± .020]
MOSEL VITELIC
V54C365164VD(L)
56 Ball Grid Array (or BGA)
12.19±0.10
10.40
0.895±0.10
ø0.50±0.05
0.20 M S B
Package Type: 56 Balls WBGA
ø0.15 M S A B
ø0.08 M S
+0.10
1.27-0.20
0.40±0.05
0.20 M S A
0.1 S
B
S
0.25+0.05 (#3)
-0.10
0.2 S
Max. 2.50 (#4)
V54C365164VD(L) Rev. 1.3 September 2001
Notes:
#1: No Bond Finger Exposed
#2: Do not measure thickness within this area
#3: No Au Wire Exposed
#4: Do not measure // within this area
55
Max. 1.50 (#2)
4.80
Min. 0.10 (#1)
0.85±0.10
0.80
1.60
A
6.50±0.10
0.80
0.40
MOSEL VITELIC
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V54C365164VD(L)
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The information in this document is subject to change without
notice.
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document may be copied or reproduced in any form or by any
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sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
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