ICs for Consumer Electronics Field Mixer SDA 9270 Data Sheet 01.96 SDA 9270 Revision History: Current Version: 01.96 Previous Version: Page Subjects (changes since last revision) 24 HYTHL1 control bits have been increased to 6 25 HYTHL2 control bits have been increased to 6 25 HYTHH1 control bits have been increased to 6 25 HYTHH2 control bits have been increased to 6 27 Clock inputs CLL, SCA, SCAD: SCA clock frequence MIN changed to 12 MHz SCAD clock specification added Fall/rise time specification added 27 I2C-Bus specification extended to fast mode 29 Max. average supply current: 200 mA Edition 01.96 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1996. All Rights Reserved. Attention please! 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General Information Table of Contents Page 1 1.1 1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Field Interpolation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Field Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SYNC-Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 3.1 3.2 3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Semiconductor Group 3 4 4 5 6 7 25 25 26 28 Field Mixer SDA 9270 Preliminary Data 1 CMOS Introduction The Field Mixer SDA 9270 is an add-on component for the Siemens MEGAVISION IC set which enables the system to reduce large area and line flickering of interlaced TV standards. 1.1 • • • • • Features High performance line flicker reduction algorithm Two input data formats (4:1:1 and 4:2:2) I2C-Bus control P-MQFP-80 package 5 V supply voltage P-MQFP-80-1 Supported MEGAVISION features • Multipicture (still in picture, picture in still, 9xpicture) • Still field • Zoom New MEGAVISION features • Still frame • Background still field MEGAVISION features not supported • 4:4:4 • Colored frame insertion (FRM) Type Ordering Code Package SDA 9270 Q67100-H5158 P-MQFP-80-1 Semiconductor Group 4 01.96 SDA 9270 1.2 Block Diagram Semiconductor Group 5 SDA 9270 1.3 Pin Configuration Semiconductor Group 6 SDA 9270 1.4 Pin Description Pin No. Name Type Description 10, 30, 47, 54, 70 VSS S Supply voltage (VSS) for digital parts and input stages 11, 31, 48, 55, 71 VDD S Supply voltage (VDD) for digital parts and input stages 74 .. 80,1 UVA0 .. 7 I/TTL Data input UV of channel A (see Data Format) 2 .. 9 YA0 .. 7 Data input Y of channel A (see Data Format) 12 .. 19 UVB0 .. 7 I/TTL Data input UV of channel B (see Data Format) 20 .. 27 YB0 .. 7 I/TTL Data input Y of channel B (see Data Format) 28 RENB Q/TTL RAM enable field memory B 29 OEBB Q/TTL Output enable port B of field memory B 32 SACQ Q/TTL Serial column address output 33 SARQ Q/TTL Serial row address output 34 SCAD I/TTL Serial address clock input 35 SCA I/TTL Clock signal for data input 36 REN I/TTL RAM enable / input from SDA 9220 37 SACIN I/TTL Serial column address / input from SDA 9220 38 SARIN I/TTL Serial row address / input from SDA 9220 39 VS2 I/TTL 100 Hz vertical synchronization signal 40 BLN I/TTL Blanking signal, high level indicates active video line 41 BLN2 I/TTL Blanking signal / double line frequency 42 CLL I/TTL System clock 43.. 46,49..52 YQ0 .. 7 Q/TTL Data output Y of channel Q (see Data Format) 53,56 .. 62 UVQ0 ..7 Q/TTL Data output UV of channel Q (see Data Format) 63 ZM I/TTL Zoom control input (HIGH level for zoom mode) 64 VS1 I/TTL 50 Hz vertical synchronization signal 65 TEST I/TTL Test pin; must be connected to VSS for normal operation 66 SCL I I2C-Bus clock line 67 SDA IQ I2C-Bus data line Semiconductor Group I/TTL 7 SDA 9270 Pin Description (cont’d) Pin No. Name Type 68 BLN3 Q/TTL Blanking signal / BLN2 delayed 69 VS3 Q/TTL Vertical synchronization signal (switched raster) 72 RENA Q/TTL RAM enable field memory A 73 OEBA Q/TTL Output enable port B of field memory A S: supply, I: input, 2 Description Q: output, TTL: digital (TTL) System Description The device generates at its output an opportune sequence of 100/120 Hz fields derived by processing the field A and the field B which are stored in 2 external field memories and made available to the SDA 9270 on 2 separate input ports of 16 bit width each. The device SDA 9270 generates also control signals for the SDA 9251 which are necessary to operate the TV - SAMs in the Frame mode, that is to write the incoming information alternatively in one or the other field memory. Additionally the device generates a vertical sync pulse which has to be synchronized with the respective field output. A horizontal blanking signal in phase with the output data is also made available. Semiconductor Group 8 SDA 9270 2.1 Input Data Format The SDA 9270 accepts for the input channels A and B two different input formats (I2C-Bus : INFOR) with two possible sample frequency relations of Y : (B-Y) : (R-Y). The representation of the samples is programmable separately for luminance and chrominance signals as positive dual code or 2’s complement code (I2C-Bus : INCODL, INCODC) Data Pin Data Format 4:1:1 INFOR = 0 4:2:2 Parallel INFOR = 1 Yx7 Y07 Y17 Y27 Y37 Y07 Y17 Yx6 Y06 Y16 Y26 Y36 Y06 Y16 Yx5 Y05 Y15 Y25 Y35 Y05 Y15 Yx4 Y04 Y14 Y24 Y34 Y04 Y14 Yx3 Y03 Y13 Y23 Y33 Y03 Y13 Yx2 Y02 Y12 Y22 Y32 Y02 Y12 Yx1 Y01 Y11 Y21 Y31 Y01 Y11 Yx0 Y00 Y10 Y20 Y30 Y00 Y10 UVx7 U07 U05 U03 U01 U07 V07 UVx6 U06 U04 U02 U00 U06 V06 UVx5 V07 V05 V03 V01 U05 V05 UVx4 V06 V04 V02 V00 U04 V04 UVx3 U03 V03 UVx2 U02 V02 UVx1 U01 V01 UVx0 U00 V00 Xab: X: signal component Yx,UVx : a: sample number x : A,B b: bit number The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 30 MHz. Consequently the SDA 9270 is dedicated for applications in high quality digital video systems. The data input stages and the internal data multiplexer operate with a special input clock (SCA). For applications in the Siemens MEGAVISION System the SCA-clock is identical with the memory output clock. Semiconductor Group 9 SDA 9270 2.2 Output Data Format The data format for the output channel Q will be a 4:2:2 parallel format in 2’s complement code representation. Xab: Data Pin 4:2:2 Parallel YQ7 Y07 Y17 YQ6 Y06 Y16 YQ5 Y05 Y15 YQ4 Y04 Y14 YQ3 Y03 Y13 YQ2 Y02 Y12 YQ1 Y01 Y11 YQ0 Y00 Y10 UVQ7 U07 V07 UVQ6 U06 V06 UVQ5 U05 V05 UVQ4 U04 V04 UVQ3 U03 V03 UVQ2 U02 V02 UVQ1 U01 V01 UVQ0 U00 V00 X: signal component Semiconductor Group a: sample number 10 b: bit number SDA 9270 2.3 Field Interpolation and Switching In order to reduce the annoying line and edge flickering a frame rate upconversion is implemented. The upconversion includes a combination of interpolation algorithms which are determined via I2C-Bus and then selected automatically depending on the picture motion content. The field interpolation and switching block accepts at its input the data of the two channels A and B, which are the combined luminance and chrominance information respectively of the field A and the field B. The field rate is 100/120 Hz. A fallback mode which corresponds to the operating mode AABB of the original MEGAVISION system is made available. This mode is selected automatically in case of non-standard input signals carrying unstable sync informations or it can be forced via I2C-Bus. 2.4 Motion Detection The motion detection output is switched in a 25/30 Hz frame synchronous raster. As input signals for this block are accepted the luminance signal components of the input channels A and B. By comparing the two fields the motion detector generates an information about 3 possible motion content levels: LOW, MEDIUM and HIGH. 2.5 Field Memory Control The Field Mixer SDA 9270 has to provide the two external field memories – composed of TV-SAM SDA 9251 – with two pairs of control signals. One pair RENA and RENB enables the MEGAVSION system to write the incoming field A and field B information alternately into one field memory block and then into the other. A second pair of control signals OEBA and OEBB enables alternately the output back channels of field memory A and B for the noise reduction in the Picture Processor SDA 9290. Because of the timing the serial address signals SAC and SAR generated by the MSC SDA 9220 must be delayed by 4 SCAD-clock periods. This delay is implemented in the SDA 9270. The Sync signals VS1 and BLN and the clock signal SCAD are used as timing reference signals. 2.6 Frame Synchronization In order to synchronize the data flows within field memories and Field Mixer and to coordinate the signal information with the associated deflection control the Field Mixer SDA 9270 has to generate 25 Hz picture frame sync signals. One 25 Hz frame sync signal is necessary for generating the field memory control signals RENA, RENB, OEBA, OEBB with a pattern repetition of 25 Hz each. This signal is synchronized to the front end side video signal of the MEGAVISION block and uses therefore as input signals the 50 Hz vertical sync signal VS1 generated by the MSC SDA 9220 and the horizontal blanking signal BLN. Semiconductor Group 11 SDA 9270 A second 25 Hz frame sync signal is needed in the interpolation and switching block and in the VS3 pulse generation block for assuring an output data sequence of the channel Q synchronized with the VS3 pulse. As reference signals for this second frame sync signal are used the 100 Hz vertical sync signal VS2 and the blanking signal BLN2 both generated by the MSC SDA 9220. 2.7 SYNC-Signal Generation This functional block generates a couple of sync signal needed in the processing stages following the Field Mixer device. This couple includes the vertical sync signal VS3 and the horizontal blanking signal BLN3. All these signals are synchronized with the output channel Q. 2.8 I2C-Bus 2.8.1 I2C-Bus Address 0 0 0 1 1 1 1 2.8.2 I2C-Bus Format write: S 0 0 0 1 1 1 1 0 A S: A: P: NA: Subaddress A Data Byte Start condition Acknowledge Stop condition Not Acknowledge An automatical address increment function is implemented. Semiconductor Group 12 A ***** A P SDA 9270 After switching on the IC (RES=0), all bits are set to defined states. Particularly: Register Default Value Register Default Value 00 00H 0B 50H 01 00H 0C 03H 02 00H 0D 0DH 03 00H 0E 08H 04 40H 0F 28H 05 F4H 10 A5H 06 58H 11 55H 07 20H 12 0AH 08 F8H 13 18H 09 70H 14 05H 0A E8H 15 03H Semiconductor Group 13 SDA 9270 I2C-Bus Commands 2.8.3 Subadd. (Hex.) Data Byte D7 D6 D5 D4 D3 D2 D1 D0 00 LINFRA PIXLIN WRMODE2 WRMODE1 WRMODE0 NRDEL RASTER1 RASTER0 01 0 INCODL INCODC INFOR FALLBACK FIWIN2 FIWIN1 FIWIN0 02 ZMMODE1 ZMMODE0 0 0 INTMODLL1 INTMODLL0 INTMODCL1 INTMODCL0 03 RDMODE1 RDMODE0 0 0 INTMODLM1 INTMODLM0 INTMODCM1 INTMODCM0 04 EDCONST1 EDCONST0 0 0 INTMODLH1 INTMODLH0 INTMODCH1 INTMODCH0 05 CFHENA07 CFHENA06 CFHENA05 CFHENA04 CFHENA03 CFHENA02 CFHENA01 CFHENA00 06 CFHENA17 CFHENA16 CFHENA15 CFHENA14 CFHENA13 CFHENA12 CFHENA11 CFHENA10 07 CFHENB07 CFHENB06 CFHENB05 CFHENB04 CFHENB03 CFHENB02 CFHENB01 CFHENB00 08 CFSCHA007 CFSCHA006 CFSCHA005 CFSCHA004 CFSCHA003 CFSCHA002 CFSCHA001 CFSCHA000 09 CFSCHA107 CFSCHA106 CFSCHA105 CFSCHA104 CFSCHA103 CFSCHA102 CFSCHA101 CFSCHA100 0A CFSCHA017 CFSCHA016 CFSCHA015 CFSCHA014 CFSCHA013 CFSCHA012 CFSCHA011 CFSCHA010 0B CFSCHA117 CFSCHA116 CFSCHA115 CFSCHA114 CFSCHA113 CFSCHA112 CFSCHA111 CFSCHA110 0C CFSCHB007 CFSCHB006 CFSCHB005 CFSCHB004 CFSCHB003 CFSCHB002 CFSCHB001 CFSCHB000 0D CFSCHB107 CFSCHB106 CFSCHB105 CFSCHB104 CFSCHB103 CFSCHB102 CFSCHB101 CFSCHB100 0E CFSCHB017 CFSCHB016 CFSCHB015 CFSCHB014 CFSCHB013 CFSCHB012 CFSCHB011 CFSCHB010 Semiconductor Group 14 SDA 9270 I2C-Bus Commands (cont’d) Subadd. (Hex.) Data Byte D7 D6 D5 D4 D3 D2 D1 D0 0F CFSCHB117 CFSCHB116 CFSCHB115 CFSCHB114 CFSCHB113 CFSCHB112 CFSCHB111 CFSCHB110 10 MDTHL21 MDTHL20 MDTHL11 MDTHL10 0 MDBLTH2 MDBLTH1 MDBLTH0 11 MDTHU21 MDTHU20 MDTHU11 MDTHU10 MDTHM21 MDTHM20 MDTHM11 MDTHM10 12 0 0 HYTHL15 HYTHL14 HYTHL13 HYTHL12 HYTHL11 HYTHL10 13 0 0 HYTHL25 HYTHL24 HYTHL23 HYTHL22 HYTHL21 HYTHL20 14 0 0 HYTHH15 HYTHH14 HYTHH13 HYTHH12 HYTHH11 HYTHH10 15 0 0 HYTHH25 HYTHH24 HYTHH23 HYTHH22 HYTHH21 HYTHH20 Semiconductor Group 15 SDA 9270 2.8.4 Detailed Description Subaddress 00 Bit D7 Name LINFRA D6 PIXLIN D5...D3 WRMODE* D2 NRDEL D1...D0 RASTER* Function Lines per frame: 0: 625 lines per frame (default value) 1: 525 lines per frame Pixels per line: 0: 864 pixels per line (default value) 1: 858 pixels per line Write Mode: 000 : Normal operation: field memory A and field memory B are written alternately (default value) 001 : Still picture A and B: writing is suppressed for both field memories 010 : Still picture A: writing is suppressed for field memory A, all incoming fields are written to field memory B 011 : Still picture A: writing is suppressed for field memory A, every second field is written to field memory B (Field Mode B) 100 : Still picture B: writing is suppressed for field memory B, all incoming fields are written to field memory A 101 : Still picture B: writing is suppressed for field memory B, every second field is written to field memory A (Field Mode A) 110 : Reserved 111 : Reserved Noise Reduction Delay: conditions: 2 field memory configuration, WRMODE = 000 0: Data delay for recursive filtering is one frame (default value) 1: Data delay for recursive filtering is one field Deflection Raster control: 00: Control by interpolation algorithm (default value) 01: ααββ 10: αβαβ 11: αααα Note: SDA 9220 programming: – Subaddress 00 / D7 (EXSYN): For EXSYN=1 WRMODE=100 is required. – Subaddress 01 / D7 (FLDM), Subaddress 02 / D7 (STB): FLDM and STB should always be set to 0. – Subaddress 00 / D1, D0 (VDM): VDM must be set to 00. Semiconductor Group 16 SDA 9270 Subaddress 01 Bit Name Function D6 INCODL Coding of luminance input data: 0: positive dual code (default value) 1: 2’s complement D5 INCODC Coding of chrominance input data: 0: positive dual code (default value) 1: 2’s complement D4 INFOR Input data format: 0: 4:1:1 luminance, chrominance parallel (8+4 wires) (default value) 1: 4:2:2 luminance, chrominance parallel (8+8 wires) D3 FALLBACK Fallback mode: 0: Normal operation (default value) 1: programmed fall back mode is activated for current display D2...D0 FIWIN Field identification window Definition of a time window. Switching from fall back mode to programmed display mode is not performed until the field identification algorithm is working in a stable condition during the programmed time. 000 : 7 field periods (default value) 001 : 15 field periods : : 110 : 55 field periods 111 : 63 field periods Semiconductor Group 17 SDA 9270 Subaddress 02 Bit Name Function D7..D6 ZMMODE zoom mode (enabled only if pin ZM = 1 and RDMODE = 00) 00: field sequence at output Q: AABB (default value) 01: field sequence at output Q: ABAB 10: display with raster correction 11: Reserved D3..D2 INTMODLL luminance interpolation mode, low degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence ABAB without interpolation (αβαβ) 10: Schröder algorithm (αβαβ) 11: Hentschel algorithm (αβαβ) D1..D0 INTMODCL chrominance interpolation mode, low degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence AABB without interpolation (αβαβ) 10: field sequence ABAB without interpolation (αβαβ) 11: linear interpolation (αβαβ) Semiconductor Group 18 SDA 9270 Subaddress 03 Bit Name Function D7..D6 RDMODE read mode 00: both inputs are used (interpolation enabled if ZM = 0) (default value) 01: only input A is used (without interpolation) 10: only input B is used (without interpolation) 11: Reserved D3..D2 INTMODLM luminance interpolation mode, medium degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence ABAB without interpolation (αβαβ) 10: Schröder algorithm (αβαβ) 11: Hentschel algorithm (αβαβ) D1..D0 INTMODCM chrominance interpolation mode, medium degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence AABB without interpolation (αβαβ) 10: field sequence ABAB without interpolation (αβαβ) 11: linear interpolation (αβαβ) Semiconductor Group 19 SDA 9270 Subaddress 04 Bit Name Function D7..D6 EDCONST edge detector gain factor 00: 2 01: 3 (default value) 10: 4 11: 5 D3..D2 INTMODLH luminance interpolation mode, high degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence ABAB without interpolation (αβαβ) 10: Schröder algorithm (αβαβ) 11: Hentschel algorithm (αβαβ) D1..D0 INTMODCH chrominance interpolation mode, high low degree of motion 00: field sequence AABB without interpolation (ααββ) (default value) 01: field sequence AABB without interpolation (αβαβ) 10: field sequence ABAB without interpolation (αβαβ) 11: linear interpolation (αβαβ) Subaddress 05 Bit Name Function D7..D0 CFHENA0 Hentschel algorithm, 8-bit coefficient a0 (2’s complement) (default value F4H) Subaddress 06 Bit Name Function D7..D0 CFHENA1 Hentschel algorithm, 8-bit coefficient a1 (2’s complement) (default value 58H) Semiconductor Group 20 SDA 9270 Subaddress 07 Bit Name Function D7..D0 CFHENB0 Hentschel algorithm, 8-bit coefficient b0 (2’s complement) (default value 20H) Subaddress 08 Bit Name Function D7..D0 CFSCHA00 Schröder algorithm, 8-bit coefficient a00 (2’s complement) (default value F8H) Subaddress 09 Bit Name Function D7..D0 CFSCHA10 Schröder algorithm, 8-bit coefficient a10 (2’s complement) (default value 70H) Subaddress 0A Bit Name Function D7..D0 CFSCHA01 Schröder algorithm, 8-bit coefficient a01 (2’s complement) (default value E8H) Subaddress 0B Bit Name Function D7..D0 CFSCHA11 Schröder algorithm, 8-bit coefficient a11 (2’s complement) (default value 50H) Subaddress 0C Bit Name Function D7..D0 CFSCHB00 Schröder algorithm, 8-bit coefficient b00 (2’s complement) (default value 03H) Semiconductor Group 21 SDA 9270 Subaddress 0D Bit Name Function D7..D0 CFSCHB10 Schröder algorithm, 8-bit coefficient b10 (2’s complement) (default value 0DH) Subaddress 0E Bit D7..D0 Name Function CFSCHB01 Schröder algorithm, 8-bit coefficient b01 (2’s complement) (default value 08H) Subaddress 0F Bit Name Function D7..D0 CFSCHB11 Schröder algorithm, 8-bit coefficient b11 (2’s complement) (default value 28H) Subaddress 10 Bit Name Function D7..D6 MDTHL2 threshold for low degree of motion (small blocks) 00: 0 01: 64 10: 128 (default value) 11: 192 D5..D4 MDTHL1 threshold for low degree of motion (large blocks) 00: 0 01: 64 10: 128 (default value) 11: 192 D2..D0 MDBLTH threshold in front of the blocking module 000: 4 001: 8 : : 111: 32 (default value 101) Semiconductor Group 22 SDA 9270 Subaddress 11 Bit Name Function D7..D6 MDTHU2 threshold for high degree of motion (small blocks) 00: 384 01: 512 (default value) 10: 640 11: 768 D5..D4 MDTHU1 threshold for high degree of motion (large blocks) 00: 384 01: 512 (default value) 10: 640 11: 768 D3..D2 MDTHM2 threshold for second field difference (small blocks) 00: 64 01: 128 (default value) 10: 192 11: 256 D1..D0 MDTHM1 threshold for second field difference (large blocks) 00: 64 01: 128 (default value) 10: 192 11: 256 Subaddress 12 Bit Name Function D5..D0 HYTHL1 hysteresis threshold, low degree of motion (large blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 001010) Semiconductor Group 23 SDA 9270 Subaddress 13 Bit Name Function D5..D0 HYTHL2 hysteresis threshold, low degree of motion (small blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 011000) Subaddress 14 Bit Name Function D5..D0 HYTHH1 hysteresis threshold, high degree of motion (large blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 000101) Subaddress 15 Bit Name Function D5..D0 HYTHH2 hysteresis threshold, high degree of motion (small blocks) 000000: 1 000001: 1 000010: 2 : 111111: 63 (default value 000011) Semiconductor Group 24 SDA 9270 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remark min. max. TA Tstg Tj TS tS VI VQ VS 0 70 ˚C − 65 125 ˚C 125 ˚C 260 ˚C 10 s − 0.3 6 V Supply voltage Differentials V − 0.25 0.25 V Total power dissipation Ptot 1 W ESD protection ESD −2 2 kV MIL STD 883C method 3015.6, 100 pF, 1500 Ω − 100 100 mA all inputs/outputs Operating temperature Storage temperature Junction temperature Soldering temperature Soldering time Input voltage Output voltage Supply voltages Latch-up protection − 0.3 V VDD + 0.3 V V − 0.3 V VDD + 0.3 V V VCC respectively VCC respectively between any internally nonconnected supply pins of the same kind, see Pin Description All voltages listed are referenced to ground (0 V, VSS) except where noted. Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 25 SDA 9270 3.2 Recommended Operating Conditions Parameter Supply voltages Ambient temperature Symbol Limit Values Unit min. typ. max. VDD VCC TA 4.5 5 5.5 V 0 25 70 ˚C VIH VIL 2.0 V VDD 1 0 0.8 V VQH VQL 2.4 Test Conditions All TTL Inputs High-level input voltage Low-level input voltage All TTL outputs High-level output voltage Low-level output voltage V 0.4 V 30 MHz IQH = − 2.0 mA IQL = 3.0 mA Clock TTL Inputs CLL, SCA, SCAD Clock frequency Low time High time Rise time Fall time SCA - CLL skew time 12 tWL tWH tTLH tTHL tSK 27 10 ns 10 ns 0 5 ns 5 ns 15 ns I2C Bus (all values are referred to min(VIH) and max(VIL)) High-level input voltage Low-level input voltage SCL clock frequency Inactive time before start of transmission Set-up time start condition Hold time start condition SCL low time SCL high time Set-up time DATA Semiconductor Group VIH VIL fSCL tBUF 3V VDD 1 0 1.5 V 0 400 kHz 1.3 µs tSU;STA tHD;STA tLOW tHIGH tSU;DAT 0.6 µs 0.6 µs 1.3 µ 0.6 µs 100 ns 26 Rise/fall time ≤ 5 ns Diagram on page 22 SDA 9270 3.2 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. Hold time DATA SDA/SCL rise times SDA/SCL fall times Set-up time stop condition Low-level output current tHD;DAT tR tF tSU;STO IOL typ. Unit max. Test Conditions µs 0 300 ns 300 ns fSCL = 400 kHz µs 0.6 3 mA Note: Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA = 25 ˚C and the nominal supply voltage. Semiconductor Group 27 SDA 9270 3.3 Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Limit Values min. Average supply current IS Unit Remark max. 200 mA All VCC and VDD pins 10 pF Not tested; max. 7 pF for SCA, CLL 10 µA All Digital Inputs (including I/O inputs) Input capacitance CI Input leakage current II − 10 TTL Inputs: YA, YB, UVA, UVB (referenced to SCA) Set-up time Input hold time tSU tIH 7 ns 6 ns TTL Inputs: REN, SACIN, SARIN (referenced to SCAD) Set-up time Input hold time tSU tIH 7 ns 6 ns TTL Inputs: BLN, BLN2, VS1, VS2, ZM (referenced to CLL) Note: For BLN a jitter of ± 1 CLL is allowed Set-up time Input hold time tSU tIH 7 ns 6 ns TTL Outputs: YQ, UVQ (referenced to CLL) Hold time Delay time tQH tQD 6 ns 25 ns CL = 30 pF TTL Outputs: VS3, BLN3 (referenced to CLL) Hold time Delay time tQH tQD 6 ns 25 ns CL = 30 pF TTL Outputs: RENA, RENB, SACQ, SARQ (referenced to SCAD) Hold time Delay time Semiconductor Group tQH tQD 6 ns 20 28 ns CL = 50 pF SDA 9270 3.3 Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Limit Values min. Unit Remark max. TTL Outputs: OEBA, OEBB (referenced to SCAD) Hold time Delay time tQH tQD 6 ns 20 ns CL = 30 pF Input/Output: SDA (referenced to SCL; Open Drain Output) Low-level output voltage VOL 0.5 V at IOL = max Note: The listed characteristics are ensured over the operating range of the integrated circuit. Semiconductor Group 29 SDA 9270 4 Application Information Semiconductor Group 30 SDA 9270 5 Waveforms Timing Diagram Data Input/Output Referenced to the Clock Timing Diagram Clock Skew SCA - CLL Semiconductor Group 31 SDA 9270 6 Package Outlines GPM05249 P-MQFP-80-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 32 Dimensions in mm SDA 9270 Semiconductor Group 33