Memory Sync Controller III SDA 9220-5 Preliminary Data MOS IC Features Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still with different frame versions ● Zoom with selection of enlarged picture segment (8 x 12 positions) ● Pin-programmable operation without standard conversion ● ● ● ● ● ● P-LCC-44-1 Type Ordering Code Package SDA 9220-5 Q67100-H5087 P-LCC-44-1 (SMD) Functional Description The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other devices of the Featurebox it enhances picture quality and offers a number of special operating modes. The MSC III is set via the I2C Bus, it being possible to switch the I2C Bus address by hardware so that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX supplied by the MSC III. Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X (27 MHz), are the memory-driving signals (RA, RB, WT, RE, SCAD, SCA) and the sync signal CSY for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (VS1, VS2) are also generated. Semiconductor Group 117 01.94 SDA 9220-5 Circuit Description The MSC III can be divided into the following function blocks (figure 6): – – – – Sync-signal generator Memory controller Clock generator I2C Bus receiver The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal CFH is output to prevent the bottom flutter effect in the video cassette recorder mode. In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this case. The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR, SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for requesting data from the picture processor during operation with reduced pictures. Two refresh operations are performed in the memory for each TV line. The clock generator consists essentially of a PLL which generates the internal and exported system clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching phases. All modes (except switching off the standard conversion) are set by appropriate programming of the I2C Bus data bytes. When the operating voltage is switched on, all bits of the associated control registers are set to 0. The address of the I2C Bus is set with signal ADR (24H or 26H). Semiconductor Group 118 SDA 9220-5 Detailed Circuit Description Picture Formats The MSC forms part of a digital television system with line-locked scanning frequency. The nominal word rate is 13.5 MHz for luminance and 3.375 MHz for each of the U and V color components. The active region of a TV line is identified by the high time interval of BLN. It comprises 720 pixels for luminance and 180 pixels each for U and V and is stored in its entirety. In the 50-Hz standard a field consists of 287.5 lines and in the 60-Hz standard of 243.5 lines. 288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance and 2 x 1 for chrominance with memory or display frames. The number of lines without a frame is 84 for the 50-Hz standard and 71 for the 60-Hz standard. Two lines less are displayed with a frame (figures 2 and 3). In the picture-in-still (PIS) and still-in-picture (SIP) modes a field without a frame or having a display frame is of the same size as a 9-image window. With the memory frame, however, eight pixels are lost for luminance and 2 x 2 for chrominance (figure 4). For generating the windows in the modes 9-image display, PIS and SIP the picture data are filtered horizontally and vertically in the picture processor and reduced by a factor of three. In the zoom mode a segment of the stored picture is enlarged by a factor of two by displaying each pixel twice as long and each line twice. The position of this picture segment is selectable. Eight vertical and twelve horizontal positions can be set by the I2C Bus (figure 5). Random Interlace The phase of VS relative to HS and the active picture content is measured at the input. At the output VS2 is generated in the same phase relation to HS2 and the picture content. Despite the random interlacing this means that standard picture conversion is possible without any visible interference. Display Raster There are three ways of displaying the field sequence: one is without interlace and two are with interlace, i.e. with a 50-Hz or 60-Hz interlace frequency or a 100-Hz or 120-Hz interlace frequency respectively. In what follows these are referred to symbolically as αααα, ααββ or βαβα. They are produced by a suitable sequence of the vertical sync pulses VS2 for the standard-converted video signal. The symbols αn, βn denote the vertical sync phases of the pulses (VS, VS2) referred to the horizontal blanking signals (BLN, BLN2), i.e. αn when the positive vertical sync edge falls within one blanking half cycle and βn when it falls within the complementary blanking half cycle. Normally the input signal will be as follows: (αn–1, βn–1) (αn, βn) (αn+1, βn+1) with αn and βn virtually constant. Figures 15, 16, 17, 18 and 19 show the sequence obtained for output signal VS2 when using one of the three operating modes. Semiconductor Group 119 SDA 9220-5 The standard conversion (SC) function can be activated via pin NW ● The following correlation exists: Low level at pin NW: Mode without standard conversion High level at pin NW: Mode with standard conversion If the standard conversion is switched on, there is a 100-(120-) Hz field frequency in the 50(60)-Hz standard. Field sequence with SC: A(α) A(α) B(β) B(β) 1) Field sequence without SC: A(α) B(β) The following functions can be set on the I2C Bus 2) interface: ● Still Field sequence with SC and interlace: ● ● ● ● ● ● A(β) A(α) A(β) A(α) or B(α) B(β) B(α) B(β) Field sequence with SC and without interlace: A(α) A(α) A(α) A(α) or B(β) B(β) B(β) B(β) Field sequence without SC and without interlace: A(α) A(α) or B(β) B(β) Teletext text mode: AVT(α) AVT(α) AVT(α) AVT(α) or: AVT(β) AVT(α) AVT(β) AVT(α) Teletext mixed mode: with SC AVT(α) AVT(α) AVT(β) AVT(β) without SC AVT(α) AVT(β) Teletext field mode: In this mode every second field is written to the field memory. The display raster is freely selectable. Although the vertical resolution of the TV picture is slightly less in this mode, the lack of background edge flicker improves the visual effect in teletext mixed mode. An improvement in the picture can also be achieved with VCR signals in the special modes. It is also possible to select a particular field; this is useful for specific requests. HS2 phase: Programmable between 0 and 32 µs in increments of approx. 300 ns (for delay equalization between picture generation and deflection). Write operation delay owing to delay in the picture processor for noise reduction can be set between 0 and 14 or 16 and 30 LL3X clocks. When the color frame is used, the picture-in-picture and multi-picture modes have to be activated without the software frame because the two are not identical. The picture-in-picture and multi-picture modes cannot be switched on in the field mode; there may otherwise be no gray backing for the frame function, depending on the field. The field mode can only be activated one field after the picture-in-picture or multi-picture mode. 1) A(α) Field content Vertical sync phase referred to horizontal sync pulse (raster) 2) I2C Bus: Bus system patented by Philips Semiconductor Group 120 SDA 9220-5 ● When switching from free running to line-locked mode, the following maximum synchronization times can occur for standard signals: a) Vertical synchronization at 50 (60) Hz and 100 (120) Hz: a) Horizontal synchronization at 50 (60) Hz: 100 (120) Hz: 220 (183) ms 100 (83) ms 100 (75) ms Device Interfaces The interfaces of this device are designed to work with the CSG SDA 9257 and triple ADC SDA 9205-2, or DMSD/CGC, the TV-SAMs SDA 9251-2X and Picture Processor SDA 9290-5. The standard conversion function can be enabled and disabled on one pin. All other functions are set on an I2C Bus interface. I2C Bus Interface 1. Functional Overview The following control signals are received on the I2C Bus: – – – – – – – – – – – – – – – – – – – – Synchronization (EXSYN) Blanking (BLK) Control for frame mode (MUXI, MUXS) VS noise reduction (VNR) 50/60-Hz standard (VERT) Deflection raster (VDM 1-0) Field mode with field changeover (FLDM, FLDC, FLDF) Delay compensation for write channel (WDEL 4-0) Still (STB) Frame (FR) Write mode (WM 1-0) Picture position for 9-image, picture-in-picture (VPOS 1-0, HPOS 1-0) Zoom mode (ZM) Position of zoom detail (ZV 2-0, ZH 3-0) NTSC mode with 864 pixels per line (N864) HS2 phase relation (HP 6-0) Disabling of frame display signal (FRDIS) Delay of frame display signal (FRD 6-0) Duration of CFH signal (CFHW 3-0) Position of CFH signal (CFHP 3-0) Semiconductor Group 121 SDA 9220-5 2. Description Slave Address: 0 0 1 0 0 1 ADR Receiver Format: S 0 A Slave Address A Sub Address Data Byte A P S: Start condition A: Acknowledge P: Stop condition Data Byte Formats: Function Subaddress D7 Data Byte D6 D5 D4 D3 D2 D1 D0 VNR VERT VDM1 VDM0 Control 1 00 EXSYN BLK MUXI MUXS Control 2 01 FLDM FLDC FLDF WDEL4 WDEL3 WDEL2 WDEL1 WDEL0 Control 3 02 STB FR WM1 WM0 VPOS1 VPOS0 HPOS1 HPOS0 Zoom control 03 ZM ZV2 ZV1 ZV0 ZH3 ZH2 ZH1 ZH0 HS2 phase 04 N864 HP6 HP5 HP4 HP3 HP2 HP1 HP0 FRM delay 05 FRDIS FRD6 FRD5 FRD4 FRD3 FRD2 FRD1 FRD0 CFH control 06 CFHW3 CFHW2 CFHW1 CFHW0 CFHP3 CFHP2 CFHP1 CFHP0 The subaddress is incremented automatically. When the operating voltage is applied (power-up reset), all registers are set to 0. Semiconductor Group 122 SDA 9220-5 3. Detailed Tables Control 1 (subaddress 00) Synchronization Control Bit EXSYN (D7) External synchronization (line-locked) 0 Internal synchronization (free-running) 1 Blanking Control Bit BLK (D6) Picture enabled 0 Picture blanked 1 MUX Invert, MUX Strobe (Figure 9b shows the functional diagram of MUX) Control Bit MUXI (D5) MUXS (D4) MUX = L 0 0 MUX toggles with VS2 (for VS1 = H change to L) 0 1 MUX = H 1 0 MUX toggles with VS2 (for VS1 = H change to H) 1 1 VS Noise Reduction Control Bit VNR (D3) Mode 1 (window) 0 Mode 2 (flywheel) 1 50/60-Hz-Standard Control Bit Vert (D2) 50-Hz standard 0 60-Hz standard 1 Deflection Raster Control Bit VDM 1 (D1) VDM 0 (D0) ααββ (with standard conversion) αβ (w/o standard conversion) 0 0 αααα (with standard conversion) αα (w/o standard conversion) 0 1 βαβα (with standard conversion) not defined (w/o standard conversion) 1 0 Not defined 1 1 Semiconductor Group 123 SDA 9220-5 Control 2 (subaddress 01) Field Mode Control Bit FLDM (D7) Normal mode (both fields) 0 Field mode (only one field) 1 Field Switching in Field Mode Control Bit FLDC (D6) 0→1 1→0 For FLDF = L: Change of field; (no reference to a specific field) For FLDF = H: Field 1 displayed Field 2 displayed 0 1 Field Mode Feature Selection Control Bit FLDF (D5) Free-running field mode without field reference 0 Field mode with field reference 1 Write Operation Delay in LL3 Periods (from rising edge of BLN) Control Bit WDEL4 (D4) WDEL3 (D3) WDEL2 (D2) WDEL1 (D1) WDEL0 (D0) Delay 0 to Delay 14 0 0 0 0 0 0 1 1 1 0 Delay 16 to Delay 30 1 0 0 0 0 1 1 1 1 0 Not defined × 1 1 1 1 Semiconductor Group 124 SDA 9220-5 Control 3 (subaddress 02) Still Control Bit STB (D7) Moving image 0 Still 1 Frame Control Bit FR (D6) 9-image picture, picture-in-picture without frame 0 9-image picture, picture-in-picture with frame 1 Write Mode Control Bit WM 1 (D5) WM 0 (D4) Normal mode (NM) 0 0 9-image picture mode (MP) 0 1 Picture-in-still (PIS) 1 0 Still-in-picture (SIP) 1 1 Vertical Picture Position for 9th Image Control Bit VPOS 1 (D3) VPOS 0 (D2) Vertical position 0 0 0 Vertical position 1 (not allowed for PIS and SIP) 0 1 Vertical position 2 1 0 Not defined 1 1 Horizontal Picture Position for 9th Image Control Bit HPOS 1 (D1) HPOS 0 (D0) Horizontal position 0 0 0 Horizontal position 1 (not allowed for PIS and SIP) 0 1 Horizontal position 2 1 0 Not defined 1 1 Semiconductor Group 125 SDA 9220-5 Zoom Control (subaddress 03) Zoom Control Bit ZM (D7) Normal 0 Zoom 1 Vertical Position of Zoomed Detail Control Bit ZV 2 (D6) ZV 1 (D5) ZV 0 (D4) 0 0 0 1 1 1 Vertical position 0 to Vertical position 7 Horizontal Position of Zoomed Detail Control Bit ZH 3 (D3) ZH 2 (D2) ZH 1 (D1) ZH 0 (D0) 0 0 0 0 1 1 0 1 1 × 1 × Horizontal position 0 to Horizontal position 11 Not defined x: don’t care HS2 Phase (subaddress 04) Switching in 60-Hz Mode (VERT = 1) Control Bit N864 (D7) 858 pixels per line 0 864 pixels per line 1 HS2 Phase 0 steps to 108 steps Control Bit HP 6 (D6) HP 5 (D5) HP 4 (D4) HP 3 (D3) HP 2 (D2) HP 1 (D1) HP 0 (D0) 0 0 0 0 0 0 0 1 1 0 1 1 0 0 One step corresponds to eight LL1.5 cycles (approx. 300 ns). Semiconductor Group 126 SDA 9220-5 FRM Delay (subaddress 05) FRM Disable Control Bit FRDIS (D7) Frame display signal FRM enable 0 Frame display signal FRM disable (FRM = L) 1 Delay for Frame Display Signal 0 LL1.5 cycles to 127 LL1.5 cycles Control Bit FRD 6 (D6) FRD 5 (D5) FRD 4 (D4) FRD 3 (D3) FRD 2 (D2) FRD 1 (D1) FRD 0 (D0) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 CFH Control (subaddress 06) CFH Width (H level) Control Bit CFHW3 (D7) CFHW2 (D6) CFHW1 (D5) CFHW0 (D4) 0 0 0 0 1 1 1 1 0 halfline to 15 halflines CFH Position Before VS Control Bit CFHP3 (D3) CFHP2 (D2) CFHP1 (D1) CFHP0 (D0) 0 0 0 0 1 1 1 1 3 halflines to 18 halflines Semiconductor Group 127 SDA 9220-5 Figure 1 Picture Format, Normal Mode Semiconductor Group 128 SDA 9220-5 Figure 2 Picture Formats for 9-Image Mode Semiconductor Group 129 SDA 9220-5 Figure 3 Picture Formats for 9-Image Mode, PIS and SIP with Display Frame Semiconductor Group 130 SDA 9220-5 Figure 4 Picture Formats for Picture-in-Still, Still-in-Picture Semiconductor Group 131 SDA 9220-5 Figure 5 Zoomed Picture Segments Semiconductor Group 132 SDA 9220-5 Figure 6 Block Diagram 1, Featurebox with Standard Conversion Semiconductor Group 133 SDA 9220-5 Figure 7 Block Diagram 2 Memory Sync Controller Semiconductor Group 134 SDA 9220-5 Figure 8 Pin Configuration (top view) Semiconductor Group 135 SDA 9220-5 Pin Definitions and Functions Pin No. Symbol Function Description 1 VSSA Analog ground 2 VDDA Analog supply voltage Positive supply voltage (+ 5 V) for analog part 3 RST PLL filter Connecting pin for PLL filter 4 TE2 Test pin Test pin; must be connected to VSS for normal mode 5 TE1 Test pin Test pin; must be connected to VSS for normal mode 6 TE0 Test pin Test pin; must be connected to VSS for normal mode 7 LL1.5X 27-MHz clock 27-MHz clock for devices of Featurebox generated by PLL 8 NW Select standard conversion Standard-conversion switching; high level on this pin means that standard conversion is activated 9 SCA Serial clock Serial clock for port A of TV-SAM 10 SCAD Serial address clock Serial address clock for TV-SAM 11 LL3X Clock 13.5-MHz clock for the devices of the Featurebox generated by PLL 12 VSS Digital ground 13 VDD Digital supply voltage Positive supply voltage 14 RE Row enable Control signal for TV-SAM 15 RA Read transfer Via port A of TV-SAM 16 SAR Serial row address For TV-SAM 17 RB Read transfer Via port B of TV-SAM 18 SAC Serial column address and mode For TV-SAM 19 WT Write transfer Via port C of TV-SAM 20 VSS Digital ground 21 WEI Write inhibit Write-enable input for direct disabling of write operation for field memory 22 DREQ Data request Data-request signal in 9-image mode for reduced picture data; at same time I2C Bus sync signal for picture processor 23 RESQ Reset output 24 RESI Reset input Normally on VDD (active low) 25 VDD Digital supply voltage Position supply voltage (+ 5 V) for digital part Semiconductor Group 136 SDA 9220-5 Pin Definitions and Functions (cont’d) Pin No. Symbol Function Description 26 ADR Address select 24H for ADR = 0 or 26H for ADR = 1 27 ZM Zoom signal Control signal for Featurebox output interface IC: supplies high level in zoom mode 28 VS Vertical sync Input determines vertical position of TV picture for 50-or 60-Hz field frequency 29 VS1 Vertical sync Output; noise suppressed 30 MUX MUX switching Switching signal for implementing simple frame Featurebox 31 LLSEL Select clock input A 27-MHz clock selected for LLSEL = low 32 CFH Clock frequency hold For elimination of bottom flutter effect in VCR mode 33 OSCI Crystal oscillator input 34 OSCQ Crystal oscillator output 35 SCL Serial clock I2C Bus 36 SDA Serial data I2C Bus 37 CSY Composite sync 38 FRM Display frame signal Control signal output for possible insertion of colored frame in multi-picture, picture-in still and still-inpicture modes 39 HS2 Horizontal sync display 40 VS2 Vertical sync display Vertical sync pulse for data readout 41 BLN2 Horizontal blank display Blanking signal for identifying active picture line for data readout 42 BLN Horizontal blank Blanking signal input; high phase identifies active picture line 43 LLIN Input clock 13.5 or 27 MHz 44 VSS Digital ground Semiconductor Group Crystal clock as reference for recovery in tuner scanning mode Horizontal and vertical sync pulses for Teletext device in standard-conversion mode Horizontal pulse for standard-converted picture (31.25 / 31.47 kHz) 137 SDA 9220-5 Absolute Maximum Ratings (all voltages are referred to VSS) Parameter Symbol Limit Values min. typ. Unit Remarks max. Ambient temperature TA 0 70 °C Storage temperature Tstg – 55 125 °C Thermal resistance Rth SA 50 K/W Supply voltage VDD – 0.3 6 V Input voltage VI – 0.3 6 V Total power dissipation Ptot 1.25 W 5 5.5 V Operating Range Supply voltage VDD Supply current digital IDDD 200 240 mA Sum pins 13, 27 Supply current analog IDDA 2 2.3 mA Pin 2 Ambient temperature TA 70 °C Semiconductor Group 4.5 0 138 SDA 9220-5 Characteristics Parameter Symbol Limit Values min. typ. Unit Test Condition max. Input Clock LLIN = 13.5 MHz/LLSEL = High or Open (refer to figure 9 c) Period TLLIN 68 74 80 H-pulse width tWH 25 ns L-pulse width tWL 25 ns H-input voltage VIH 2 V L-input voltage VIL 0.8 ns V Input Clock LLIN = 27 MHz/LLSEL = Low (refer to figure 9 c) Period TLLIN 34 37 40 H-pulse width tWH 10 ns L-pulse width tWL 10 ns H-input voltage VIH 2 V L-input voltage VIL 0.8 ns V Input Signal BLN, VS, WEI/Reference Clock: LLIN = 13.5 MHz (refer to figure 9c) Setup time tSU 14 ns Hold time tIH 5 ns H-input voltage VIH 2 V L-input voltage VIH H-input current IIH L-input current IIL 0.8 V – 80 – 500 µA – 100 – 500 µA Input Signal BLN, VS, WEI/Reference Clock: LLIN = 27 MHz (refer to figure 9c) Setup time tSU 7 ns Hold time tIH 6 ns H-input voltage VIH 2 V L-input voltage VIL H-input current IIH L-input current IIL Semiconductor Group 0.8 V – 80 – 500 µA – 100 – 500 µA 139 SDA 9220-5 Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Clock LL1.5X/Reference Clock: LLIN (refer to figure 9a) Period TLL1.5X 34 37 40 ns H-pulse width tWH 12 ns L-pulse width tWL 12 ns Clock skew *) tSK 0 Load capacitance CL H-output voltage VQH L-output voltage VQL 15 ns 50 pF 2.4 0.4 V IQH = – 2.5 mA V IQL = 5 mA Output Clock LL3X/Reference Clock: LLIN (refer to figure 9a) Period TLL3X 68 74 H-pulse width tWH 25 ns L-pulse width tWL 25 ns Clock skew *) tSK 0 Load capacitance CL H-output voltage VQH L-output voltage VQL ns 50 pF 0.4 140 ns 15 2.4 *) With steady-state PLL. Semiconductor Group 80 V IQH = – 2.5 mA V IQL = 5 mA SDA 9220-5 Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Clock SCA/Reference Clock: LL1.5X (refer to figure 9a) H-pulse width tWH 10 L-pulse width tWL 10 Clock skew **) tSK 0 Load capacitance CL H-output voltage VQH L-output voltage VQL Period TSCA1 34 TSCA2 ***) TSCA3 ***) 25 ns ns 15 ns 50 pF V IQH = – 2.5 mA 0.4 V IQL = 5 mA 37 40 ns Normal mode with standard conversion 68 74 80 ns Normal mode without standard conversion or zoom mode with standard conversion 136 148 160 ns Zoom mode without standard conversion 2.4 Output Clock SCAD/Reference Clock: LL3X (refer to figure 9a) Period TSCAD 34 37 40 ns H-pulse width tWH 12 ns L-pulse width tWL 12 ns Clock skew *) tSK – 15 Load capacitance CL H-output voltage VQH L-output voltage VQL 0 ns 50 pF 2.4 0.4 V IQH = – 2.5 mA V IQL = 5 mA *) With steady-state PLL and provided that the capacitive load of the reference clock is identical or more. **) With steady-state PLL and provided that the capacitive load of the reference clock is identical or less. ***) TSCA2/3 are generated from TSCA1 (by blanking the high phases). Semiconductor Group 141 SDA 9220-5 Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Signals: BLN2, FRM, ZM, HS2, VS2/Reference Clock: LL1.5X (refer to figure 9b) Delay time (for HS2, VS2) tQD 20 ns Delay time (for BLN2, FRM, ZM) tQD 25 ns Hold time tQH Load capacitance CL H-output voltage VQH L-output voltage VQL 6 ns 30 2.4 0.4 pF V IQH = – 2.5 mA V IQL = 5 mA Output Signals: WT, RB, CSY, VS1, MUX, DREQ, CFH/Reference Clock: LL3X (refer to figure 9b) Delay time tQD Hold time tQH Load capacitance for WT, RB CL 50 pF Load capacitance for CSY, VS1, DREQ, CFH CL 30 pF H-output voltage VQH L-output voltage VQL 25 6 ns ns 2.4 0.4 V IQH = – 2.5 mA V IQL = 5 mA Output Signals: RA/Reference Clock: SCA (refer to figure 9b) Delay time tQD Hold time tQH Load capacitance CL H-output voltage VQH L-output voltage VQL Semiconductor Group 15 0 ns ns 50 2.4 0.4 142 pF V IQH = – 2.5 mA V IQL = 5 mA SDA 9220-5 Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Signals: SAR, SAC, RE/Reference Clock: SCAD (refer to figure 9b) Delay time for SAR, SAC tQD 25 ns Delay time for RE tQD 20 ns Hold time tQH Load capacitance CL H-output voltage VQH L-output voltage VQL 6 ns 50 pF V IQH = – 2.5 mA 0.4 V IQL = 5 mA 2.4 PLL-Filter Currents Charge current ICH 80 250 µA VQL = 1.9 V Charge current ICH 70 250 µA VQL = 2.9 V Discharge current IDCH – 80 – 300 µA VQL = 1.9 V Discharge current IDCH – 70 – 300 µA VQL = 2.9 V Filter Elements (see figure 10a) CF1 ≈ 1.5 nF, RF ≈ 1.8 kΩ, CF2 ≈ 100 pF Crystal (see figure 10b) Nominal frequency fQ Effect of temperature and accuracy of adjustment ∆f/fQ Temperature range TA Load capacitance CL 33 ± 0.5 pF Resonant impedance ZR 60 Ω Equivalent parallel C CO 6.7500 0 70 °C 7 ± 20 % pF Crystal load Semiconductor Group MHz 0.1 143 mW SDA 9220-5 Figure 9 Timing Diagram (for characteristics of SDA 9220-5) Semiconductor Group 144 SDA 9220-5 a) Filter Circuitry b) Crystal Circuitry Figure 10 Circuit Configuration for Filter and Crystal Reset Behavior of SDA 9220-5 The circuitry has sensor logic for separately detecting values below the minimum supply level on the VDDA and the two VDD pins. A reset cycle is initiated whenever such values are detected; the reset time is preset by charging and discharging the pin capacitance of the reset input pin which is not normally connected. This time can be extended by connecting RESI with an external capacitance. The RESI pin can also be connected directly with a signal; a RES low level enables reset, a RES high level terminates the reset. The internal circuit reset status is output via reset RESQ and can then be used as an active low signal (low level = reset status). During the reset phase all the output clocks generated by MSC (LL1.5X, LL3X, SCA and SCAD) are kept at low level. Upon completion of the reset the SDA 9220-5 is in its basic (line-locked) mode. If no clock is applied to LLIN at this point of time, the VCO in the PLL oscillates at its free-running frequency (5–20 MHz) and enables all the output clocks derived from it. – Typical Control Values for the Reset System Initiation level for reset on VDD Low level on RESI High level on RESI VDDR VRIL VRIH < 3.9 V < 1.5 V > 2.3 V Output low level on RESQ Output high level on RESQ VQL VQH ≤ 0.4 V (IQL = 5 mA) ≥ 2.4 V (IQH = – 2.5 mA) Semiconductor Group 145 SDA 9220-5 Figure 11 Application Circuit for Eliminating Bottom Flutter Semiconductor Group 146 SDA 9220-5 Figure 12 Timing Diagrams, Horizontal Sync Signals for Standard Conversion Note: The figures indicate the number of LL3-clock periods Semiconductor Group 147 SDA 9220-5 Figure 13 Timing Diagrams, Horizontal Sync Signals without Standard Conversion Note: The figures indicate the number of LL3-clock periods Semiconductor Group 148 WTN: ––– Write operation delay 0 or 16 LL3X clocks ----- Write operation delay 1-14 or 17-30 LL3X clocks SDA 9220-5 Figure 14 Memory Basic Cycle for Normal Mode with Standard Conversion and 864 Pixels per Line Semiconductor Group 149 SDA 9220-5 Figure 15 Semiconductor Group 150 SDA 9220-5 Figure 16 Semiconductor Group 151 SDA 9220-5 Figure 17 Semiconductor Group 152 SDA 9220-5 Figure 18 Semiconductor Group 153 SDA 9220-5 Figure 19 Semiconductor Group 154 SDA 9220-5 Operation with Standard Conversion Figure 20a VS/VS2 Phase Relation for Mode A(α) A(α) B(β) B(β) and VS Edge in First BLN-Half Cycle (VNR Bit = 1) Semiconductor Group 155 SDA 9220-5 Figure 20b VS/VS2 Phase Relation for Mode A(α) A(α) B(β) B(β) and VS Edge in Second BLN-Half Cycle (VNR Bit = 1) Semiconductor Group 156 SDA 9220-5 Figure 21 Timing Diagram, CSY-Pulse Sequency B) C) *) **) Start of TV line 3 (1st field) or 316/266 (2nd field) before standard conversion (50/60 Hz) Start of TV line 3 of each field after standard conversion (100/120 Hz) Alternative Rising edge of CSY comes four LL3X cycles before falling edge of BLN2 Semiconductor Group 157 SDA 9220-5 Figure 22 Timing for I2C Bus Parameter Symbol Limit Values min. max. 100 Unit Clock frequency fSCL 0 Inactive time before start of new transmission tBUF 4.7 µs Hold time for start condition (after this time first clock pulse is generated) tHD; STA 4.0 µs Low clock phase tLOW 4.7 µs High clock phase tHIGH 4.0 µs Setup time for data tSU; DAT 250 ns Rise time for SDA and SCL signals tTLH 1 µs Fall time for SDA and SCL signals tTHL 300 ns Setup time for SCL clock in stop condition tSU; STO All values are referred to specified input levels VIH and VIL. Semiconductor Group 158 4.7 kHz µs