INFINEON SDA9206

s
ICs for Consumer Electronics
ADC with Built in Antialiasing filter and
Clock generation UnitS
ABACUS
SDA 9206
Data Sheet 1999-02-10
Edition 1999-02-10
This edition was realized using
the software system FrameMaker
Published by Siemens AG, Bereich
Halbleiter, Marketing-Kommunikation,
Balanstraße 73,
81541 München
© Siemens AG 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third
parties are concerned, liability is only
assumed for components, not for
applications, processes and circuits
implemented within components or
assemblies.
The information describes the type of
component and shall not be considered
as assured characteristics.
Terms of delivery and rights to change
design reserved.
For questions on technology, delivery
and prices please contact
the Semiconductor Group Offices in
Germany or the Siemens Companies and
Representatives worldwide
(see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest
Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators
known to you. We can also help you – get
in touch with your nearest sales office. By
agreement we will take packing material
back, if it is sorted. You must bear the
costs of transport.
For packing material that is returned to us
unsorted or which we are not obliged to
accept, we shall have to invoice you for
any costs incurred.
Components used in life-support devices or systems must be expressly
authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be
used in life-support devices or systems2
with the express written approval of the
Semiconductor Group of Siemens AG.
1 A critical component is a component
used in a life-support device or system
whose failure can reasonably be
expected to cause the failure of that
life-support device or system, or to
affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are
intended (a) to be implanted in the
human body, or (b) to support and/or
maintain and sustain human life. If
they fail, it is reasonable to assume
that the health of the user may be
endangered.
ICs for Consumer Electronics
ADC with Built in Antialiasing filter and
Clock generation UnitS
ABACUS
SDA 9206
Data Sheet 1999-02-10
SDA 9206
Revision History:
Current Version: 1999-02-10
Previous Version:
Page
Page
(in previous (in current
Version)
Version)
Subjects (major changes since last revision)
21
Update of Table 2 concerning Straight Binary
21
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Recommended Operating Conditions
Under this conditions the functions given in the circuit description are fulfilled. Nominal
conditions specify mean values expected over the production spread and are the
proposed values for interface and application. If not stated otherwise, nominal values will
apply at TA=25°C and the nominal supply voltage.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1999-02-10
Published by Siemens AG, Semiconductor Group
Copyright  Siemens AG 1999. All rights reserved.
Terms of delivery and right to change design reserved.
SDA 9206
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.2.1
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converter for YUV Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signal Amplification, Prefiltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Decimation Filters for YUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Output Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Coding for Straight Binary / Two’s Complement Mode . . . . . . . . . .
Clock Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Horizontal PLL (HPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vertical Sync Processing (only available for 1fh mode) . . . . . . . . . . . . . . . .
Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Circuit Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 47
4
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5
5.1
5.2
5.3
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Diagram Data Input/Output Referenced to the Clock CLK1 . . . . . . .
Timing Diagram Clock Skew CLK2 - CLK1 . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Data Output Delay:
DAT_OUT: Pins PAQ7...0, PBQ7...0, BLN, HS, H1I1, H2I2 and VS . . . . . .
6
15
15
15
15
16
16
18
20
21
21
23
25
26
27
27
27
28
29
42
52
52
52
53
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Semiconductor Group
5
1999-02-10
SDA 9206
ADC with Built in Antialiasing filter and
Clock generation UnitS
ABACUS
Preliminary Data
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS
Three equivalent CMOS A/D converters on chip
30 MHz sampling rate
8-Bit resolution
No external sample & hold required
P-MQFP-64-3
Internal clamping circuits for each of the ADCs
Internal amplification of input signals
can be set by I2C Bus
Internal pre-filtering of analog input signals
High performance decimation filters
Two data sampling modes (4:2:2 and 4:1:1)
3 output data interfaces
- CCIR 656 interface (8 wires)
- Parallel data interface (2 x 8 wires)
- Quasi Parallel data interface (8 + 4 wires)
Overflow and underflow I2C status bits
On-chip sync and clock generation
Separate SYNC input with clamping for sync and clock generation
(max. line frequency of SYNC input: 38 kHz)
positive and negative polarity of SYNC signal (switchable by I2C Bus)
Lock-in behavior can be set via I2C Bus
Frequency generator function possible with digitally adjustable frequency
Clock generation for single and double line input frequencies supported
(1fh / 2fh mode)
Vertical noise suppression and 50/60 Hz detection (for 1fh mode only)
Type
Ordering Code
Package
SDA 9206
Q67101-H5185-A704
P-MQFP-64-3
Semiconductor Group
6
1999-02-10
SDA 9206
•
•
•
•
I2C-Bus interface
P-MQFP-64-3
5 V supply voltage for input signals
3.3 V or 5 V supply voltage for output signals
1.2
General Description
The SDA 9206 is a single monolithic IC containing three separate 8-Bit A/D converters
for video (YUV) applications and a clock sync generator which is delivering the sample
clock for the A/D converters. It utilizes an advanced VLSI 0.5 µm CMOS process
providing 30 MHz sampling rates at 8-Bits.
The YUV processing consists of following functional blocks:
•
•
•
•
•
Analog input buffers and clamping circuits
Three 30 MHz A/D converters
Digital decimation filters
Delay compensation in Y-path
Output formatter and buffer
The clock sync generator consists essentially of the following functional blocks:
• Analog clamping
• 7-Bit A/D converter
• Sync processor with digital horizontal PLL, vertical sync processor
and pulse generator
• Clock generator with discrete timing oscillator, D/A converter,
analog PLL and divider, as well as a crystal oscillator
Semiconductor Group
7
1999-02-10
SDA 9206
Pin Configuration
X1
X2
V DDDTO
V DD
PBQ0
PBQ1
PBQ2
PBQ3
PBQ4
PBQ5
PBQ6
PBQ7
V SS
ADR0
SDL
SDA
1.3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
31
50
30
51
29
52
28
53
27
54
26
55
25
56
SDA 9206
24
57
23
58
22
59
21
60
20
61
19
62
18
63
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VADDY
V REFHY
AINY
V REFLY
VAGNDY
VADDU
V REFHU
AINU
V REFLU
VAGNDU
V ADDV
V REFHV
AINV
V REFLV
VAGNDV
RESIN
VSSDTO
V DDQ
VS
CLK2
CLK1
HS
VSSQ
TEST
EXSYN
VAGNDPA
VADDPA
VAGNDC
V REFLC
SYNC
V REFHC
VADDC
V DDQ
PAQ0
PAQ1
PAQ2
PAQ3
PAQ4
PAQ5
PAQ6
PAQ7
V SSQ
V SS
V DD
H2I2
BLN
RESOUTN
H1I1
UEP10457
Figure 1
Semiconductor Group
8
1999-02-10
SDA 9206
1.4
Pin Description
Pin No.
Symbol
Type
Description
22, 36
VSS
S
Supply ground (VSS) for digital parts
21, 45
VDD
S
Supply voltage (VDD) for digital parts
23, 55
VSSQ
S
Supply ground for output stages and input stages
32, 50
VDDQ
S
Supply voltage for output stages and
input stages (3.3 V / 5 V)
1
VADDY
S
Analog positive supply voltage of ADC AINY (5 V)
2
VREFHY
3
AINY
4
VREFLY
5
VAGNDY
S
Analog ground of ADC AINY
6
VADDU
S
Analog positive supply voltage of ADC AINU (5 V)
7
VREFHU
8
AINU
9
VREFLU
10
VAGNDU
S
Analog ground of ADC AINU
11
VADDV
S
Analog positive supply voltage of ADC AINV (5 V)
12
VREFHV
13
AINV
14
VREFLV
15
VAGNDV
S
Analog ground of ADC AINV
16
RESIN
I/TTL/pu
Reset input signal: active low
17
H1I1
Q/TTL
Pin function defined by I2C Bus:
Line frequent pulse output or
programmable digital control output
18
RESOUTN Q/TTL
Reset output signal: active low; reset for other ICs
19
BLN
Blanking signal output, high level indicates
active video line
Semiconductor Group
Reference voltage high of ADC AINY (4.2 V)
I/ana
Analog voltage input of ADC AINY input range
selectable via I2C Bus (subaddress 11H, YAMP)
Reference voltage low of ADC AINY (2.2 V)
Reference voltage high of ADC AINU (4.2 V)
I/ana
Analog voltage input of ADC AINU input range
selectable via I2C Bus (subaddress 12H, UAMP)
Reference voltage low of ADC AINU (2.2 V)
Reference voltage high of ADC AINV (4.2 V)
I/ana
Analog voltage input of ADC AINV input range
selectable via I2C Bus (subaddress 12H, VAMP)
Reference voltage low of ADC AINV (2.2 V)
Q/TTL
9
1999-02-10
SDA 9206
1.4
Pin Description (cont’d)
Pin No.
Symbol
Type
Description
20
H2I2
Q/TTL
Pin function defined by I2C Bus:
Line frequent pulse output or
programmable digital control output
24 ... 31
PAQ7 ... 0 Q/TTL
Data output Port A (see Data Format)
33
SDA
IQ
I2C-Bus data line
34
SCL
I
I2C-Bus clock line
35
ADR0
I/TTL/pd
I2C-Chip select
37 ... 44
PBQ7... 0 Q/TTL
Data output port B (see Data Format)
46
VDDDTO
S
Positive supply voltage of DTO (5 V)
47
X2
Q/ana
Crystal connection
48
X1
I/ana
Crystal connection (clock input)
49
VSSDTO
S
Ground of DTO
51
VS
Q/TTL
Vertical sync pulse output
52
CLK2
Q/TTL
Clock out: tristate / 6.75 / 13.5 / 27 MHz;
selectable via I2C
53
CLK1
Q/TTL
Clock out: tristate / 6.75 / 13.5 / 27 MHz;
selectable via I2C
54
HS
Q/TTL
Horizontal sync pulse output
56
TEST
I/TTL/pd
Input signal for test mode selection
(0 V: no test mode selected)
Leave unconnected or connect to VSS
57
EXSYN
I/TTL/pd
Input signal for test mode selection
(0 V: no test mode selected)
Leave unconnected or connect to VSS
58
VAGNDPA
Analog ground of analog PLL and DACs
59
VADDPA
Analog positive supply voltage of analog PLL
and DACs (5 V)
60
VAGNDC
Analog ground of ADC SYNC
61
VREFLC
Reference voltage low of ADC SYNC (2.2 V)
62
SYNC
Semiconductor Group
I/ana
SYNC input
Input range selectable via I2C Bus
(subaddress 11H, SYNAMP)
10
1999-02-10
SDA 9206
1.4
Pin Description (cont’d)
Pin No.
Symbol
63
VREFHC
Reference voltage high of ADC SYNC (4.2 V)
64
VADDC
Analog positive supply voltage of ADC SYNC (5 V)
S: supply,
I: input,
ana: analog,
1.5
Type
Q: output,
Description
TTL: digital (TTL)
pu: internal pullup-circuit,
pd: internal pulldown-circuit
Internal Pin Configuration
Pin 2, 4, 7, 9, 12, 14, 61, 63
V REFHY , V REFLY , V REFHU , V REFLU , V REFHV , V REFLV ,
V REFLC , V REFHC
PAD
UES10549
Figure 2
Pin 17, 18, 19, 20, 24...31, 37...44, 51, 52, 53, 54
H1I1, RESOUTN, BLN, H2I2, PAQ7...0, PBQ7...0, VS, CLK2,
CLK1, HS
PAD
UES10550
Figure 3
Semiconductor Group
11
1999-02-10
SDA 9206
Pin 16, 35, 56, 57
RESIN, ADR0, TEST, EXSYN
350 Ω
PAD
UES10551
Figure 4
Pin 33
SDA
350 Ω
PAD
UES10552
Figure 5
Pin 34
SCL
350 Ω
PAD
UES10553
Figure 6
Semiconductor Group
12
1999-02-10
SDA 9206
Pin 3, 8, 13, 62
AINY, AINU, AINV, SYNC
350 Ω
PAD
350 Ω
UES10554
Figure 7
Pin 47, 48
X2, X1
350 Ω
PAD X2
350 Ω
PAD X1
UES10555
Figure 8
Semiconductor Group
13
1999-02-10
SDA 9206
1.6
Block Diagram
V AGND V ADD
V REFHY
AINY
V REFLY
V REFHU
AINU
V REFLU
V REFHV
AINV
V REFLV
V REFHC
SYNC
V REFLC
Clamping
Circuit
Triple
8 Bit
30 MHz
ADC
V SS
Decimator
2:1
Decimator
Stage 1
2:1
Sync
Processing
V DD
V SSQ
Delay
V DDQ
8
Delay
Decimator
Stage 2
2:1
Decimator
Stage 3
2:1
Numerical
Clock PLL
Port A
Output
Formatter
8
Ι 2 C Bus
Port B
VS
HS
BLN
CLK2
CLK1
H1I1
H2I2
RESOUTN
RESIN
V DDDTO V SSDTO
X1
X2 V AGNDPA V ADDPA ADR0
SCL SDA
UEB10456
Figure 9
Semiconductor Group
14
1999-02-10
SDA 9206
2
System Description
2.1
A/D Converter for YUV Inputs
2.1.1 Introduction
The SDA 9206 implements 3 independent 8-Bit A/D converters.
Maximum conversion rate is 30 MHz.
2.1.2 Input Signal Amplification, Prefiltering
The amplification of the input signals can be adjusted via I2C Bus. An internal prefiltering
of the analog input signals is implemented. The typ. frequency response of the analog
antialiasing prefilter is shown in figure 10.
UED10458
0
dB
-10
-20
-30
-40
-50
-60
-70
10 0
5
10 1
5
MHz 10 2
Frequency
Figure 10
Frequency Response of the Analog Antialiasing Prefilter
Semiconductor Group
15
1999-02-10
SDA 9206
2.1.3 Clamping
The analog pins AINY, AINU, AINV are switched simultaneously to on chip generated
clamping levels by an on chip clamping pulse H2.
Analog Channel
Straight Binary
Code
Two’s Complement
Code
Components
AINY
0001 0000
1001 0000
Y
AINU, AINV
1000 0000
0000 0000
U, V
The external clamping capacitance is loaded by on chip current sources during
clamping. So loading time depends on the values of Cext cl .
2.1.4 Digital Decimation Filters for YUV
The data rates of digital YUV signals are reduced in decimation filters following the
A/D conversion. The overall performance of the decimation filters is tuned to the
requirements for TV signals.
In figure 11 the frequency response of the filter for the Y channel is shown. The input
sampling rate is 27 MHz, the output sampling rate is 13.5 MHz.
UED10459
10
dB
Amplitude
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 11
Magnitude Frequency Response of the Luminance Filter
The Input Sampling Frequency fS is 27 MHz
Semiconductor Group
16
1999-02-10
SDA 9206
The total frequency response of the decimator stages 1 and 2 of the UV channels for an
input sampling rate of 27 MHz and an output sampling rate of 6.75 MHz is shown in
figure 12.
UED10460
Amplitude
10
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 12
Magnitude Frequency Response for Chroma Signals (Decimator Stages 1 and 2)
The Input Sampling Frequency fS is 27 MHz
Semiconductor Group
17
1999-02-10
SDA 9206
The frequency response of the decimator filter stage 3 of the UV channels for an input
sampling rate of 6.75 MHz and an output sampling rate of 3.375 MHz is shown in
figure 13. The decimator stage 3 is active for 4:1:1 mode and can also be activated for
4:2:2 mode by I2C Bus (control bit UV3FIL).
UED10461
Amplitude
10
dB
0
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 13
Frequency Response of the Chroma Decimator Stage 3
The Input Sampling Frequency fS is 6.75 MHz
2.2
Data Output Formatter
Three output data formats can be selected via I2C Bus (control Bits FORMAT). One
format corresponds to CCIR 656 (8-Bit bus at a data rate of 27 MHz), an other format
makes available Y and UV data separately on 2 parallel 8-Bit buses for Y and UV at a
data rate of 13.5 MHz each. The third format is a 12-Bit bus with 8 connections for Y and
4 connections for multiplexed UV data.
Semiconductor Group
18
1999-02-10
SDA 9206
Output Quasiparallel Data
Pin
FORMAT = 10 or 11
(13.5 MHz)
Parallel Data CCIR 656
FORMAT = 01 FORMAT = 00
(13.5 MHz)
(27 MHz)
PAQ7 Y07
Y17
Y27
Y37
Y07
Y17
U07
Y07
V07
Y17
PAQ6 Y06
Y16
Y26
Y36
Y06
Y16
U06
Y06
V06
Y16
PAQ5 Y05
Y15
Y25
Y35
Y05
Y15
U05
Y05
V05
Y15
PAQ4 Y04
Y14
Y24
Y34
Y04
Y14
U04
Y04
V04
Y14
PAQ3 Y03
Y13
Y23
Y33
Y03
Y13
U03
Y03
V03
Y13
PAQ2 Y02
Y12
Y22
Y32
Y02
Y12
U02
Y02
V02
Y12
PAQ1 Y01
Y11
Y21
Y31
Y01
Y11
U01
Y01
V01
Y11
PAQ0 Y00
Y10
Y20
Y30
Y00
Y10
U00
Y00
V00
Y10
PBQ7 U07
U05
U03
U01
U07
V07
Z
Z
Z
Z
PBQ6 U06
U04
U02
U00
U06
V06
Z
Z
Z
Z
PBQ5 V07
V05
V03
V01
U05
V05
Z
Z
Z
Z
PBQ4 V06
V04
V02
V00
U04
V04
Z
Z
Z
Z
PBQ3 Z
Z
Z
Z
U03
V03
Z
Z
Z
Z
PBQ2 Z
Z
Z
Z
U02
V02
Z
Z
Z
Z
PBQ1 Z
Z
Z
Z
U01
V01
Z
Z
Z
Z
PBQ0 Z
Z
Z
Z
U00
V00
Z
Z
Z
Z
XAB: X: signal component
Z: Pin is in tristate mode.
A: sample number
B: bit number
The BLN signal marks the active part of the video line (see figure 14).
CLK1
BLN
PAQ
U0
PAQ, PBQ
Y0
Y0 / U0
V0
Y1
Y1 / V0
UED10462
Figure 14
Semiconductor Group
19
1999-02-10
SDA 9206
2.2.1 Output Coding for Straight Binary / Two’s Complement Mode
Straight binary or Two’s complement output coding is selectable for each separate signal
component (Y and UV) via I2C-Bus control bits YCODE and UVCODE.
For straight binary coding a special suppression of code 0 and code 255 is provided in
output format mode according CCIR 656.
Table 1
Output Coding
Step
AINY
AINU, AINV
OFL UFL Straight
Two’s
Bit Bit Binary
Complement
7654 3210 7654 3210
< VCU, V - 1.0 V
0
1
0 0 0 0 0 0 0 0 1 0 0 0 0 00 0
VCU, V - 1.0 V 0
VCU, V - 0.992 V 0
VCU, V - 0.984 V 0
0
0 0 0 0 0 0 0 0 1 0 0 0 0 00 0
0
0 0 0 0 0 0 0 1 1 0 0 0 0 00 1
2
VCY - 0.125 V
VCY - 0.117 V
VCY - 0.109 V
0
0 0 0 0 0 0 1 0 1 0 0 0 0 01 0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VCU, V + 0.984 V
VCU, V + 0.992 V
VCU, V + 1.0 V
VCU, V + 1.0 V
0
0
1 1 1 1 1 1 0 1 0 1 1 1 1 10 1
0
0
1 1 1 1 1 1 1 0 0 1 1 1 1 11 0
0
0
1 1 1 1 1 1 1 1 0 1 1 1 1 11 1
1
0
1 1 1 1 1 1 1 1 0 1 1 1 1 11 1
Underflow < VCY - 0.125 V
0
1
VCY + 1.859 V
VCY + 1.867 V
254
VCY + 1.875 V
255
Overflow > VCY + 1.875 V >
253
VCY, VCU, V: ext. clamping level during clamping at Cext cl on channel AINY
resp. AINU, AINV
Table 1 is valid for VREFL = 2.2 V and VREFH = 4.2 V, xAMP = 0000
Semiconductor Group
20
1999-02-10
SDA 9206
Table 2
Output Coding in Case of CCIR 656 Format, FORMAT = 00
Step
AINY
AINU, AINV
OFL UFL Straight
Two’s
Bit Bit Binary
Complement
7654 3210 7654 3210
< VCU, V - 1.0 V
0
1
0000 0001 1000 0000
VCU, V - 1.0 V 0
VCU, V - 0.992 V 0
VCU, V - 0.984 V 0
0
0000 0001 1000 0000
0
0000 0001 1000 0001
2
VCY - 0.125 V
VCY - 0.117 V
VCY - 0.109 V
0
0000 0010 1000 0010
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VCU, V + 0.984 V
VCU, V + 0.992 V
VCU, V + 1.0 V
VCU, V + 1.0 V
0
0
1111 1101 0111 1101
0
0
1111 1110 0111 1110
0
0
1111 1110 0111 1111
1
0
1111 1110 0111 1111
Underflow < VCY - 0.125 V
0
1
VCY + 1.859 V
VCY + 1.867 V
254
VCY + 1.875 V
255
Overflow > VCY + 1.875 V >
253
VCY, VCU,V: ext. clamping level during clamping at Cext cl on channel AINY
resp. AINU, AINV
Table 2 is valid for VREFL = 2.2 V and VREFH = 4.2 V, xAMP = 0000
2.3
Clock Sync Generation
The clock sync generator is a phase locked loop that locks on a horizontal SYNC input
signal and generates the clock signals as well as additional control output signals.
2.3.1 Horizontal PLL (HPLL)
The input signal SYNC may be either a CVBS signal or a composite sync signal. The
polarity of the SYNC signal can be both positive or negative (I2C-Bit SYPOL). The edges
of the SYNC input pulses should not be steeper than 100 ns. The frequency of the SYNC
signal can be of normal or double line frequency (I2C-Bit 2FH).
The SYNC is clamped before A/D conversion. For DC-input signals clamping can be
disabled (I2C-Bit CLOF). A/D conversion takes place with 7 bits and a nominal frequency
of 27 MHz.
The digital HPLL filters the signal with a cutoff frequency of 1 MHz (2 MHz for 2fh mode).
If 1fh mode is used the sampling frequency is decimated to 13.5 MHz. Following the low
pass filtering a black- and sync bottom- level measurement takes place in order to
calculate a threshold value. By means of this value the phase difference between the
HPLL output and the SYNC input pulse is determined. Using a digital PI filter an
increment is calculated from this for the Discrete Timing Oscillator (DTO). It is possible
Semiconductor Group
21
1999-02-10
SDA 9206
to adapt the nominal frequency of the DTO by means of 5 I2C-Bus bits (INC4...INC0)
such shifting the center frequency according to the momentary standard used.
For the different applications the following values of INC are allowed (values valid for
a crystal frequency of 24.576 MHz):
Application
FH [Hz]
2FH
YUV-ADCs
INC
PAL
15625
0
active
6
NTSC
15750
0
active
6
PAL (100 Hz/VGA) 31250
1
inactive
6
NTSC (120 Hz/VGA) 31500
1
inactive
6
ATV
32400
1
inactive
8
MUSE
33750
1
inactive
11
Macintosh
35000
1
inactive
14
VGA
38000
1
inactive
21
Note: A change of INC causes spontaneous changes of the generated clock
frequencies!
The DTO generates a saw-tooth with a frequency that is proportional to the increment.
The saw-tooth is converted into a sinusoidal clock signal by means of a D/A converter
and applied to an analog PLL which multiplies the frequency and minimizes residual
jitter.
By means of the I2C bits S1CL and S2CL the output frequency on pins CLK1 and CLK2
can be set. In this manner a clock is provided that is line-locked with the SYNC-input
signal. The ratio of these clock frequencies to the horizontal frequency of SYNC depends
only on the I2C-Bus bits S1CL, S2CL, HPLL and 2FH.
For the different modes the following values of S1CL and S2CL are allowed:
Mode
YUV-ADC 2FH
S1CL
S2CL
fCLK1
fCLK2
(MHz)
(MHz)
CCIR
enabled
0
11
11
27
27
CCIR
enabled
0
11
00
27
tristate
4:2:2, 4:1:1 enabled
0
11
11
27
27
4:2:2, 4:1:1 enabled
0
10
00
13.5
tristate
VGA
disabled
1
01
11
6.25 ... 8.75 25 ... 35
VGA
disabled
1
10
11
12.5 ... 17.5 25 ... 35
The digital horizontal PLL supplies a noise-suppressed horizontal pulse.
Semiconductor Group
22
1999-02-10
SDA 9206
During 1fh mode (2FH = 0) the digital HPLL also supplies a noise-suppressed vertical
pulse obtained by digital integration of the main equalizing pulses. An integration time of
26.6 µs or 11.3 µs can be set by the I2C Bus. This functionality is switched off during 2fh
mode (2FH = 1).
2.3.2 Vertical Sync Processing (only available for 1fh mode)
Vertical sync processing consists of:
• 625/525 line detection
• vertical noise suppression
The vertical pulses are obtained from the SYNC signal by integration. The 625/525 line
detector measures the number of lines per field. By taking the average of the individual
measurements with two up/down counters, the status bits ’FF’ ad ’FFGF’ are obtained.
When vertical noise suppression is switched on (VOFF = 0), the vertical pulse obtained
from the SYNC signal by integration is admitted only within a preset window (refer to
timing diagram) and appears as a VS pulse. The width of the window can be set via the
I2C Bus.
In the temporary absence of vertical pulses in SYNC, a continuous VS can be generated
by switching on a ’flywheel mode’ (SCHW = 1) providing a number of lines per field of
312.5 or 262.5 respectively.
When interference to SYNC is heavy, missing vertical pulses can be supplemented by
switching on the flywheel mode and vertical interference can be eliminated by switching
on the noise suppression circuitry. Noise suppression and the flywheel mode can be
enabled independently of each other.
There is also the possibility of generating VS in the free-running mode. The VS pulses
are then completely independent of the vertical sync pulse in SYNC. When FREE = 1
and SCHW = 1, a VS pulse is generated every 262.5 or 312.5 lines (VF = 1 or 0
respectively). When FREE = 1 and SCHW = 0, a VS pulse is generated every 279 or 339
lines (VF = 1 or 0 respectively). Free-running generation of VS occurs every 262 or 312
in the terminal mode (TERM = 1).
Semiconductor Group
23
1999-02-10
SDA 9206
Non-Suppressed
Vertical Sync
from HPLL
Interference Pulse
xxx
Line Number
249
289
298 299 300
(199) (200)
(239) (240)
311 312
(249) (250)
(261) (262)
Vertical Sync
Closes
Window
Window
(VWIWI = 11)
Window
(VWIWI = 10)
Window
(VWIWI = 01)
Window
(VWIWI = 00)
VS
(noise-suppressed)
Suppression of Interference
Pulse not in Window
Numbers in Brackets for 525 Lines per Frame
UED10463
When missing Vertical Sync from HPLL:
Line Number
312 313
339
1
272
(262)
(279) (1)
(242)
VS
SCHW = 0
Windows
RC-Opening
(Independent from WWW Bit)
Numbers in Brackets for 525 Lines per Frame
UED10464
Figure 15
Window for Vertical Pulse Noise Suppression
Semiconductor Group
24
1999-02-10
SDA 9206
2.3.3 Pulse Generation
The clock sync generator supplies the following pulses:
•
•
•
•
HS
VS
BLN
Two clamping pulses H1 and H2. H2 is also the internal clamping pulse of
the YUV-ADCs.
• The HS pulse is 16 13.5 MHz clock periods long and can be shifted by the I2C-Bus in
increments of four 13.5 MHz clock periods.
• For the VS pulse refer to vertical noise suppression.
• With the BLN pulse the start time (high-to-low edge) and the stop time (low-to-high
edge) can be set within a certain range of lines in increments of 13.5 MHz clock
periods by I2C Bus. The timing of BLN does not change during
the field blanking interval.
• During the BLN pulse the Y-U-V output data are set to their clamping level.
• For pulse H1 the start time (low-to-high edge) and stop time can be set in increments
of two 13.5 MHz clock periods.
• For pulse H2 the start time (low-to-high edge) and stop time can be set in increments
of 13.5 MHz clock periods.
The timing of the BLN, H1, H2, VS and HS pulses can be set by the costumer using the
specified I2C-Bus bits. Figure 9 shows the ranges of those settings.
Reference Time
BURST
SYNC
approx. 2.6 µs
HS
HSON (-35.22 µ s ... 28.42 µ s)
approx. 1.2 µs
H1
H2
H1ON (-28.27 µ s ... 9.47 µ s)
H1OF (-28.27 µ s ... 9.47 µ s)
H2ON (-4.67 µ s ... 14.21 µ s)
H2OF (-4.67 µ s ... 14.21 µ s)
BON (-8.89 µ s ... 9.99 µ s)
BOF (0.59 µ s ... 19.46 µ s)
BLN
UET10465
All times are given in relation to the Reference Time!
All times are only valid for 2FH = 0. If 2FH = 1 all times have to be divided by two!
Figure 16
I2C-Bus Programming Areas of Horizontal-Frequency Pulses
Semiconductor Group
25
1999-02-10
SDA 9206
2.3.4 Miscellaneous Circuit Sections
To suppress bottom flutter in VCR mode, the frequency of the clock can be ’hold’ by
’freezing’ the increment of the HPLL. The vertical-frequency ’freezing-time’ starts a
number of lines (programmable by the I2C Bus) before the vertical pulse and then lasts
for a number (programmable) of lines. The settings do not depend on I2C-Bit TV. This
functionality is only available for the 1fh mode (2FH = 0).
VS
Line Number
of Half Picture
n-2
n
n-1
1
Start 0...15 Lines before VS
15
14
13
12
3
2
2
3
4
5
n = Number of Lines
in preceding Half Picture
1
0
Start
Range over which
Frequency Value
is Frozen
Stop
0
1
10
11
0...15 Lines Duration
12
13
14
15
(In this example the frequency value was frozen 13 lines before the VS pulse and for
a duration of 11 lines.)
UED10466
Figure 17
I2C-Bus Programming Area which Clock Frequency Value Generated by HPLL
can be Frozen
An active low reset signal for other chips is available at pin RESOUTN. It is activated
when the chip supply voltage VDD is switched on or when voltage glitches occur on it.
RESOUTN also is activated by pin RESIN. The RESOUTN pulse signal is not cancelled
until the crystal oscillator resonates and in addition stretched by an internal circuit for
approximately 127 lines (8 ms).
Semiconductor Group
26
1999-02-10
SDA 9206
2.4
I2C Bus
2.4.1 I2C-Bus Address
1 0 1 1 0 0 B
B: equal to the value set on pin ADR0
2.4.2 I2C-Bus Format
Write:
S 1 0 1 1 0 0 B 0 A
Subaddress
A
Data Byte
A
A
*****
P
Read:
S 1 0 1 1 0 0 B 1 A
···
Status Byte 0
A
Status Byte 1
**** Byte n A Data Byte (n+1) A
*****
A Data
****
NA P
Reading starts with status byte 0, followed by status byte 1 and then in succession by
data byte n, data byte n+1..., where n is the last write address. Specification of a
subaddress in reading mode is not possible.
S:
A:
P:
NA:
Start condition
Acknowledge
Stop condition
Not Acknowledge
An automatic address increment function is implemented.
After switching on the IC or RESIN = 0, all bits are set to defined states. Particularly:
Register
Default value
Register
Default value
00H
10H
0CH
00H
01H
40H
0DH
00H
02H
00H
0EH
00H
03H
00H
0FH
00H
04H
28H
10H
00H
05H
00H
11H
00H
06H
00H
12H
00H
07H
06H
13H
00H
08H
00H
14H
13H
09H
00H
15H
00H
0AH
00H
16H
00H
0BH
00H
17H
00H
Semiconductor Group
27
1999-02-10
SDA 9206
2.4.3 I2C-Bus Commands
Data Byte
Subadd.
D7
D6
D5
00H
0
UV3FIL
01H
YD3
02H
D2
D1
D0
FORMAT1 FORMAT0 UVCODE
YCODE
OENB
OENA
YD2
YD1
YD0
0
0
0
0
I2
I1
SELH2I2
SELH1I1
0
0
0
0
03H
0
0
0
0
CGSUP1
CGSUP0
VWIWI1
VWIWI0
04H
0
OEFB
S1CL1
S1CL0
S2CL1
S2CL0
0
0
05H
0
SCHW
HPLL
VTHRE
CLOF
0
0
0
06H
TV
FREE
VOFF
VF
TERM
GENMOD
0
SYPOL
07H
2FH
HSWMA
HSWMIN
INC4
INC3
INC2
INC1
INC0
08H
BON7
BON6
BON5
BON4
BON3
BON2
BON1
BON0
09H
BOF7
BOF6
BOF5
BOF4
BOF3
BOF2
BOF1
BOF0
0AH
H1ON7
H1ON6
H1ON5
H1ON4
H1ON3
H1ON2
H1ON1
H1ON0
0BH
H1OF7
H1OF6
H1OF5
H1OF4
H1OF3
H1OF2
H1OF1
H1OF0
0CH
H2ON7
H2ON6
H2ON5
H2ON4
H2ON3
H2ON2
H2ON1
H2ON0
0DH
H2OF7
H2OF6
H2OF5
H2OF4
H2OF3
H2OF2
H2OF1
H2OF0
0EH
HSON7
HSON6
HSON5
HSON4
HSON3
HSON2
HSON1
HSON0
0FH
0
0
0
0
0
0
0
0
10H
FION3
FION2
FION1
FION0
FILE3
FILE2
FILE1
FILE0
11H
SYNAMP3 SYNAMP2 SYNAMP1 SYNAMP0 YAMP3
YAMP2
YAMP1
YAMP0
12H
UAMP3
UAMP2
UAMP1
UAMP0
VAMP3
VAMP2
VAMP1
VAMP0
13H
DATDEL2
DATDEL1
DATDEL0
DATSLOP
CLKSLOP1 CLKSLOP0 0
0
14H
0
0
0
1
0
0
1
1
15H
0
0
0
0
0
0
0
0
16H
0
0
0
0
0
0
0
0
17H
0
0
0
0
0
0
0
0
Semiconductor Group
D4
D3
28
1999-02-10
SDA 9206
2.4.4 Detailed Description
Subaddress 00H
Bit
Name
Function
D7
0
Reserved
D6
UV3FIL
Filter stage 3 for UV data (FORMAT = 0X)
OFF
0:
1:
ON
Note: For FORMAT = 1X filter stage 3 for UV data is “on”
(UV3FIL = don´t care)
D5...D4
FORMAT Selection of output data interface:
00:
Output data format according CCIR 656 (8 wires at Port A)
01:
Parallel output data format (2 x 8 wires)
10:
Quasiparallel 12 wire interface
11:
Quasiparallel 12 wire interface
D3
UVCODE Coding of UV data:
Straight binary code
0:
1:
Two’s complement code
D2
YCODE
Coding of Y data:
Straight binary code
0:
1:
Two’s complement code
D1
OENB
Output enable port B:
Tristate
0:
1:
Port enabled
D0
OENA
Output enable port A:
Tristate
0:
1:
Port enabled
Semiconductor Group
29
1999-02-10
SDA 9206
Subaddress 01H
Bit
Name
Function
D7...D4
YD
Delay compensation in Y-signal path (13.5 MHz clocks):
0000:
... - 0.30 µs
0001
0010
0011
0100:
... 0 µs
:
:
1110
1111:
... 0.81 µs
D3...D0
0000
Reserved
Subaddress 02H
Bit
Name
Function
D7
I2
Voltage level of H2I2 output (SELH2I2 = 1):
0:
Low voltage at pin H2I2
1:
High voltage at pin H2I2
D6
I1
Voltage level of H1I1 output (SELH1I1 = 1):
Low voltage at pin H1I1
0:
1:
High voltage at pin H1I1
D5
SELH2I2
Function of pin H2I2:
H2 (line frequency, start and stop programmable)
0:
1:
I2 (low/high programmable)
D4
SELH1I1
Function of pin H1I1:
H1 (line frequency, start and stop programmable)
0:
1:
I1 (low/high programmable)
D3
0
Reserved
D2
0
Reserved
D1
0
Reserved
D0
0
Reserved
Semiconductor Group
30
1999-02-10
SDA 9206
Subaddress 03H
Bit
Name
Function
D7...D4
0000
Reserved
D3...D2
CGSUP
Suppression of black level disturbances caused by copy
guarded tapes
No function
00:
01:
Black level error is limited to + / - 32 (~ 27 mV)
10:
Black level error is limited to + / - 16 (~ 14 mV)
11:
Black level error is limited to + / - 8 (~ 7 mV)
D1...D0
VWIWI
Width of Window in Vertical Processing:
00:
Narrow window: open from line 312 for PAL and 262
for NTSC
01:
Window: open from line 300 for PAL and 250 for NTSC
10:
Window: open from line 290 for PAL and 240 for NTSC
11:
Very wide window: open from line 250 for PAL and
200 for NTSC
Subaddress 04H
Bit
Name
Function
D7
0
Reserved
D6
OEFB
Output enable for Featurebox signals BLN, HS and VS:
BLN, HS, VS outputs tristate
0:
1:
BLN, HS, VS outputs enabled (2FH = 0)
BLN, HS outputs enabled, VS output tristate (2FH = 1)
D5...D4
S1CL
Selection of clock frequency on pin CLK1:
00:
Tristate
01:
6.75 MHz
13.5 MHz
10:
11:
27 MHz
For the allowed values of S1CL refer to table chapter 2.3.1!
D3...D2
S2CL
Selection of clock frequency on pin CLK2:
00:
Tristate
01:
6.75 MHz
13.5 MHz
10:
11:
27 MHz
For the allowed values of S2CL refer to table chapter 2.3.1!
D1...D0
00
Semiconductor Group
Reserved
31
1999-02-10
SDA 9206
Subaddress 05H
Bit
Name
Function
D7
0
Reserved
D6
SCHW
Mode of vertical pulse generation:
No flywheel mode
0:
1:
Flywheel mode
D5
HPLL
Relationship between horizontal frequency in SYNC and default
frequency on CLK1 and CLK2:
0:
864
1:
858
D4
VTHRE
Minimum sync pulse length from which a vertical pulse is
detected:
0:
26.6 µs
1:
11.3 µs
D3
CLOF
Clamping of SYNC for clock generator:
Clamping on
0:
1:
Clamping off
D2...D0
000
Reserved
Semiconductor Group
32
1999-02-10
SDA 9206
Subaddress 06H
Bit
Name
Function
D7
TV
Selection of HPLL lock-in behavior:
0:
Optimum for VCR
1:
Optimum for SYNC from network
D6
FREE
Generation of V pulse:
V derived from SYNC
0:
1:
Free-running generation; vertical frequency is
determined by VF bit, VOFF bit is enabled, SCHW bit
should be set to 1
D5
VOFF
Vertical noise suppression:
0:
Noise suppression enabled
1:
No noise suppression
D4
VF
Number of lines per field:
312.5 or 312
0:
1:
262.5 or 262
Note: VF must be set to the number of lines present in SYNC for
fly-wheel and noise suppression modes. VF determines
the number of lines per field for the free-running or
terminal mode.
D3
TERM
Terminal mode:
FREE
TERM
SCHW
VF
Number of Lines
per Field generated
in Free-Running Mode
don’t care
don’t care
1
1
1
1
don’t care
don’t care
1
1
0
0
0
1
0
1
0
1
312
262
312.5
262.5
339
279
1
1
0
0
0
0
D2
GENMOD Clock generator mode
Normal PLL mode
0:
1:
Generator mode (fixed frequency output,
controlled by INC)
D1
0
Reserved
D0
SYPOL
SYNC polarity:
Negative sync signals (normal SYNC input)
0:
1:
Positive sync signals
Semiconductor Group
33
1999-02-10
SDA 9206
Subaddress 07H
Bit
Name
Function
D7
2FH
Selection of input frequency range:
0:
Normal line frequencies (around 15.6 kHz)
1:
Double line frequencies (31.2...38 kHz)
[YUV A/D converters are switched off]
D6
HSWMA
Maximum width of HSYNC (input SYNC):
6.2 µs for low FH-range
0:
3.1 µs for high FH-range (2FH = 1)
1:
9.0 µs for low FH-range
4.5 µs for high FH-range (2FH = 1)
D5
HSWMI
Minimum width of HSYNC (input SYNC):
3.0 µs for low FH-range
0:
1.5 µs for high FH-range (2FH = 1)
1:
1.7 µs for low FH-range
0.8 µs for high FH-range (2FH = 1)
D4...D0
INC
Nominal PLL output frequency: INC = 00110
For the allowed values of INC refer to table chapter 2.3.1!
Calculation of INC for low FH range:
f
INC = INT  ---h- * 110592 – 64 ,625
 f

q
for high FH range (2FH = 1):
f
INC = INT  ---h- * 55292 – 64 ,625
 f

q
Semiconductor Group
34
1999-02-10
SDA 9206
Subaddress 08H
Bit
Name
Function
D7...D0
BON
BLN start time in relation reference time
(refer to the following table and to timing diagram)
BON7...BON0
Number
13.5 MHz Cycles
Time (2FH = 0)
1000 0000
- (- 128) + 7
= 135
9.99 µs
...
...
...
...
1111 1111
- (- 1) + 7
=8
0.60 µs
0000 0000
- (0) + 7
=7
0.52 µs
0000 0001
- (+ 1) + 7
=6
0.44 µs
...
...
...
...
0111 1111
- (+ 127) + 7
= - 120
- 8.89 µs
Subaddress 09H
Bit
Name
Function
D7...D0
BOF
BLN stop time in relation to reference time:
(refer to the following table and to timing diagram)
BOF7...BOF0
Number
13.5 MHz Cycles
Time (2FH = 0)
0000 0000
(0) + 8
=8
0.59 µs
0000 0001
(+ 1) + 8
=9
0.67 µs
...
...
...
...
0111 1111
(+ 127) + 8
= 135
9.99 µs
1000 0000
(+ 128) + 8
= 136
10.06 µs
1000 0001
(+ 129) + 8
= 137
10.14 µs
...
...
...
...
1111 1110
(+ 254) + 8
= 262
19.39 µs
1111 1111
(+ 255) + 8
= 263
19.46 µs
Semiconductor Group
35
1999-02-10
SDA 9206
Subaddress 0AH
Bit
Name
Function
D7...D0
H1ON
H1 start time in relation to reference time:
(refer to the following table and to timing diagram)
H1ON7...H1ON0
Number
13.5 MHz Cycles
Time (2FH = 0)
1100 0000
- (- 64) x 2
= 128
9.47 µs
...
...
...
...
1111 1111
- (- 1) x 2
=2
0.15 µs
0000 0000
- (0) x 2
=0
0 µs
0000 0001
- (+ 1) x 2
=-2
- 0.15 µs
...
...
...
...
0111 1111
- (+ 127) x 2
= - 254
- 18.79 µs
1000 0000
- (+ 128) x 2
= - 256
- 18.94 µs
1000 0001
- (+ 129) x 2
= - 258
- 19.09 µs
...
...
...
...
1011 1111
- (+ 191) x 2
= - 382
- 28.27 µs
Subaddress 0BH
Bit
Name
Function
D7...D0
H1OF
H1 stop time in relation to reference time:
(refer to the following table and to timing diagram)
H1OF7...H1OF0
Number
13.5 MHz Cycles
Time (2FH = 0)
1100 0000
- (- 64) x 2
= 128
9.47 µs
...
...
...
...
1111 1111
- (- 1) x 2
=2
0.15 µs
0000 0000
- (0) x 2
=0
0 µs
0000 0001
- (+ 1) x 2
=-2
- 0.15 µs
...
...
...
...
0111 1111
- (+ 127) x 2
= - 254
- 18.79 µs
1000 0000
- (+ 128) x 2
= - 256
- 18.94 µs
1000 0001
- (+ 129) x 2
= - 258
- 19.09 µs
...
...
...
...
1011 1111
- (+ 191) x 2
= - 382
- 28.27 µs
Semiconductor Group
36
1999-02-10
SDA 9206
Subaddress 0CH
Bit
Name
Function
D7...D0
H2ON
H2 start time in relation to reference time:
(H2 is always used as clamping reference for the YUV ADCs)
(refer to the following table and to timing diagram)
H2ON7...H2ON0
Number
13.5 MHz Cycles
Time (2FH = 0)
0100 0000
- (- 192)
= 192
14.21 µs
...
...
...
...
0111 1111
- (- 129)
= 129
9.55 µs
1000 0000
- (- 128)
= 128
9.47 µs
1000 0001
- (- 127)
= 127
9.40 µs
...
...
...
...
1111 1111
- (- 1)
=1
0.07 µs
0000 0000
- (0)
=0
0 µs
0000 0001
- (+ 1)
=-1
- 0.07 µs
...
...
...
...
0011 1111
- (+ 63)
= - 63
- 4.67 µs
Semiconductor Group
37
1999-02-10
SDA 9206
Subaddress 0DH
Bit
Name
Function
D7...D0
H2OF
H2 stop time in relation to reference time:
(H2 is always used as clamping reference for the YUV ADCs)
(refer to the following table and to timing diagram)
H2OF7...H2OF0
Number
13.5 MHz Cycles
Time (2FH = 0)
0100 0000
- (- 192)
= 192
14.21 µs
...
...
...
...
0111 1111
- (- 129)
= 129
9.55 µs
1000 0000
- (- 128)
= 128
9.47 µs
1000 0001
- (- 127)
= 127
9.40 µs
...
...
...
...
1111 1111
- (- 1)
=1
0.07 µs
0000 0000
- (0)
=0
0 µs
0000 0001
- (+ 1)
=-1
- 0.07 µs
...
...
...
...
0011 1111
- (+ 63)
= - 63
- 4.67 µs
Subaddress 0EH
Bit
Name
Function
D7...D0
HSON
HS start time in relation to reference time:
(refer to the following table and to timing diagram)
HSON7...HSON0
Number
13.5 MHz Cycles
Time (2FH = 0)
1010 0000
- (- 96) x 4
= 384
28.42 µs
...
...
...
...
1111 1111
- (- 1) x 4
=4
0.30 µs
0000 0000
- (0) x 4
=0
0 µs
0000 0001
- (+ 1) x 4
=-4
- 0.30 µs
...
...
...
...
0111 0110
- (+ 118) x 4
= - 472
- 34.93 µs
0111 0111
- (+ 119) x 4
= - 476
- 35.22 µs
Semiconductor Group
38
1999-02-10
SDA 9206
Subaddress 0FH
Bit
Name
Function
D7...D0
0000 0000 Reserved
Subaddress 10H
Bit
Name
Function
D7...D4
FION
Start of clock frequency freezing in number of lines before
the vertical pulse (only valid for 2FH = 0):
0000:
0 (no freezing)
0001:
1
:
:
1111:
15
D3...D0
FILE
Duration of clock frequency freezing in number of lines:
0000:
0 (no freezing)
0001:
1
:
:
1111:
15
Subaddress 11H
Bit
Name
Function
D7...D4
SYNAMP Internal amplification of SYNC input signal.
Allowed values:
SYNAMP = 0000 : amplification 0 dB : SYNC input nom. 2 Vpp
SYNAMP = 0110 : amplification 6 dB : SYNC input nom. 1 Vpp
D3...D0
YAMP
Internal amplification of AINY input signal.
Allowed values:
YAMP = 0000 : amplification 0 dB : AINY input nom. 2 Vpp
YAMP = 0110 : amplification 6 dB : AINY input nom. 1 Vpp
Semiconductor Group
39
1999-02-10
SDA 9206
Subaddress 12H
Bit
Name
Function
D7...D4
UAMP
Internal amplification of AINU input signal.
Allowed values:
UAMP = 0000 : internal amplification 0 dB : AINU input nom. 2 Vpp
UAMP = 0110 : internal amplification 6 dB : AINU input nom. 1 Vpp
D3...D0
VAMP
Internal amplification of AINV input signal.
Allowed values:
VAMP = 0000 : amplification 0 dB : AINV input nom. 2 Vpp
VAMP = 0110 : internal amplification 6 dB : AINV input nom. 1 Vpp
Subaddress 13H
Bit
Name
Function
D7...D5
DATDEL
Programmable output delay for PAQ7...PAQ0, PBQ7...PBQ0,
BLN, HS, H1I1, H2I2, VS.
Allowed values:
000
001 (description see chapter 5.3)
D4
DATSLOP Adaptation of the output driver stages for PAQ7...PAQ0,
PBQ7...PBQ0, BLN, HS, H1I1, H2I2, VS.
Allowed values:
0 ... to be used only for 5 V output stage supply voltage
1 ... to be used only for 3.3 V output stage supply voltage and
FORMAT = 00
D3...D2
CLKSLOP Adaptation of the output driver stages for CLK1 and CLK2.
Allowed values:
00 ... to be used only for 5 V output stage supply voltage
10 ... to be used only for 3.3 V output stage supply voltage
D1...D0
00
Semiconductor Group
Reserved
40
1999-02-10
SDA 9206
Subaddress 14H
Bit
Name
Function
D7...D0
0001 0011 Reserved
Subaddress 15H
Bit
Name
Function
D7...D0
0000 0000 Reserved
Subaddress 16H
Bit
Name
Function
D7...D0
0000 0000 Reserved
Subaddress 17H
Bit
Name
D7...D0
0000 0000 Reserved
Semiconductor Group
Function
41
1999-02-10
SDA 9206
2.4.5 Read Mode
Status Byte 0
Bit
Name
Function
D7
CON
Absolute difference between the horizontal sync pulse in SYNC
and the HPLL:
0:
Larger than or equal to 32 system clock cycles
1:
Less than 32 system clock cycles
D6
THRELIM Absolute difference between the horizontal sync pulse in SYNC
and the HPLL:
0:
Larger than 8 system clock cycles
1:
Less than 8 system clock cycles for 8 or more
successive lines (i.e. HPLL well locked in)
D5, D4
FFGF, FF Identified number
of lines per field
(refer also to timing diagram
figure 16):
< N1
≥ N1 and ≤ N2
> N2 and < 287
≥ 287 and < N3
≥ N3 and ≤ N4
> N4
Status Bits
FFGF
FF
0
1
0
0
1
0
0
0
0
1
1
1
N1 to N4 depends on Control Bits VWIWI:
VWIWI1
0
0
1
1
D3
D2 ... D0
VWIWI0
0
1
0
1
N1
262
250
240
200
N2
264
275
285
312
N3
312
300
290
250
N4
314
325
335
362
don´t care
POR
Semiconductor Group
Status bit POR is set by power on reset or by activating the reset pin.
POR is reset after reading the status byte.
42
1999-02-10
SDA 9206
Status Byte 1
Bit
Name
D7...D6
Function
don´t care
D5
OFLY
Overflow detection of ADC for input AINY
D4
UFLY
Underflow detection of ADC for input AINY
D3
OFLU
Overflow detection of ADC for input AINU
D2
UFLU
Underflow detection of ADC for input AINU
D1
OFLV
Overflow detection of ADC for input AINV
D0
UFLV
Underflow detection of ADC for input AINV
Semiconductor Group
43
1999-02-10
SDA 9206
3
Absolute Maximum Ratings
Parameter
Storage temperature
Symbol
Tstg
Limit Values
Unit
min.
max.
- 40
125
°C
260
°C
sec
Soldering temperature Tsold
Soldering time
tsold
10
Input/output voltage
VI/Q
VSSQ - 0.3 V VDDQ + 0.3 V 1
Remark
Not valid for
I2C-Bus pins
Input/output voltage VI/Q, I2C
I2C-pins 33, 34 (SCL,
SDA)
VSSQ - 0.3 V 6 V
1
Power supply voltage VDD,
- 0.3
6
V
1.25
W
- 100
100
mA
All inputs/outputs
-1
1
kV
MIL STD 883C
method 3015-6,
100 pF, 1500 Ω
VADDx,
VDDQ,
VDDDTO
Total power dissipation Ptot
Latch-up protection
ESD protection
ESD
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Note: Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions or at any other condition
beyond those indicated in the operational sections of this specification is not
implied.
Semiconductor Group
44
1999-02-10
SDA 9206
3.1
Recommended Operating Conditions
Parameter
Symbol
Limit Values
Unit
min.
nom.
max.
0
25
70
°C
Analog supply voltage VADDx
4.75
5.0
5.25
V
Digital supply voltage VDD
4.75
5.0
5.25
V
Ambient temperature TA
Remark
Power Requirements
DTO supply voltage
VDDDTO
4.75
5.0
5.25
V
Output stage supply
voltage
VDDQ
4.75
5.0
5.25
V
5 V-Mode
3.0
3.3
3.6
V
3.3 V mode, only
to be used for
FORMAT = 00
VDD, diff - 0.25
0.25
V
Supply pins VADDx
H-input voltage
VIH
2.0V
VDDQ
1
L-input voltage
VIL
0
0.8
V
Supply voltage
differential
All TTL Inputs
I2C-Bus (Values are Referred to min. (VIH) and max. (VIL))
H-input voltage
VIH
0.7 x VDDQ
VDD
L-input voltage
VIL
0V
0.3 x VDDQ 1
SCL clock frequency
fSCL
0
400
kHz
Rise times
of SCL, SDA
tR
0.3
µs
Fall times
of SCL, SDA
tF
0.3
µs
Set-up time data
tSU, Dat
100
ns
Hold time data
tHD, Dat
0
ns
Bus free time before
start condition
tBuf
1.3
µs
Set-up time start
condition
tSU, Sta
0.6
µs
Hold time start
condition
tHD, Sta
0.6
µs
Semiconductor Group
45
1
1999-02-10
SDA 9206
3.1
Recommended Operating Conditions (cont’d)
Parameter
Symbol
Limit Values
min.
nom.
Unit
max.
SCL low time
tLow
1.3
µs
SCL high time
tHigh
0.6
µs
Load capacitance
Remark
400
pF
Reference Inputs for Analog Inputs AINY, AINU, AINV, SYNC
Reference voltage high VREFHx
3.2
4.2
4.7
V
VADDx = 5 V
Reference voltage low VREFLx
1.7
2.2
3.2
V
VREFHx VREFLx
1
YAMP, UAMP,
VAMP = 0000,
Prefiltering
see chapter 2.1.2
nF
AINY, AINU,
AINV each
Analog Inputs AINY, AINU, AINV
Input range
(Peak-Peak)
VIPP
2V
Required ext clamp
capacitance
Cext cl
100
Required signal
source resistance
RS
0
200
Ω
VREFHCVREFLC
1
SYNAMP = 0000
12
MHz
To avoid aliasing
SYNC Input for Sync and Clock Generation
Input range
(Peak-Peak)
VIPP
0.5 V
Input frequency
f
0
Required ext clamp
capacitance
Cext cl
Required signal
source resistance
RS
2V
100
nF
200
Ω
Inputs Crystal Connections X1, X2
Crystal frequency
fc
24.576
MHz
3.6
pF
Crystal Type Fundamental Crystal
Equivalent parallel C
CO
Crystal resonant
impedance
ZR
40
Ω
Pin capacitance
CI
10
pF
External capacitance Cext
Semiconductor Group
18
46
pF
Each
1999-02-10
SDA 9206
3.2
Characteristics (Assuming Recommended Operating Conditions)
Parameter
Symbol
Limit Values
min.
nom.
Unit
Remark
max.
Supply Currents
Analog supply current IADD
120
mA
Sum of all VADDx pins
Digital supply current IDD
40
mA
Sum of all
VDD pins + VDDDTO
40
mA
Sum of all VDDQ pins
Output stage supply
current
IDDQ
Reference Inputs for Analog Inputs AINY, AINU, AINV
Reference ladder
resistance
RREF
175
250
325
Ω
For each converter
between REFH and
REFL
520
Ω
For each converter
between REFH and
REFL
300
µA
VI = 0 V...VDDQ
Note: internal pullup/
pulldown-circuits
0.6
V
I = 4 mA
100
nA
AINY, AINU, AINV,
SYNC each
10
pF
AINY, AINU, AINV,
SYNC each
Reference Inputs for Analog Input SYNC
Reference ladder
resistance
RREF
280
400
All TTL Inputs
Input current
- 300
I2C Input/Output SDA
L-output voltage
VQL
Analog Inputs
Analog input leakage IAIN
current
Analog input
capacitance
- 100
CI
TTL Outputs Port A, Port B, VS, HS, BLN, H1, H2, RESOUTN (VDDQ = 3.3 V or 5 V)
L-output voltage
VQL
0
0.4
V
I = 1 mA
H-output voltage
VQH
2.4 V
VDDQ
1
I = - 0.5 mA
- 20
20
µA
VQ = 0 V...VDDQ
High impedance state IQZ
output current
Load capacitance
Semiconductor Group
Port A, Port B, VS,
HS, BLN
CL
25
47
pF
1999-02-10
SDA 9206
3.2
Characteristics (Assuming Recommended Operating Conditions) (cont’d)
Parameter
Symbol
Limit Values
min.
nom.
Output data delay time, tQD
referenced to CLK1
(not valid for ESOUTN)
Output data hold time, tQH
referenced to CLK1
(not valid for
RESOUTN)
6
Pin RESOUTN
Data delay/
data hold time
-
Unit
Remark
25
ns
DATDEL = 000
CL = 15 pF
5 V output stage
supply voltage,
DATSLOP = 0
35
ns
DATDEL = 000
CL = 25 pF
5 V output stage
supply voltage,
DATSLOP = 0
25
ns
DATDEL = 000
CL = 25 pF
3.3 V output stage
supply voltage,
FORMAT = 00
DATSLOP = 1
max.
ns
-
-
Asynchronous output
signal
Clock TTL Outputs CLK1, CLK2
L-output voltage
VQL
0
0.4
V
I = 1 mA
H-output voltage
VQH
2.4 V
VDD
1
I = - 0.5 mA
Load capacitance
CL
30
pF
Transition times
t R, t F
5
ns
5 V output stage
supply voltage,
CLKSLOP = 00
3.3 V output stage
supply voltage,
CLKSLOP = 10
Semiconductor Group
48
1999-02-10
SDA 9206
3.2
Characteristics (Assuming Recommended Operating Conditions) (cont’d)
Parameter
Symbol
Limit Values
min.
nom.
Unit
Remark
max.
Low time 13.5 MHz
tWL13
26
ns
13.5 MHz
High time 13.5 MHz
tWH13
26
ns
13.5 MHz
Low time 27 MHz
tWL27
10
ns
27 MHz
High time 27 MHz
tWH27
10
ns
27 MHz
Skew
tSK
-2
0
2
ns
CL,CLK1 = CL,CLK2
25
27
35
MHz
± 4.8% at 27 MHz
S1CL = 11, S2CL = 11
Frequency range
f
when PLL is locked at
SYNC input signal
Performance of A/D Conversion (8-Bit)
Test Conditions: ADC Clock = 27 MHz, DATDEL = 000, xAMP = 0000, VIPP = 2 Vpp
Sampling rate
Differential linearity
(DC)
27
DNLE
Integral linearity (DC) INLE
0.5
MHz
± 0.5
LSB
±1
LSB
±3
LSB
Clamping level
accuracy
CLA
Gain error (DC)
GE
±6
LSB
Gain matching error
(DC)
GME
±3
LSB
Differential gain
DG
3
%
Not tested
Differential phase
DP
3
deg
Not tested
Signal to noise ratio
at 4.4 MHz sinus
αS/N
dB
Without harmonics
dB
dB
dB
4.4 MHz fundamental
4.4 MHz fundamental
4.4 MHz fundamental
45
48
Harmonic Distortion
2./4. order
3. order
5./6. order
Semiconductor Group
- 42
- 42
- 48
49
1999-02-10
SDA 9206
4
Application Information
SDA
9251-2X
YI
4
YOUT
UI
Picture
Processor
3ADC
CSG
12
SDA 9253
16
8
SDA
9206
UOUT
12
27 MHz
VI
Display
Processor
Field
Mixer
SDA 9253
SDA
9290
SDA
9251-2X
CVBS /
SYNC
SDA
9270
SDA
9280
MSC
SDA 9220
SYNC
VOUT
4
SYNCOUT
UES10470
Figure 18
Application Circuit 1
27 MHz
YIN
12
12
UIN
VIN
CVBS
SYNC
CLK
SDA
9206
Scan Rate
Converter
YUV
Display
Provessor
HREF
SDA
9280
YUV
HIN
VIN
YOUT
UOUT
SDA
9255
VOUT
SYNCOUT
UES10471
Figure 19
Application Circuit 2
Semiconductor Group
50
1999-02-10
SDA 9206
L3
L2
+5 V
10 µH
L1
2.2 Hµ
R4
8.2 Ω /
2%
TL 431
D1
1
3
R3
2 62 Ω /
2%
R2
+
+
C 35
100 nF
C 54
100 nF
C 55
100 nF
C 56
100 nF
C 12
100 nF
100 nF
100 nF
100 nF
6.8 Ω / C 8
2% +
R1
1 µF
16 Ω /
C 51
2%
C 52
C7
1 µF
YIN
UIN
VIN
CVBS
SCL
SDA
C 11
10 µF
1
5
6
10
11
15
64
60
59
58
C 48
2
C 49
7
C 50
12
C 10
63
100 nF
100 nF
4
100 nF
9
C 53
100 nF 14
C9
100 nF
61
C6
100 nF
3
C5
100 nF
8
C4
100 nF
13
C3
100 nF
62
35
34
33
16
10 µH
V ADDY
V AGNDY
V ADDU
V AGNDU
V ADDV
V AGNDV
V ADDC
V AGNDC
V ADDPA
V AGNDPA
V DDQ
V SSQ
V DD
V SS
V DDQ
V SSQ
32
23
45
36
50
55
46
49
21
22
44
43
42
41
40
39
38
37
31
30
29
28
27
26
25
24
20
57
54
53
17
52
19
51
18
56
47
V DDDTO
V SSDTO
V DD
V SS
PBQ0
PBQ1
V REFHY
PBQ2
PBQ3
V REFHU
PBQ4
PBQ5
V REFHV
PBQ6
V REFHC
PBQ7
PAQ0
ABACUS PAQ1
SDA 9206 PAQ2
PAQ3
V REFLY
PAQ4
PAQ5
V REFLU
PAQ6
V REFLV
PAQ7
H2I2
V REFLC
EXSYN
AINY
HS
CLK1
AINU
H1I1
CLK2
AINV
BLN
SYNC
VS
RESOUTN
ADR0
TEST
SCL
X2
SDA
48
X1
RESIN
+ C 13
10 µF
C 14
100 nF
C 15
100 nF
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CLK1
H1I1
CLK2
BLN
VS
RESOUTN
C 2 18 pF
C 1 18 pF
Q1
24.576 MHz
UES10472
Figure 20
Application Circuit 3
Semiconductor Group
51
1999-02-10
SDA 9206
5
Waveforms
5.1
Timing Diagram Data Input/Output Referenced to the Clock CLK1
t WH
t WL
V QH
Clock CLK1
t THL
t TLH
V QL
V QH
Output Data
V QL
t QH
t QD
UET10467
Figure 21
5.2
Timing Diagram Clock Skew CLK2 - CLK1
T
t WH
t WL
V QH
CLK1
t THL
t SK
t WH
t TLH
V QL
t WL
V QH
CLK2
t THL
T
t TLH
V QL
UET10468
Figure 22
Semiconductor Group
52
1999-02-10
SDA 9206
5.3
Programmable Data Output Delay:
DAT_OUT: Pins PAQ7...0, PBQ7...0, BLN, HS, H1I1, H2I2 and VS
T
CLK1
DAT_OUT
Data valid
Data not valid
Data valid
tQH
t QD
UET10469
Figure 23
DATDEL
tQH; min.
tQD; max.
000
6 ns
25 ns
001
10 ns
29 ns
The delay times are valid for a clock rate of the analog PLL of 27 MHz.
Semiconductor Group
53
1999-02-10
SDA 9206
6
Package Outlines
+0.15
7˚ max
H
0.88 ±0.15
0.8
0.3
0.15 +0.08
-0.02
2.45 max
2 +0.1
-0.05
0.25 min
P-MQFP-64-3
(Plastic Metric Quad Flat Package)
12
0.2
0.1
C
M
A-B D C 64x
17.2
14
0.2 A-B D 64x
1)
0.2 A-B D H 4x
D
B
14 1)
17.2
A
64
1
Index Marking
1)
0.6 x 45˚
Does not include plastic or metal protrusions of 0.25 max. per side
GPM05250
Figure 24
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
54
1999-02-10