1-A DC Motor Driver TLE 4205 Overview Bipolar IC Features ● ● ● ● ● ● Max. driver current 1 A Integrated free-wheeling diodes Short-circuit proof to ground Inhibit ESD protected inputs Temperature range – 40 °C ≤ Tj ≤ 150 °C P-DIP-18-3 P-DSO-20-6 Type Ordering Code Package TLE 4205 Q67000-A9025 P-DIP-18-3 TLE 4205 G Q67006-A9114 P-DSO-20-6 Description TLE 4205 is an integrated power full-bridge DC-motor driver for a wide temperature range, as required in automotive applications for example. The circuit contains two power comparators that can be combined to a full-bridge circuit. For inductive loads there are integrated free-wheeling diodes to + VS and ground. The outputs are shortcircuit proof up to 18 V supply voltage to ground and turn off when overtemperature occurs. This IC is especially suitable for headlight-beam adjustment in automobiles. Semiconductor Group 1 1998-02-01 TLE 4205 TLE 4205 TLE 4205 G Q1 1 18 VS 2 17 Q2 3 16 GND 4 15 -Ι2 5 14 +Ι2 6 13 + Ι1 7 12 - Ι1 8 11 INH 9 10 GND must be connected to Pin 4 Q2 N.C. N.C. GND GND GND GND - Ι2 + Ι2 +Ι 1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VS Q1 N.C. GND GND GND GND N.C. ΙNH -Ι 1 AEP01318 AEP00636 Figure 1 Pin Configuration (top view) Semiconductor Group 2 1998-02-01 TLE 4205 Pin Definitions and Functions Pin No. Symbol Function 1 Q1 Output Q1 of channel 1; push-pull B output with DC short-circuit protection to ground. Integrated free-wheeling diodes to ground and the supply voltage. 2 VS Supply voltage VS; must be blocked to ground with a ceramic capacitor of at least 100 nF directly on the pins of the IC. 3 Q2 Output Q2 of channel 2; see pin 1. 4 GND Ground 5 – I2 Inverting input channel 2; to be wired according to general rules. 6 + I2 Non-inverting input channel 2; to be wired according to general rules. 7 + I1 Non-inverting input channel 1; see pin 6. 8 – I1 Inverting input channel 1; see pin 5. 9 INH Inhibit; the IC is passive when this pin is open or connected to ground. 10-18 GND Ground; must be connected to pin 4. Semiconductor Group 3 1998-02-01 TLE 4205 Pin Definitions and Functions (TLE 4205 G) Pin No. Symbol Function 1 Q2 Output 2 of channel 2; push-pull B output with DC short-circuit protection to ground. Integrated free-wheeling diodes to ground and the supply voltage. 2 N.C. Not connected 3 N.C. Not connected 4-7 GND Ground 8 – I2 Inverting input channel 2; to be wired according to general rules. 9 + I2 Non-inverting input channel 2; to be wired according to general rules. 10 + I1 Non-inverting input channel 1; see pin 9. 11 – I1 Inverting input channel 1; see pin 8. 12 INH Inhibit; the IC is passive when this pin is open or connected to ground. 13 N.C. Not connected 14-17 GND Ground 18 N.C. Not connected 19 Q1 Output Q1 of channel 1, see pin 1. 20 VS Supply voltage VS; must be blocked with a ceramic capacitor of at least 100 nF directly on the pins of the IC. Semiconductor Group 4 1998-02-01 TLE 4205 VS 2 (20) T1 7 + Ι1 (10) 8 - Ι1 (11) + 1 Q1 (19) - T2 Power Limiting for T1, T3 Temperature Protection 9 INH (12) T3 6 +Ι2 (9) 5 -Ι2 (8) + 3 Q2 (1) - T4 (4-7) 4, 10-18 (14-17) GND Figure 2 AEB00637 Block Diagram Semiconductor Group 5 1998-02-01 TLE 4205 Circuit Description The IC contains two amplifiers with typical open-loop gain of 80 dB at 500 Hz. The input stages consist of PNP-differential amplifiers. This produces a common-mode input range of 0 V to nearly VS and a maximum differential input voltage of VS. The IC is guarded against ground shorts by an SOA-protective circuit. The output transistors are turned off if the chip temperature exceeds approx. 160 °C. The IC can be turned off by an inhibit input, which very much reduces current consumption. VS (2) TLE 4205 +Ι2 -Ι2 - Ι1 (6) 10 k Ω 10 kΩ (1) (5) (8) (3) + Ι1 Q1 10 k Ω (7) 10 kΩ 30 k Ω 200 kΩ 10 k Ω (9) INH Figure 3 Q2 (4) GND (10-18) GND AES00665 Circuit Diagram Semiconductor Group 6 1998-02-01 TLE 4205 Absolute Maximum Ratings Tj = − 40 to 150 °C Parameter Supply voltage Differential input voltage Output current Supply current Ground current Input voltage Symbol Limit Values Unit Remarks min. max. VS VID – 0.3 45 V – – ± VS V ∆V6-5 or ∆V7-8 TLE 4205 ∆V8-9 or ∆V10-11 TLE 4205 G IQ IS IGND VI –1 1 A – 2.5 3 A – –3 2.5 A I2 – 15 VS V V5; V6; V7; V8 TLE 4205 V8; V9; V10; V11 TLE 4205 G Inhibit input VInh – 15 VS V V9 TLE 4205 V12 TLE 4205G Junction temperature Tj Tstg – 150 °C – – 50 150 °C – 6 32 V – – 40 105 °C Case temperature VS TC TC – 40 95 °C PDmax = 3 W; DIP PDmax = 3 W; SO Thermal resistance junction - ambient junction - case Rth JA Rth JC – – 60 15 K/W TLE 4205 K/W TLE 4205 Thermal resistance junction - ambient junction - case Rth JA Rth JC – – 65 20 K/W TLE 4205 G K/W TLE 4205 G Storage temperature Operating Range Supply voltage Case temperature Outputs pin 1 (19) and pin 3 (1) short-circuit proof to GND at VS ≤ 18 V for TLE 4205 (TLE 4205G) Semiconductor Group 7 1998-02-01 TLE 4205 Characteristics 6 V < VS < 18 V; – 40 °C < Tj < 150 °C Parameter Symbol Limit Values min. typ. max. Unit Test Condition General Open-circuit current consumption IS – 10 30 mA active, both outputs high Open-circuit current consumption IS – 10 100 µA inhibit Turn-ON dead time ref. to V9 OFF/ON td ON – 10 20 µs |I1,3| < 1 A TLE 4205 |I1,19| < 1 A TLE 4205 G Turn-OFF dead time ref. to V9 OFF/ON td OFF – 10 20 µs |I1,3| < 1 A TLE 4205 |I1,19| < 1 A TLE 4205 G Open-loop gain GVO 50 80 – dB f = 500 Hz VIO ∆VIO/∆T IIO II ∆II/∆T VIC – 7.5 – 7.5 mV RS = 10 kΩ; – 20 30 µV/K – – 75 – 75 mA – – 300 – 300 nA – – – 5 nA/K – – – VS – 2 V – Input common-mode range, negative VIC – – – 0.5 V – Power-supply rejection ratio PSSR – – 200 µV/V RS = 10 kΩ; Common-mode rejection ratio CMRR 70 80 – dB – Inputs Input zero voltage Input-voltage drift Input zero current Input current Input-current drift Input common-mode range, positive Semiconductor Group 8 1998-02-01 TLE 4205 Characteristics (cont’d) 6 V < VS < 18 V; – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. VSat U VSat L VFU – 1.35 1.5 V – 0.8 1.2 V – 1 1.5 V IQ = – 0.6 A IQ = 0.6 A IF = 0.6 A Forward voltage of free-wheeling diode VFL – 1 1.5 V IF = 0.6 A; Slew rate of VQ dVqdtr – 0.5 – V/µs – Switching threshold high VIH 2 – – V – Switching threshold low VIL – – 0.8 V – H-input current IIH IIH – 100 – µA – 0 – µA V9 = 5 V V9 = 0 V Outputs Saturation voltage Saturation voltage Forward voltage of free-wheeling diode Inhibit Input L-input current Note: VSat U = upper VSat L = lower Semiconductor Group 9 1998-02-01 TLE 4205 1000 µF 63 V ΙS 2 VS V9 V5 V6 Ι Ι NH 9 Ι - Ι2 5 Ι + Ι2 6 Ι - Ι1 8 Ι + Ι1 7 470 nF Ι Q1 1 TLE 4205 RL 3 Ι Q2 VQ1 VQ2 V8 V7 4, 10-18 Ι GND AES00638 Figure 4 Test Circuit 13.5 V 2 VΙ NH 9 V+ Ι1 7 8 V- Ι1 *) 100 µF + - 1 Amp 1 TLE 4205 V- Ι 2 V+ Ι 2 5 6 VQ1 100 nF 220 nF 1Ω 220 nF 1Ω M - 3 +Amp 2 VQ2 4, 10-18 AES00639 *) Value depends on load current and wiring inductivity Figure 5 Application Circuit Semiconductor Group 10 1998-02-01 TLE 4205 Forward Voltage of the Free-Wheeling Diodes versus Junction Temperature IED00955 1.6 V VF Start Point of the SOAProtection Circuit versus Junction Temperature Ι F = 0.6 A A 1.4 2.0 I VFU 1.2 VFL 1.0 IED00956 2.4 1.6 V S = 13.5 V 0.8 1.2 0.6 0.8 0.4 0.4 0.2 0 -40 0 40 80 ˚C 0 120 -40 0 V Sat Current Consumption versus Junction Temperature IED00957 IED00958 18 mA 16 I Q = 600 mA VS = 13.5 V 1.4 120 TJ Saturation Voltage versus Junction Temperature 1.6 V 80 ˚C 40 TJ IS VSat U 14 1.2 VS = 13.5 V 12 1.0 10 VSat L 0.8 8 0.6 6 0.4 4 0.2 2 0 -40 0 0 40 80 ˚C -40 120 40 80 ˚C 120 TJ TJ Semiconductor Group 0 11 1998-02-01 TLE 4205 Package Outlines P-DIP-18-3 (Plastic Dual In-line Package) 3.5 ±0.3 ~ 1.2 1.5 max 2.54 0.45 18 1 +0.1 4.2 max 0.5 min 7.6 ±0.2 0.25 18x 6.4 -0.2 7.6 +1.2 10 22.7 -0.2 9 0.4 max Index Marking GPD05035 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Semiconductor Group 0.25 +0.1 12 Dimensions in mm 1998-02-01 TLE 4205 1.27 0.35 x 8˚ ma 7.6 -0.2 1) +0.09 0.35 x 45˚ 0.23 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-20-6 (Plastic Dual Small Outline Package) 0.4 +0.8 +0.15 2) 0.2 24x 20 0.1 10.3 ±0.3 11 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 13 Dimensions in mm 1998-02-01