INFINEON HYB18T256800AC

Da ta Sh e et , V 0. 2 2, Fe b. 2 00 4
H YS72 T 320 00 GR (2 56 M B y t e )
H YS72 T 640 01 GR (5 12 M B y t e )
H YS72 T 640 20 GR (5 12 M B y t e )
DDR 2 Reg istered D IMM Modu les
M em or y P r od uc t s
N e v e r
s t o p
t h i n k i n g .
HYS72T32000GR, HYS72T64001GR
HYS72T64020GR
Preliminary Datasheet Rev. 0.22 (2.04)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
256 MByte & 512 MByte Modules
PC2-3200R /-4200R /-5300R
• Re-drive for all input signals using register
and PLL devices.
• 240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
• OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
• One rank 32Mb x 72, 64Mb x 72 and
two ranks 64Mb × 72 organizations
• Serial Presence Detect with E2PROM
• JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
• Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
• Based on JEDEC standard reference card
designs Raw Card “A”, “B” and “C”.
• Modules built with 256 Mb DDR2 SDRAMs in
60-ball FBGA chipsize packages
• Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Performance:
-5
-3.7
-3
Component Speed Grade on Module
Speed Grade Indicator
DDR2-400
DDR2-533
DDR2-667
Module Speed Grade
PC2-3200
PC2-4200
PC2-5300
Unit
Max. Clock Frequency @ CL = 3
200
200
200
MHz
Max. Clock Frequency@ CL = 4 & 5
200
266
333
MHz
1.0 Description
The INFINEON HYS72T32000GR, HYS72T64020GR and HYS72T64001 are low profile
Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available
in 32M x 72 (256 MByte), 2 x 32M x 72 (512 MByte) and 64M x 72 (512 MByte) organisation and
density, intended for mounting into 240 pin connector sockets.
The memory array is designed with 256Mbit Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
[email protected]
2
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber
Compliance Code
Description
SDRAM
Technology
PC2-3200 (DDR2-400):
HYS72T32000GR-5-A
PC2-3200R-33310-A
one rank 256 MB Reg. DIMM
HYS72T64020GR-5-A
PC2-3200R-33310-B
two ranks 512 MB Reg. DIMM
256 Mbit (x8)
256 Mbit (x8)
HYS72T64001GR-5-A
PC2-3200R-33310-C
one ranks 512 MB Reg.DIMM
256 Mbit (x4)
HYS72T32000GR-3.7-A
PC2-4200R-44410-A
one rank 256 MB Reg. DIMM
256 Mbit (x8)
HYS72T64020GR-3.7-A
PC2-4200R-44410-B
two ranks 512 MB Reg. DIMM
256 Mbit (x8)
HYS72T64001GR-3.7-A
PC2-4200R-44410-C
one ranks 512 MB Reg.DIMM
256 Mbit (x4)
HYS72T32000GR-3-A
PC2-5300R-44410-A
one rank 256 MB Reg. DIMM
256 Mbit (x8)
HYS72T64020GR-3-A
PC2-5300R-44410-B
two ranks 512 MB Reg. DIMM
256 Mbit (x8)
HYS72T64001GR-3-A
PC2-5300R-44410-C
one ranks 512 MB Reg.DIMM
256 Mbit (x4)
PC2-4200 (DDR2-533):
PC2-5300 (DDR2-667):
Notes:
1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 72T32000GR-5-A, indicating
Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
section 8 of this datasheet.
2. The Compliance Code is printed on the module label and describes the speed grade, f.e. “PC2-4200R-44410-C”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “44410” means CAS latency = 4, trcd
latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card “C”.
1.2 Address Format
Part Number
DIMM
Density
Organization
Memory
Ranks
DDR2SDRAMs
HYS72T32000GR
256 MB
32Mb × 72
1
(256Mb)
32Mb × 8
9
13/2/10
HYS72T64020GR
512 MB
2 x 32Mb × 72
2
(256Mb)
32Mb × 8
18
13/2/10
HYS72T64001GR-
512 MB
64Mb x 72
1
(256Mb)
64Mb × 4
18
13/2/11
INFINEON Technologies
3
# of
# of row/bank/
SDRAMs
column bits
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.3 Components on Modules and RawCard
DIMM
Density
DRAM components
reference datasheet
PLL
Register
Raw Card
256 MB
HYB18T256800AC
1:10, 1.8V, CU877
1:1 25-bit 1.8V SSTU32864
A
512 MB
HYB18T256800AC
1:10, 1.8V, CU877
1:2 14-bit 1.8V SSTU32864
B
512 MB
HYB18T256400AC
1:10, 1.8V, CU877
1:2 14-bit 1.8V SSTU32864
C
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component
datasheet
1.4 Pin Definition and Function
Pin Name
Description
Pin Name
Description
A[12:0]
Row Address Inputs
CB[7:0]
DIMM ECC Check Bits
A11, A[9:0]
Column Address Inputs 4)
DQS[8:0]
SDRAM low data strobes
A10/AP
Column Address Input for AutoPrecharge
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
BA[1:0]
SDRAM Bank Selects
DQS[17:0]
SDRAM differential data strobes
CK0
Clock input
SCL
Serial bus clock
SDA
Serial bus data line
(positive line of differential pair)
CK0
Clock input
(negative line of differential pair)
RAS
Row Address Strobe
SA[2:0]
slave address select
CAS
Column Address Strobe
VDD
Power (+ 1.8 V)
WE
Read/Write Input
VREF
I/O reference supply
CS[1:0]
Chip Selects 3)
VSS
Ground
CKE[1:0]
Clock Enable 3)
VDDSPD
EEPROM power supply
ODT[1:0]
Active termination control lines 1) 3)
RESET
Register and PLL control pin 2)
DQ[63:0]
Data Input/Output
NC
No connection
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 256Mb DDR2 components only.
INFINEON Technologies
4
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.5 Pin Configuration
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
RESET
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3
DQS3
VSS
DQ26
DQ27
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
VSS
DQ4
DQ5
VSS
DM0, DQS9
DQS9
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1, DQS10
DQS10
VSS
NC
NC
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2, DQS11
DQS11
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3, DQS12
DQS12
VSS
DQ30
DQ31
VSS
61
62
63
64
A4
VDDQ
A2
VDD
KEY
VSS
VSS
VDD
NC
VDD
A10/AP
BA0
VDDQ
WE
CAS
VDDQ
CS1
ODT1
VDDQ
VSS
DQ32
DQ33
VSS
DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
181
182
183
184
VDDQ
A3
A1
VDD
KEY
CK0
CK0
VDD
A0
VDD
BA1
VDDQ
RAS
CS0
VDDQ
ODT0
NC
VDD
VSS
DQ36
DQ37
VSS
DM4, DQS13
DQS13
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5, DQS14
DQS14
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
INFINEON Technologies
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
5
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Pin Configuration (cont’d)
PIN#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
VSS
CB0
CB1
VSS
DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
NC
NC
VDDQ
A11
A7
VDD
A5
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
CB4
CB5
VSS
DM8, DQS17
DQS17
VSS
CB6
CB7
VSS
VDDQ
NC, CKE1
VDD
NC
NC
VDDQ
A12
A9
VDD
A8
A6
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VSS
SA2
NC
VSS
DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NC
NC
VSS
DM6, DQS15
DQS15
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7, DQS16
DQS16
VSS
DQ62
DQ63
VSS
VDDSPD
SA0
SA1
1.6 Pin Locations
Front
p in 1
pin 1 21
64
18 4
65
1 85
120
2 40
Backside
240 pin Modules (MO-237)
INFINEON Technologies
6
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.7 Registered DIMM Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK0
Input
The system clock inputs. All address and command lines are sampled on the cross point of
Cross point the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE[1:0]
Input
CKE high activates and CKE low deactivates internal clock signals and device input buffers
Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CS[1:0]
Input
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations conActive Low tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on
the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except
CK, ODT and Chip select) remain in the previous state.
ODT[1:0]
RAS, CAS,
WE
Input
Active High On-Die Termination control signals
Input
sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
Active Low When
be executed by the SDRAM.
Input
Active High Masks write data when high, issued concurrently with input data.
DM[8:0]
BA[1:0]
A[12:0]
DQ[63:0],
CB[7:0]
-
Selects which internal SDRAM memory bank is activated
Input
-
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
I/O
-
Data and Check Bit Input /Output pins.
Input
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
DQS[17:0],
DQS[17:0]
I/O
SA[2:0]
Input
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
SDA
I/O
-
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup.
SCL
Input
-
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
RESET
Input
-
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the
register(s) will be set to low level. The PLL will remain synchronized with the input clock.
VDD, VSS
Supply
-
Power and ground for the DDR SDRAM input buffers and core logic.
VREF
Supply
-
Reference voltage for the SSTL-18 inputs.
VDDSPD
Supply
-
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
INFINEON Technologies
7
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
2.0 Block Diagrams (cont’d)
2.1 One Rank 32M x 72 (256 MByte) DDR2 SDRAM DIMM Module (x8 components)
HYS72T32000GR on Raw Card A
RS0
DQS0
DQS4
DQS0
DM0/DQS9
DQS4
DM4/DQS13
NU/
RDQS
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS5
DQS1
DM1/DQS10
DQS5
DM5/DQS14
NU/
RDQS
DQS10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS
DQS
DQS2
DQS6
DQS6
DM6/DQS15
NU/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DQS
D2
DQS7
DQS7
DM7/DQS16
NU/
RDQS
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DM/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
0
1
2
3
4
5
6
7
DQS
CS DQS DQS
D5
0
1
2
3
4
5
6
7
NU/
RDQS
DQS16
CS DQS
D4
0
1
2
3
4
5
6
7
NU/
RDQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQS15
DQS3
DM3/DQS12
DQS12
NU/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS14
DQS0
DM2/DQS11
DQS11
NU/
RDQS
DQS13
CS DQS
DQS
D6
DM/
RDQS
CS DQS
DQS
D7
DQS8
DQS8
DM8/DQS17
NU/
RDQS
DQS17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0 *
B A 0-BA1
A0 -A12
RAS
CAS
WE
CKE0
ODT0
RESET
PCK7
PCK 7
1:1
R
E
G
I
S
T
E
R
DM/
RDQS
Serial PD
CS DQS DQS
SCL
D8
SDA
WP A0
RS0 -> C S : SDRAMs D0-D8
RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0 -D8
RA0 -RA 12-> A0 -A 12: SDR A Ms D0 -D 8
RR A S -> RAS : SD RAMs D0- D 8
RC AS -> C A S: SD RAMs D0-D8
RW E -> WE : SD RAMs D0-D8
RCK E0 -> CKE : SDR A
D0-D8
RODT0 -> ODT 0: SDRAMs D0-D8
A1
A2
SA0 SA1 SA2
CK0
CK 0
RESET
P
L
L
OE
VDDSPD
Serial PD
VDD, V DDQ
D0 - D8
VREF
D0 - D8
V SS
D0 - D8
PCK0-PCK6,PCK8,PCK9
PCK0-PCK6,PCK8,PCK9
CK : SDRAMs D0-D8
CK : SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 > CK : Register
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. Unless otherwise noted, resistor values are 22 Ohms
RST
*) CS0 connects to DCS and VDD connects to CSR on the Registers
INFINEON Technologies
8
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Block Diagrams (cont’d)
2.2 64M x 72 (512 MByte) two rank DDR2 SDRAM DIMM Modules (x8 components)
HYS72T64020GR on Raw Card B
RS1
RS0
DQS0
DQS4
DQS0
DM0/DQS9
DQS4
DM4/DQS13
NU/
RDQS
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
NU/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D0
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DQS5
DQS1
DM1/DQS10
DQS5
DM5/DQS14
NU/
RDQS
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
DQS
NU/
RDQS
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
CS DQS
DQS2
DQS6
DQS6
DM6/DQS15
NU/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS
DQS
NU/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D2
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
DQS3
DQS7
DQS7
DM7/DQS16
NU/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS DQS
NU/
RDQS
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
CS DQS
DQS
NU/
RDQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
DM/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CS DQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
CS DQS
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
DM/
RDQS
NU/
RDQS
CS DQS DQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7
CS DQS DQS
D14
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
CS DQS DQS
D13
0
1
2
3
4
5
6
7
NU/
RDQS
DQS
DM/
RDQS
0
1
2
3
4
5
6
7
NU/
RDQS
DQS
D5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS16
NU/
RDQS
CS DQS DQS
D4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU/
RDQS
DQS15
DQS3
DM3/DQS12
DQS12
NU/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS14
DQS
DQS0
DM2/DQS11
DQS11
NU/
RDQS
DQS13
CS DQS
DQS
D15
DM/
RDQS
0
1
2
3
4
5
6
7
CS DQS DQS
D16
DQS8
DQS8
DM0/DQS17
NU/
RDQS
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0 *
CS1 *
B A 0-BA1
A0 -A12
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RESET
PCK7
PCK 7
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1:2
R
E
G
I
S
T
E
R
CS DQS
D8
DQS
NU/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DM/
RDQS
0
1
2
3
4
5
6
7
VDDSPD
Serial PD
VDD, V DDQ
D0 - D17
VREF
D0 - D17
CS DQS DQS
D17
V SS
D0 - D17
Serial PD
SCL
SDA
WP A0
RS0 -> C S : SDRAMs D0-D8
RS1 -> C S : SDRAMs D9-D17
RB A0 -RBA1 -> B A 0-BA1 : SDRAMs D0-D17
RA0 -RA 12-> A0 -A 12: SDR A Ms D0-D17
RR A S -> RAS : SD RAMs D0-D17
RC AS -> C A S: SD RAMs D0-D17
RW E -> WE : SD RAMs D0-D17
RCK E0 -> CKE :SDRAMs D0-D8
RCK E1 -> CKE :SDRAMs D9-D17
RODT0 -> ODT : SDRAMs D0-D8
A1
A2
SA0 SA1 SA2
PCK0-PCK6, PCK8,PCK9
CK 0
CK 0
RESET
P
L
L
OE
PCK0-PCK6,
PCK8,PCK9
CK : SDRAMs D0-D17
CK : SDRAMs D0-D17
:
PCK7 -> CK Register
PCK7 > CK : Register
RODT1 -> ODT : SDRAMs D9-D17
RST
DQ-to-I/O wiring may be changed within a byte
DQ/DQS/DQS, adress and control resistors are 22 Ohms
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register.
RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
INFINEON Technologies
9
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Block Diagrams (cont’d)
2.3 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Modules (x4 components)
HYS72T64001GR on Raw Card C
VSS
RS0
DQS0
DQS9
DQS9
DQS0
DM
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
CS DQS
0
1
2
3
DM
DQS
D0
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
DQ36
DQ37
DQ38
DQ39
I/O
I/O
I/O
I/O
DQ44
DQ45
DQ46
DQ47
I/O
I/O
I/O
I/O
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
CS DQS DQS
0
1
2
3
D9
0
1
2
3
D10
0
1
2
3
D11
0
1
2
3
D12
0
1
2
3
D13
DQS10
DQS10
DQS1
DQS0
DM
DQ8
DQ9
DQ10
DQ11
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D1
CS DQS
DQS11
DQS11
DQS2
DQS2
DM
DQ16
DQ17
DQ18
DQ19
I/O
I/O
I/O
I/O
DQ24
DQ25
DQ26
DQ27
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D2
CS DQS
DQS12
DM
DM
CS DQS DQS
0
1
2
3
D3
CS DQS
DQS13
DM
DQ32
DQ33
DQ34
DQ35
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D4
CS DQS
DM
DQ40
DQ41
DQ42
DQ43
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D5
CS DQS
0
1
2
3
DQS
D14
DQS15
DQS15
DQS6
DQS6
DM
DQ48
DQ49
DQ50
DQ51
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D6
CS DQS
0
1
2
3
D15
0
1
2
3
D16
0
1
2
3
D17
DQS
DQS16
DQS16
DQS7
DQS7
DM
DQ56
DQ57
DQ58
DQ59
I/O
I/O
I/O
I/O
DM
CS DQS DQS
0
1
2
3
D7
DQS8
DQS8
DQS17
DQS17
DM
CB0
CB1
CB2
CB3
I/O
I/O
I/O
I/O
CS DQS DQS
0
1
2
3
D8
CS DQS
DM
CS DQS
Serial PD
RST
DQS
DQS14
DQS14
DQS5
DQS5
R
E
G
I
S
T
E
R
DQS
DQS13
DQS4
DQS4
1:2
DQS
DQS12
DQS3
DQS3
CS0 *
B A 0-BA1
A0 -A12
RAS
CAS
WE
CKE0
ODT0
RESET
PCK7
PCK 7
DQS
RS0 -> C S : SDRAMs D0-D17
RB A0 -RBA1 -> BA 0-BA1 : SDRAMs
RA0 -RA 12-> A0 -A 12: SDR A Ms D0-D17
RRA S -> RAS : SD RAMs D0-D17
RCAS -> C A S: SD RAMs D0-D17
RW E -> WE : SD RAMs D0-D17
RCK E0 -> CKE : SDRAMs D0-D17
RODT0 -> ODT : SDRAMs D0-D17
*) CS0 connects to DCS of Register 1 and CSR of Register 2,
CSR of Register 1 and DCS of Register 2 connects to VDD
**) RESET, PCK7 and PCK7 connet to both Registers.
Other signals connect to one of two Registers.
INFINEON Technologies
SCL
SDA
WP A0
A1
A2
SA0 SA1 SA2
CK 0
P
L
L
RESET
OE
CK 0
DQS
DQS
VDDSPD
Serial PD
VDD, V DDQ
D0 - D17
VREF
D0 - D17
V SS
PCK0-PCK6,
PCK8,PCK9
PCK0-PCK6,
PCK8,PCK9
D0 - D17
CK : SDRAMs D0-D17
CK : SDRAMs D0-D17
PCK7 -> CK : Register
PCK7 > CK : Register
DQ-to-I/O wiring may be changed within per nibble
Unless otherwise noted, resistor values are 22 Ohms
10
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
3.0 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Voltage on any pins relative to VSS
VIN, VOUT
– 0.5
2.3
V
Voltage on VDD relative to VSS
VDD
– 1.0
2.3
V
Voltage on VDD Q relative to VSS
VDDQ
– 0.5
2.3
Storage temperature range
TSTG
-55
+100
o
C
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3.1 Operating Temperature Range
Parameter
Symbol
Limit Values
min.
max.
Unit
DIMM Module Operating Temperature Range (ambient)
TOPR
0
+55
o
C
DRAM Component Case Temperature Range
TCASE
0
+95
o
C
Notes
1-4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
min.
nom.
Unit
Notes
max.
Device Supply Voltage
VDD
1.7
1.8
1.9
V
-
Output Supply Voltage
VDDQ
1.7
1.8
1.9
V
1)
Input Reference Voltage
VREF
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2)
EEPROM Supply Voltage
VDDSPD
1.7
–
3.6
V
DC Input Logic High
VIH (DC)
VREF + 0.125
–
VDDQ + 0.3
V
DC Input Logic Low
VIL (DC)
– 0.30
–
VREF – 0.125
V
In / Output Leakage Current
IL
–5
–
5
µA
1
2
3
3)
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ.
For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.
INFINEON Technologies
11
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.0 IDD Specifications and Conditions
4.1 256MByte Registered Module HYS72T32000GR (one rank, nine components x8)
256 MByte HYS72T32000GR
Symbol
Parameter / Condition
IDD0 Operating Current
PC2-3200 “-5”
PC2-4200 “-3.7”
PC2-5300 “-3”
max.
max.
max.
700
828
957
Unit Note
1
mA
IDD1
Operating Current
745
873
1002
mA
1
IDD2P
Precharge PD Standby Current
286
369
453
mA
1
IDD2N
Precharge Standby Current
502
657
822
mA
1
IDD2Q
Precharge Quiet Standby Current
430
558
687
mA
1
IDD3P(0) Active PD Standby Current
367
477
597
mA
1
IDD3P(1) LP Active PD Standby Current
286
369
867
mA
1
IDD3N
Active Standby Current
520
648
777
mA
1
IDD4R
Operating Current Burst Read
790
963
1137
mA
1
IDD4W
Operating Current Burst Write
880
1098
1317
mA
1
IDD5B
Auto-Refresh Current (tRFCmin.)
970
1098
1227
mA
1
IDD5D
Auto-Refresh Current (tREFI)
304
387
471
mA
1
IDD6
Self-Refresh Current
36
36
36
mA
1
IDD7
Operating Current
1375
1548
1722
mA
1
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
4.2 512 MByte Registered Module HYS72T64020GR (two ranks, eighteen components x8)
512 MByte HYS72T64020GR
Symbol
Parameter / Condition
IDD0 Operating Current
PC2-3200 “-5”
PC2-4200 “-3.7”
max.
max.
PC2-5300 “-3”
max.
854
1021
1190
Unit Note
mA 1, 2
IDD1
Operating Current
899
1066
1235
mA
1, 2
IDD2P
Precharge PD Standby Current
440
562
686
mA
1, 3
IDD2N
Precharge Standby Current
872
1138
1424
mA
1, 3
IDD2Q
Precharge Quiet Standby Current
728
940
1154
mA
1, 3
IDD3P(0) Active PD Standby Current
602
778
974
mA
1, 3
IDD3P(1) LP Active PD Standby Current
440
562
686
mA
1, 3
IDD3N
Active Standby Current
908
1120
1334
mA
1, 3
IDD4R
Operating Current Burst Read
944
1156
1370
mA
1, 2
IDD4W
Operating Current Burst Write
1034
1291
1550
mA
1, 2
IDD5B
Auto-Refresh Current (tRFCmin.)
1126
1291
1460
mA
1, 2
IDD5D
Auto-Refresh Current (tREFI)
476
598
722
mA
1, 3
IDD6
Self-Refresh Current
72
72
72
mA
1, 3
IDD7
Operating Current
1529
1741
1955
mA
1, 2
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
INFINEON Technologies
12
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.3 512 Mbyte Registered Module HYS72T64001GR (one rank, eighteen components x4)
512 MByte HYS72T64001GR
Symbol
Parameter / Condition
IDD0 Operating Current
PC2-3200 “-5”
PC2-4200 “-3.7”
max.
max.
PC2-5300 “-3”
max.
1268
1480
1694
Unit Note
1
mA
IDD1
Operating Current
1358
1570
1784
mA
1
IDD2P
Precharge PD Standby Current
440
562
686
mA
1
IDD2N
Precharge Standby Current
872
1138
1424
mA
1
IDD2Q
Precharge Quiet Standby Current
728
940
1154
mA
1
IDD3P(0) Active PD Standby Current
602
778
974
mA
1
IDD3P(1) LP Active PD Standby Current
440
562
686
mA
1
908
1120
1334
mA
1
IDD3N
Active Standby Current
IDD4R
Operating Current Burst Read
1448
1750
2054
mA
1
IDD4W
Operating Current Burst Write
1628
2020
2414
mA
1
IDD5B
Auto-Refresh Current (tRFCmin.)
1808
2020
2234
mA
1
IDD5D
Auto-Refresh Current (tREFI)
476
598
722
mA
1
IDD6
Self-Refresh Current
72
72
72
mA
1
IDD7
Operating Current
2618
2920
3224
mA
1
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
INFINEON Technologies
13
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.4 IDD Measurement Conditions
Symbol
Parameter/Condition
IDD0
Operating Current - One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD),tRCD = tRCD(IDD),AL = 0, CL = CL(IDD);
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
IDD2P
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCK(IDD);
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD);
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD2Q
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD);
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Power-Down Current: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STAIDD3P(0) Active
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Power-Down Current: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STAIDD3P(1) Active
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
IDD3N
Active Standby Current: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD); tRP = tRP(IDD),CKE is HIGH; CS is high
between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD4R
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
IDD4W
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
IDD5B
Burst Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is
HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Distributed Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tREFI interval, CKE is LOW and CS
is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD6
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
IDD7
All Bank Interleave Read Current:
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is high between valid commands, Address bus
inputs are STABLE during DESELECTS; Data bus is SWITCHING.
2. Timing pattern:
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
- DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or
strobes.
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level
the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
INFINEON Technologies
14
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.5 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
Parameter
Symbol
-5
PC2-3200
-3.7
PC2-4200
-3
PC2-5300
4-4-4
Unit
3-3-3
4-4-4
CAS Latency
CL(IDD)
3
4
4
tCK
Clock Cycle Time
tCK(IDD)
5
3.75
3
ns
tRCD(IDD)
15
15
12
ns
tRC(IDD)
60
60
57
ns
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Active to Precharge Command
tRRD(IDD)
7.5
7.5
7.5
ns
tRASmin(IDD)
45
45
45
ns
tRASmax(IDD)
70000
70000
70000
ns
tRP(IDD)
15
15
12
ns
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command
period
Average periodic Refresh interval
tRFC(IDD)
75
75
75
ns
tREFI
7.8
7.8
7.8
µs
4.5 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
Unit
min.
typ.
max.
A6 = 0, A2 = 1
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
2.5
3
3.75
mA/DQ
A6 = 0, A2 = 1
10
12
15
mA/DQ
A6 = 1, A2 = 0
5
6
7.5
mA/DQ
IODTO
IODTT
note: For power consumption calculations the ODT duty cycle has to be taken into account
INFINEON Technologies
15
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only)
Symbol
tAC
Parameter
DQ output access time from CK / CK
tDQSCK DQS output access time from CK / CK
-5
DDR2 -400
Min
Max
− 600
− 500
-3.7
DDR2 -533
-3
DDR2 -667
Unit
Min
Max
Min
Max
+ 600
-500
+500
-450
+450
+ 500
−450
+450
-400
+400
ps
ps
tCH
CK, CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
CK, CK low-level width
tHP
Clock Half Period
tCK
Clock cycle time
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3
5000
8000
5000
8000
5000
8000
ps
CL = 4 & 5
5000
8000
3750
8000
3000
8000
ps
tIS
Address and control input setup time
600
-
600
-
tbd.
-
ps
tIH
Address and control input hold time
600
-
600
-
tbd.
-
ps
tDS
DQ and DM input setup time
400
-
350
-
300
-
ps
tDH
DQ and DM input hold time
400
-
350
-
300
-
ps
tIPW
Control and Addr. input pulse width (each input)
0.6
-
0.6
-
0.6
-
tCK
0.35
-
0.35
-
0.35
-
tCK
-
tACmax
-
tACmax
-
tACmax
ps
tLZ(DQ) DQ low-impedance from CK / CK
2*tACmin
tACmax
2*tACmin
tACmax
2*tACmin
tACmax
ps
tLZ(DQS) DQS low-impedance from CK / CK
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ps
-
350
-
300
-
250
ps
ps
tDIPW DQ and DM input pulse width (each input)
tHZ
Data-out high-impedance time from CK / CK
tDQSQ
DQS-DQ skew
(for DQS & associated DQ signals)
tQHS
Data hold skew factor
tQH
Data Output hold time from DQS
-
450
-
400
-
350
tHP-tQHS
-
tHP-tQHS
-
tHP-tQHS
-
tDQSS Write command to 1st DQS latching transition
WL
-0.25
WL
+0.25
WL
-0.25
WL
+0.25
WL
-0.25
WL
+0.25
tCK
tDQSL,H DQS input low (high) pulse width (write cycle)
0.35
-
0.35
-
0.35
-
tCK
tDSS
DQS falling edge to CLK setup time
(write cycle)
0.2
-
0.2
-
0.2
-
tCK
tDSH
DQS falling edge hold time from CLK
(write cycle)
0.2
-
0.2
-
0.2
-
tCK
tMRD
Mode register set command cycle time
2
-
2
-
2
-
tCK
tWPRE
Write preamble
0.25
-
0.25
-
0.35
-
tCK
tWPST Write postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read preamble
tRPST Read postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK
tRAS
Active to Precharge command
45
70000
45
70000
45
70000
ns
tRC
Active to Active/Auto-refresh command period
60
-
60
-
57
-
ns
tRFC
Auto-refresh to Active/Auto-refresh command
period
75
-
75
-
75
-
ns
INFINEON Technologies
16
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Symbol
tRCD
tRP
-5
DDR2 -400
Parameter
Active to Read or Write delay (with and without
Auto-Precharge) delay
-3.7
DDR2 -533
-3
DDR2 -667
Unit
Min
Max
Min
Max
Min
Max
15
-
15
-
12
-
ns
Precharge command period
15
-
15
-
12
-
ns
tRRD
Active bank A to Active bank B command
(1k page size)
7.5
-
7.5
-
7.5
-
ns
tCCD
CAS A to CAS B Command Period
2
-
2
-
2
-
tCK
tWR
Write recovery time
15
-
15
-
15
-
ns
tDAL
Auto precharge write recovery + precharge time WR+tRP
-
WR+tRP
-
WR+tRP
-
tCK
tWTR Internal write to read command delay
10
-
7.5
-
7.5
-
ns
tRTP
7.5
-
7.5
-
7.5
-
ns
2
-
2
-
2
-
tCK
6 - AL
-
6 - AL
-
6 - AL
-
tCK
2
-
2
-
2
-
tCK
tCK
Internal read to precharge command delay
tXARD
Exit power down to any valid command
(other than NOP or Deselect)
tXARDS
Exit active power-down mode to read command
(slew exit, lower power)
tXP
Exit precharge power-down to any valid command (other than NOP or Deselect)
tXSRD Exit Self-Refresh to read command
tXSNR Exit Self-Refresh to non-read command
tCKE
CKE minimum high and low pulse width
tOIT
OCD drive mode output delay
200
-
200
-
200
-
tRFC + 10
-
tRFC + 10
-
tRFC + 10
-
ns
3
-
3
-
3
-
tCK
0
12
0
12
0
12
ns
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
0 C - 85 C
-
7.8
-
7.8
-
7.8
85oC - 95oC
-
3.9
-
3.9
-
3.9
time clocks remain ON after CKE
tDELAY Minimum
asynchronously drops low
Periodic
tREFI Average
Refresh Interval
o
o
µs
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code
for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
tAOND
tAON
min.
max.
Units
2
2
tCK
DDR2-400/533
tAC(min)
tAC(max) + 1 ns
DDR2-667
tAC(min)
tAC(max) + 0.7 ns
tAC(min) + 2 ns
2 tCK + tAC(max) + 1 ns
ns
2.5
2.5
tCK
ns
ODT turn-on delay
ODT turn-on
tAONPD ODT turn-on (Power-Down Modes)
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
ns
tAC(min)
tAC(max) + 0.6 ns
tAOFPD
ODT turn-off delay (Power-Down Modes)
tAC(min) + 2 ns
2.5 tCK + tAC(max) + 1 ns
ns
tANPD
ODT to Power Down Mode Entry Latency
3
-
tCK
tAXPD
ODT Power Down Exit Latency
8
-
tCK
INFINEON Technologies
17
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
6.0 Serial Presence Detect Codes for Registered DIMM Modules
Speed
Grade
SPD Entry
Value
all
all
all
all
all
all
all
all
all
-5
-3.7
-3
-5
-3.7
-3
all
all
all
all
all
all
all
all
all
all
all
all
-5
-3.7
-3
-5
-3.7
-3
all
all
-5 & -3.7
-3
all
-5 & -3.7
-3
all
all
128
256
DDR2-SDRAM
13
10 / 11
1/2
x72
not used
SSTL_1.8
5 ns
3.7 ns
3 ns
0.6 ns
0.5 ns
0.45 ns
ECC
7.8 µs / SR
x8, x4
x8, x4
not used
4&8
4
5, 4, 3
not used
Reg. DIMM
see note 1
incl. weak driver
5 ns
3.7 ns
3 ns
0.6 ns
0.5 ns
0.45 ns
5 ns
0.6 ns
15 ns
12 ns
7.5 ns
15 ns
12 ns
45 ns
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks, Package and Height
Module Data Width
Not used
Module Interface Levels
Min. Clock Cycle Time at CAS Latency = 5
10
SDRAM Access Time from Clock at CL = 5
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration Type
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data Width
Not used
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
Not used
DIMM Type Information
SDRAM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 4
24
SDRAM Access Time from Clock at CL = 4
25
26
27
Min. Clock Cycle Time at CAS Latency = 3
SDRAM Access Time from Clock at CL = 3
Minimum Row Precharge Time (tRP)
28
29
Minimum Row Act. to Row Act. Delay (tRRD)
Minimum RAS to CAS Delay (tRCD)
30
31
Minimum RAS Pulse Width (tRAS)
Module Density (per rank)
INFINEON Technologies
Hex Value
HYS72T32000GR
Note:
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
18
0A
60
08
08
40
80
08
08
0D
0A
61
48
00
05
50
3D
30
60
50
45
02
82
08
08
00
0C
04
38
00
01
00
01
50
3D
30
60
50
45
50
60
3C
30
1E
3C
30
2D
40
HYS72T64001GR
Description
HYS72T64020GR
Byte#
0B
60
04
04
80
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Speed
Grade
SPD Entry
Value
-5
-3.7
-3
-5
-3.7
-3
-5
-3.7
-3
-5
-3.7
-3
all
-5
-3.7 & -3
all
0.60 ns
0.50 ns
0.45 ns
0.60ns
0.50 ns
0.45ns
0.40 ns
0.35 ns
0.30 ns
0.40 ns
0.35 ns
0.30 ns
15 ns
10 ns
7.5 ns
7.5 ns
not used
32
Address and Command Setup Time (tIS)
33
Address and Command Hold Time (tIH)
34
Data Input Setup Time (tDS)
35
Data Input Hold Time (tDH)
36
37
Write Recovery Time (tWR)
Internal Write to Read Command delay (tWTR)
38
39
40
41
Internal Read to Precharge delay (tRTP)
Not used
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
42
43
44
Min. Auto Refresh Command Cycle Time (tRFC)
Maximum Clock Cycle Time tck
Max. DQS-DQ Skew (tDQSQmax.)
45
Read Data Hold Skew Factor (tQHS)
46
47-61
62
63
PLL Relock Time
Reserved for “Delta Temperature in SPD”
SPD Revision
Checksum for Bytes 0 - 62
Hex Value
HYS72T32000GR
Note:
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
all
-5 & -3.7
-3
all
all
-5
-3.7
-3
-5
-3.7
-3
-5
-3.7
-3
60 ns
57 ns
75 ns
8 ns
0.35 ns
0.30 ns
0.25 ns
0.45 ns
0.40 ns
0.35 ns
15.0 µs
see note 1
Revision 1.0
7D
tbd.
tbd.
60
50
45
60
50
45
40
35
30
40
35
30
3C
28
1E
1E
00
00
3C
39
4B
80
23
1E
19
2D
28
23
0F
00
10
7E
tbd.
tbd.
C1
00
XX
XX
XX
XX
XX
FF
HYS72T64001GR
Description
HYS72T64020GR
Byte#
B6
tbd.
tbd.
64
Manufacturers JEDEC ID Code
INFINEON
65-71 Not used
not used
72
Module Assembly Location
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Date
Year/Week Code
95-98 Module Serial Number
Serial Number
99-127 Manufacturer’s Specific Data
blank
128-255 Open for Customer use
blank
Note 1 : Will be used for future SPD Code Revisions. For details of “Delta Temperature in SPD” see JEDEC ballot JC42.5 Item # 1468.
INFINEON Technologies
19
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.0 Package Outline
7.1 Raw Card A
Module Package
DDR2 Registered DIMM Modules Raw Card A
one physical rank, 9 components x8 organised
133.35 +- 0.15
2.7 max.
Register
30.0.
Front View
4.0
PLL
pin 1
64
120
65
63,0
5,175
5,175
55,0
1.27 +- 0.1
PCB warpage 0.40
5.0
Backside View
184
240
185
10.0
17.80
pin 121
3
3
Detail of Contacts B
5.0
2.50 +- 0.20
0.20 +- 0.15
Detail of Contacts A
3.8 typ.
0.75R
0.8 +- 0.05
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
20
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.2 Raw Card B
Module Package
DDR2 Registered DIMM Modules Raw Card B
two one physical rank, 18 components x8 organised
1 3 3.3 5 +- 0.15
4.0 m a x.
Register
Front View
30.0.
4 .0
PLL
p in 1
64
1 20
65
6 3,0
5,1 75
5 ,1 7 5
55 ,0
1 .27 +- 0.1
PCB warpage 0.40
5.0
Backside View
240
185
1 84
Register
10.0
17.80
pin 1 21
3
3
D e tail o f C o nta cts B
5 .0
2.50 +- 0.20
0.20 +- 0.15
D e ta il of C on tac ts A
3.8 typ.
0 .8
0 .75 R
+
- 0.05
1 .0
1 .5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
21
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.3 Raw Card C
Module Package
DDR2 Registered DIMM Modules Raw Card C
one physical rank, 18 components x4 organised
1 3 3.3 5 +- 0.15
4.0 m a x.
Register
Front View
30.0.
4 .0
PLL
p in 1
64
1 20
65
6 3,0
5,1 75
5 ,1 7 5
55 ,0
1 .27 -+ 0.1
PCB warpage 0.40
5.0
Backside View
240
185
1 84
Register
10.0
17.80
pin 1 21
3
3
D e tail o f C o nta cts B
5 .0
2.50 +- 0.20
0.20 +- 0.15
D e ta il of C on tac ts A
3.8 typ.
0 .8
0 .75 R
+
- 0.05
1 .0
1 .5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
22
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1
Example:
HYS
2
3
4
5
6
7
8
9
10
11
64
T
64
0
2
0
G
R
-5
-A
0 = standard
2 = dual die package
1
INFINEON Prefix
HYS for DIMM Modules
7
Product Variations
2
Module Data Width
64 = Non-ECC Modules
72 = ECC Modules
8
Package
3
DRAM Technology
9
Module Type
R = Registered DIMMs
U = Unbuffered DIMMs
DL = Small Outline DIMMs
4
Memory Density per I/O
32 = 32 Mb
64 = 64 Mb
128 = 128 Mb
256 = 256 Mb
10
Speed Grade
-5 = PC2-3200 (DDR2-400)
-3.7 = PC2-4200 (DDR2-533)
-3 = PC2-5300 (DDR2-667)
5
Raw Card Generation
0 = first generation
11
Die Revision
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
6
Number of Memory
Ranks
0 = One Rank
2 = Two Ranks
Multiplying “Memory Density per I/O” with “Module Data Width”
and dividing by 8 for Non-ECC and 9 for ECC modules gives the
overall module memory density in MBytes.
T = DDR2
G= BGA components
8.2 DDR2 Memory Components
1
Example:
HYB
2
3
4
5
6
7
8
9
18
T
256
40
0
A
C
-5
1
INFINEON
Component Prefix
HYB for DRAM Components
6
Product Variations
0 = standard
2
Power Supply Voltage
18 = 1.8 V Power Supply
7
Die Revision
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
3
DRAM Technology
T = DDR2
8
Package Type
C = BGA package
F = BGA package (lead and
halogen free)
4
Memory Density
256 = 256 Mb
512 = 512 Mb
1G = 1024Mb
9
Speed Grade
-5 =...DDR2-400
-3.7 =.DDR2-533
-3 =...DDR2-667
5
Memory Organisation
40 = x4, 4 data in/outputs
80 = x8, 8 data in/outputs
16 = x16, 16 data in/outputs
INFINEON Technologies
23
2.04