INTEGRATED CIRCUITS DATA SHEET 74AHC2G00; 74AHCT2G00 2-input NAND gate Product specification 2004 Jan 21 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 FEATURES DESCRIPTION • Symmetrical output impedance The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS device. • High noise immunity • ESD protection: The 74AHC2G/AHCT2G00 provides the 2-input NAND gate function. – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V – CDM EIA/JESD22-C101 exceeds 500 V. • Low power dissipation • Balanced propagation delays • SOT505-2 and SOT765-1 package • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC2G tPHL/tPLH propagation delay nA and nB to nY CI input capacitance CPD power dissipation capacitance per gate CL = 15 pF; VCC = 5 V CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2004 Jan 21 2 AHCT2G 3.5 3.6 ns 1.5 1.5 pF 17 18 pF Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L H L H H H L H H H L Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS 74AHC2G00DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 A00 74AHCT2G00DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 C00 74AHC2G00DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 A00 74AHCT2G00DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 C00 PACKAGE MATERIAL PINNING PIN 2004 Jan 21 SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 2Y data output 4 GND ground (0 V) 5 2A data input 6 2B data input 7 1Y data output 8 VCC supply voltage 3 CODE MARKING Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 handbook, halfpage 1A 1 8 VCC 1B 2 7 1Y handbook, halfpage 00 2Y 3 6 2B GND 4 5 2A 1 1A 2 1B 5 2A 6 2B 1Y 7 2Y 3 MNA712 MNA711 Fig.1 Pin configuration. handbook, halfpage 1 & Fig.2 Logic symbol. 7 2 5 handbook, halfpage B Y & 3 A 6 MNA099 MNA713 Fig.3 IEC logic symbol. 2004 Jan 21 Fig.4 Logic diagram. 4 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 RECOMMENDED OPERATING CONDITIONS 74AHC2G00 SYMBOL PARAMETER 74AHCT2G00 CONDITIONS UNIT MIN. TYP. MAX. MIN. VCC supply voltage 2.0 5.0 5.5 4.5 VI input voltage 0 − 5.5 VO output voltage 0 − VCC Tamb operating ambient temperature see DC and AC −40 characteristics per device +25 tr, tf input rise and fall times VCC = 3.3 ± 0.3 V − VCC = 5 ± 0.5 V − TYP. MAX. 5.0 5.5 V 0 − 5.5 V 0 − VCC V +125 −40 +25 +125 °C − 100 − − − ns/V − 20 − − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input diode current − −20 mA VI < −0.5 V IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC, IGND VCC or GND current − ±75 mA Tstg storage temperature −65 +150 °C PD power dissipation − 250 mW Tamb = −40 to +125 °C Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2004 Jan 21 5 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 DC CHARACTERISTICS Type 74AHC2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = 25 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 2.0 − V IO = −50 µA 3.0 2.9 3.0 − V IO = −50 µA 4.5 4.4 4.5 − V IO = −4.0 mA 3.0 2.58 − − V IO = −8.0 mA 4.5 3.94 − − V IO = 50 µA 2.0 − 0 0.1 V IO = 50 µA 3.0 − 0 0.1 V IO = 50 µA 4.5 − 0 0.1 V IO = 4.0 mA 3.0 − − 0.36 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 8.0 mA 4.5 − − 0.36 V ILI input leakage current VI = VCC or GND 5.5 − − 0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA CI input capacitance − − 1.5 10 pF 2004 Jan 21 6 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 − − V IO = −50 µA 3.0 2.9 − − V IO = −50 µA 4.5 4.4 − − V IO = −4.0 mA 3.0 2.48 − − V IO = −8.0 mA 4.5 3.8 − − V IO = 50 µA 2.0 − − 0.1 V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.44 V IO = 8.0 mA 4.5 − − 0.44 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA CI input capacitance − − − 10 pF 2004 Jan 21 7 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 − − V IO = −50 µA 3.0 2.9 − − V IO = −50 µA 4.5 4.4 − − V IO = −4.0 mA 3.0 2.40 − − V IO = −8.0 mA 4.5 3.70 − − V IO = 50 µA 2.0 − − 0.1 V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.55 V IO = 8.0 mA 4.5 − − 0.55 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − 2.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA CI input capacitance − − − 10 pF 2004 Jan 21 8 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 Type 74AHCT2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = 25 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VOL LOW-level output voltage VI = VIH or VIL IO = −50 µA 4.5 4.4 4.5 − V IO = −8.0 mA 4.5 3.94 − − V IO = 50 µA 4.5 − 0 0.1 V IO = 8.0 mA 4.5 − − 0.36 V 5.5 − − 0.1 µA VI = VIH or VIL ILI input leakage current VI = VIH or VIL ICC quiescent supply current VI = VCC or GND; IO = 0 ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 CI input capacitance 5.5 − − 1.0 µA 5.5 − − 1.35 mA − 1.5 10 pF Tamb = −40 to +85 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VOL LOW-level output voltage VI = VIH or VIL IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.8 − − V VI = VIH or VIL IO = 50 µA 4.5 − − 0.1 V IO = 8.0 mA 4.5 − − 0.44 V 5.5 − − 1.0 µA ILI input leakage current VI = VIH or VIL ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2004 Jan 21 9 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.70 − − V IO = 50 µA 4.5 − − 0.1 V IO = 8.0 mA 4.5 − − 0.55 V VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VIH or VIL 5.5 − − 2.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2004 Jan 21 10 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 AC CHARACTERISTICS Type 74AHC2G00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS CL (pF) MIN. TYP. MAX. UNIT 3.0 to 3.6 − 4.5(1) 7.9 ns 4.5 to 5.5 − 3.5(2) 5.5 ns 3.0 to 3.6 − 6.5(1) 11.4 ns 4.5 to 5.5 − 4.9(2) 7.5 ns VCC (V) Tamb = 25 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 Tamb = −40 to +85 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 3.0 to 3.6 1.0 − 9.5 ns 4.5 to 5.5 1.0 − 6.5 ns 3.0 to 3.6 1.0 − 13.0 ns 4.5 to 5.5 1.0 − 8.5 ns 3.0 to 3.6 1.0 − 10.5 ns 4.5 to 5.5 1.0 − 7.0 ns 3.0 to 3.6 1.0 − 14.5 ns 4.5 to 5.5 1.0 − 9.5 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 50 Notes 1. Typical values are measured at VCC = 3.3 V. 2. Typical values are measured at VCC = 5.0 V. 2004 Jan 21 11 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 Type 74AHCT2G00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS CL (pF) MIN. TYP. MAX. UNIT 1.0 3.6(1) 6.2 ns 7.9 ns VCC (V) Tamb = 25 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 15 4.5 to 5.5 50 4.5 to 5.5 1.0 5.0(1) 15 4.5 to 5.5 1.0 − 7.1 ns 50 4.5 to 5.5 1.0 − 9.0 ns 15 4.5 to 5.5 1.0 − 8.0 ns 50 4.5 to 5.5 1.0 − 10.0 ns Tamb = −40 to +85 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 Tamb = −40 to +125 °C tPHL/tPLH propagation delay input nA and nB to output nY see Figs 5 and 6 Note 1. Typical values are measured at VCC = 5.0 V. 2004 Jan 21 12 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 AC WAVEFORMS handbook, halfpage nA, nB input VM tPHL tPLH VM nY output MNA213 FAMILY VM INPUT VM OUTPUT AHC2G00 50% VCC 50% VCC AHCT2G00 1.5 V 50% VCC Fig.5 The inputs (nA and nB) to output (nY) propagation delays. VCC handbook, halfpage PULSE GENERATOR VI VO D.U.T. RT CL MNA101 FAMILY VI INPUT REQUIREMENTS AHC2G00 GND to VCC AHCT2G00 GND to 3.0 V Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (See “AC characteristics” for the value). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. Fig.6 Load circuitry for switching times. 2004 Jan 21 13 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 PACKAGE OUTLINES TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 2004 Jan 21 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- 14 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 2004 Jan 21 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 15 Philips Semiconductors Product specification 2-input NAND gate 74AHC2G00; 74AHCT2G00 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Jan 21 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R44/01/pp17 Date of release: 2004 Jan 21 Document order number: 9397 750 12474