5 A Evaluation Board for Step-Down DC-to-DC Controller EVAL-ADP1828LC EVALUATION BOARD DESCRIPTION This data sheet describes the design, operation, and test results of the ADP1828 5 A evaluation board. The input range for this evaluation board is 5.5 V to 13.2 V, and the output voltage is 1.8 V with a maximum load current of 5 A. For this design, a switching frequency (fSW) of 600 kHz is chosen to achieve a good balance between efficiency and the sizes of the power components. ADP1828 DEVICE DESCRIPTION The ADP1828 is a synchronous PWM voltage mode buck controller. It drives an all N-channel power stage to regulate an output voltage as low as 0.6 V to 85% of the input voltage and is sized to handle large MOSFETs for point-of-load regulators. The ADP1828 is ideal for a wide range of high power applications, such as DSP and processor core I/O power, as well as generalpurpose power in telecommunications, medical imaging, PC, gaming, and industrial applications. It operates from an input voltage of 3 V to 18 V with an internal LDO that generates a 5 V output for a VIN of 5.5 V to 18 V. The ADP1828 operates at a pin-selectable, fixed switching frequency of either 300 kHz or 600 kHz, or at any frequency between 300 kHz and 600 kHz if a resistor is used. The frequency can also be synchronized to an external clock up to 2× the switching frequency. The clock output can be used for synchronizing the ADP1828 or another part, such as the ADP1829, thus eliminating the need for an external clock source. The ADP1828 includes soft start protection (to limit inrush current from the input supply during startup), reverse current protection during soft start for a precharged output, voltage tracking, power good, as well as an adjustable lossless current-limit scheme utilizing external MOSFET sensing. The ADP1828 is offered in a 20-lead QSOP package. DIGITAL PICTURE OF THE BOARD DISK DRIVE POWER CONNECTOR VIN TERMINAL GND TERMINAL ACTIVE AREA GND TERMINAL DUAL FET Si7958DP ADP1828 06906-001 VOUT TERMIINAL Figure 1. ADP1828 5 A Evaluation Board Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. EVAL-ADP1828LC TABLE OF CONTENTS Evaluation Board Description......................................................... 1 Switching Noise and Overshoot Reduction...............................4 ADP1828 Device Description......................................................... 1 Compensation Design ..................................................................4 Digital Picture of the Board ............................................................ 1 Test Results .........................................................................................5 Revision History ............................................................................... 2 Evaluation Board OperatinG InstructionS ................................7 Component Design .......................................................................... 3 Evaluation Board Schematic ............................................................9 Input Capacitor............................................................................. 3 Evaluation Board Layout ............................................................... 10 Inductor Selection ........................................................................ 3 Ordering Information.................................................................... 11 Output Capacitor Selection......................................................... 3 Bill of Materials........................................................................... 11 MOSFET Selection....................................................................... 3 Ordering Guide .......................................................................... 12 Soft Start ........................................................................................ 3 ESD Caution................................................................................ 12 Current Limit ................................................................................ 3 REVISION HISTORY 8/07—Revision 0: Initial Version Rev. 0 | Page 2 of 12 EVAL-ADP1828LC COMPONENT DESIGN For information about selecting power components and calculating component values, see the ADP1828 data sheet. the effective capacitance of the ceramic capacitor decreases as the bias voltage increases. INPUT CAPACITOR MOSFET SELECTION Ceramic capacitors have very low ESR (in the order of 1 mΩ or 2 mΩ) and have large ripple current rating. For a 5 A output with a VIN of 6 V to13.2 V and a VOUT of 1.8 V, three 22 μF ceramic capacitors (22 μF/16 V/X5R/1210) are adequate. In general, select the high-side MOSFET with fast rise and fall times and low input capacitance. Fast rise and fall times and low input capacitance are especially important for circuits with low duty cycles because switching loss is high. Select the low-side MOSFET with low RDSON. Switching speed is not critical because there is no switching loss in the low-side MOSFET. A small amount of power is lost in the body diode of the low-side MOSFET during the dead time. INDUCTOR SELECTION For this design, a 1.8 μH inductor (FDV0630-1R8M from Toko Inc.) is selected. This is a compact, low-cost inductor with an iron powder core, which generally has more core power loss but at a lower cost than the ones with ferrite cores. OUTPUT CAPACITOR SELECTION The output voltage ripple can be approximated as follows: 2 ⎞ ⎛ 1 ⎟ + (4 f SW ESL)2 ΔVOUT = ΔI L ESR2 + ⎜⎜ ⎟ 8 f C ⎝ SW OUT ⎠ (1) where: ΔVOUT is the output ripple voltage. ΔIL is the inductor ripple current. ESR is the equivalent series resistance of the output capacitor. ESL is the equivalent series inductance of the output capacitor. A minimum capacitance at the output is needed to achieve a fast load-step response and a reasonable overshoot voltage. The minimum capacitance can be calculated as C OUT,min1 = ΔI LOAD L 2VO UT ΔVup (2) C OUT,min2 = ΔI LOAD 2 L 2(V IN − VO UT ) ΔVdown (3) 2 where: ΔILOAD is the step load. ΔVup is the output voltage overshoot when the load is stepped down. ΔVdown is the output voltage overshoot when the load is stepped up. VIN is the input voltage. COUT,min1 is the minimum capacitance according to the overshoot voltage ΔVup. COUT,min2 is the minimum capacitance according to the overshoot voltage ΔVdown. Select an output capacitance that is greater than both COUT, min1 and COUT, min2. In this design, multilayer ceramic capacitors (MLCCs) are used. Because MLCCs have very low ESR and ESL, the output ripple is dominated by the bulk capacitance. Two output ceramic capacitors (100 μF/6.3 V/X5R/1210 and 47 μF/6.3 V/X5R/1206) have been selected to satisfy a 5 A step load. Keep in mind that For this evaluation board, a dual FET in a PowerPAK® SO-8 (Si7958DP from Vishay) has been selected. The PowerPAK SO-8 has a low thermal resistance, θJA, and is adequate for handling a 5 A output. An alternative is to use two single MOSFETs in standard SO-8 packages. Furthermore, for an output current less than 3 A, a dual FET in a standard SO-8 package is usually adequate. SOFT START The soft start period is given by the following equation: C SS = 8.015 × t SS (4) where: CSS is the soft start capacitance in microfarads. tSS is the soft start period in seconds. A CSS of 150 nF, which yields a 19 ms soft start period, is chosen for this design. CURRENT LIMIT The external current-limit resistor can be calculated by the following equation: RCL ΔI L ⎞ ⎛I ⎜ LIMIT + ⎟RDSON − 38 mV 2 ⎠ ⎝ = 42 μA (5) where: ILIMIT is the output limit current. ΔIL is the ripple current in the inductor. RDSON is the on resistance of the low-side MOSFET. −38 mV is the CSL threshold voltage. ΔIL can be approximated by ΔI L = VOUT (1 − D) f SW × L (6) where: D is the duty cycle. L is the inductance of the inductor. In this design, RDSON of the MOSFET Si7958DP is 20 mΩ with a VGS of 4.5 V. Because L is chosen to be 1.8 μH, ΔIL is calculated to be 1.4 A. If ILIMIT is set to 6.5 A, RCL is calculated to be 2.88 kΩ. A standard value of 2.87 kΩ is chosen. Keep in mind that RDSON Rev. 0 | Page 3 of 12 EVAL-ADP1828LC CHF RFF VOUT CFF RZ CI RTOP RBOT FB EA SWITCHING NOISE AND OVERSHOOT REDUCTION An RC snubber can be added between SW and PGND to reduce noise and ringing at the SW node and at the drains of the external MOSFETs. In this design, an RC snubber is added with an RSNUB of 3.01 Ω and a CSNUB of 1.2 nF. Gate resistors can be added to reduce overshoot voltage at the drains of the MOSFETs. For more information, see the ADP1828 data sheet. COMPENSATION DESIGN Type III compensation is used in this design because all output capacitors all ceramic with very low ESR. For information on calculating the compensation component values, refer to the ADP1828 data sheet. INTERNAL VREF COMP 06906-002 of the MOSFET can vary by more than 25% from part to part, and by more than 50% over the temperature range; therefore, the actual current limit can vary by more than 50% from part to part over the temperature range. For more information on this topic, see the ADP1828 data sheet. Figure 2. Type III Compensation The compensation values for this evaluation board have been optimized as follows: RFF = 422 Ω CFF = 1 nF RZ = 7.5 kΩ CI = 3.9 nF CHF = 33 pF RTOP = 20 kΩ RBOT = 10 kΩ Rev. 0 | Page 4 of 12 EVAL-ADP1828LC TEST RESULTS T T SW VOUT (AC-COUPLED) 1 1 2 INPUT RIPPLES 1A TO 5A STEP LOAD OUTPUT RIPPLES 3 CH2 50.0mV BW M 1.00µs A CH1 3.60V BW CH1 100mV M 200µs BW A CH4 3.60A CH4 2.00A Ω 06906-006 CH1 10.0V CH3 10.0mV 06906-003 4 Figure 6. Load Transient, VIN = 12 V, Load = 1 A to 5 A Figure 3. Output Ripple, VIN = 12 V, Load = 5 A 95 T VIN = 4V 90 VIN (5V TO 9V) VIN = 5.5V 85 EFFICIENCY (%) 80 75 VIN = 12V 70 65 VOUT (AC-COUPLED) 60 1 VOUT = 1.8V TA = 25°C 0 1 2 3 4 5 LOAD (A) 06906-004 45 3 fSW = 600 kHz 50 CH1 2.00V CH3 50.0mV M 4.00ms BW BW A CH1 6.08V 06906-007 55 Figure 7. Line Transient, VIN = 5 V to 9 V, No Load Figure 4. Efficiency vs. Load Current T T DH EN 1 1 VOUT 2 DL 2 SS 3 4 CH2 1.00V M 4.00ms A CH1 3.000V CH1 10.0V CH2 5.00V CH4 1.00A Ω M 1.00µs A CH1 4.60V Figure 8. Inductor Current Waveform, VIN = 12 V, No Load Figure 5. Soft Start, VIN = 12 V Rev. 0 | Page 5 of 12 06906-008 CH1 5.00V CH3 1.00V 06906-005 INDUCTOR CURRENT EVAL-ADP1828LC 1.806 1.797 1.804 1.796 1.794 VOUT (V) 1.798 1.796 1.794 1.793 1.792 1.791 1.790 1.792 5A LOAD 1.789 1.790 0 1 2 3 4 LOAD (A) 5 6 Figure 9. Load Regulation, VIN = 12 V 1.787 5 7 9 VIN (V) Figure 10. Line Regulation Rev. 0 | Page 6 of 12 11 13 06906-010 1.788 06906-009 VOUT (V) 1.800 1.788 2A LOAD 1.795 1.802 EVAL-ADP1828LC EVALUATION BOARD OPERATING INSTRUCTIONS 1. 2. 3. 4. 5. 6. 7. Connect Jumper JP3 to the on position to enable the ADP1828. Do not connect Jumper J7 (VIN to VREG). Connect Jumper JP2 (FREQ) to the 600 kHz position. Connect Jumper J8 (SYNC) to GND (that is, if SYNC is not used). If SYNC is used, connect SYNC to an external clock or CLKOUT from another ADP1828. Connect Jumper JP1 (CLKSET) to high, which sets CLKOUT to 2× the internal oscillator frequency and in phase with the oscillator, or to low, which sets CLKOUT to 1× the oscillator frequency and 180o out of phase. Connect the positive terminal of the input power supply to the input terminal, J3. Connect the load to the VOUT terminal, J1. Table 1. Jumper Descriptions Jumper JP1 Description CLKSET. Clock set input. Function CLKSET = high sets CLKOUT to 2 × fOSC CLKSET = low sets CLKOUT to 1 × fOSC VREG: fSW = 600 kHz GND: fSW = 300 kHz EN = on enables ADP1828 EN = off disables ADP1828 Short VREG to VIN when VIN is less than 5.5 V JP2 Frequency selection. Connect to VREG for fSW = 600 kHz. JP3 EN. Connect to the on position to enable the ADP1828. J7 VREG to VIN. Do not connect this jumper when VIN is greater than 5.5 V. J8 SYNC. Connect SYNC to GND if the SYNC function is not used. If SYNC is used, connect SYNC to an external clock or to the CLKOUT of another ADP1828. Synchronization J9 12 V supply from the disk drive connector. Short this jumper if the 12 V input supply comes from the disk drive connector. Do not short J9 and J10 at the same time. 12 V supply from disk drive J10 5 V supply from the disk drive connector. Short this jumper if the 5 V input supply comes from the disk drive connector. Do not short J9 and J10 at the same time. 5 V supply from disk drive Table 2. Evaluation Board Operating Conditions Parameter VIN VOUT fSW Maximum Step Load Condition Input range 5.5 V to 13.2 V. VOUT = 1.8 V at 5 A maximum output current. Switching frequency is set to 600 kHz. This design can handle a 0 A to 5 A step load at the output. The output capacitance can be reduced if a 5 A step load is not required. Table 3. Temperature of the Power Components 1, 2 ADP1828 50oC 1 2 Inductor (Toko FDV0630-1R8M) 60oC MOSFETs (Vishay Si7958DP) 60oC After the evaluation board ran for 30 minutes at a 5 A load, the surface temperatures of the power components were measured with an infrared thermometer. VIN = 12 V, TA = 25oC. Rev. 0 | Page 7 of 12 EVAL-ADP1828LC Table 4. Miscellaneous Information Parameter Switching Frequency, fSW Dual Power MOSFETs: Q1A and Q1B Inductor VREG and VIN Snubber Circuit Gate Resistors Capacitor C17 Voltage Divider Comment The switching frequency, fSW, is set to 600 kHz (Jumper JP2) on the evaluation board. If a different fSW is needed, the compensation and the power components need to be recalculated. If a fSW other than 300 kHz or 600 kHz is desired, a resistor, R13, can be soldered onto the PCB to select any frequency between 300 kHz and 600 kHz. The footprint for the dual power MOSFETs is laid out to fit both the PowerPAK SO-8 and the standard SO-8 package so that the user can easily replace the on-board PowerPAK with a standard SO-8 package. The footprint for the inductor is laid out to fit inductors that are smaller or larger than the on-board inductor, Toko FDV0630. For input voltages less than 5.5 V, the user can connect Jumper J7 by shorting VREG to VIN. A snubber RC circuit, RSNUB and CSNUB, is laid out on the evaluation board to help reduce switching noise and ringing at the SW node. The user can remove this RC snubber or try different RC values for a particular application. Keep in mind that the RC snubber dissipates power and slightly reduces the overall efficiency, generally in the range of 0.1% to 0.5%. The dummy 0 Ω gate resistors, R2 and R3, at DH and DL, respectively, are provided on the evaluation board for reducing overshoot voltage at the drains of the external MOSFETs. The user can change these 0 Ω resistors to different values (generally in the range of 1 Ω to 5 Ω) to achieve the desired reduction in overshoot voltage. Keep in mind that the gate resistor dissipates power and slightly reduces the overall efficiency. A ceramic capacitor, C17, is placed very close to the drain of the high-side MOSFET. This capacitor, typically 0.1 μF to 1 μF, helps to reduce input impedance during high frequency transients. C17 is not assembled on the evaluation board. The user can add this capacitor if needed for a particular application. If a different output voltage other than 1.8 V is desired, the user needs to change the voltage feedback divider, R7 and R8, and rework the compensation component values and the input and output capacitances. Rev. 0 | Page 8 of 12 Rev. 0 | Page 9 of 12 100K R9 TP4 FB Figure 11. ADP1828 5 A Evaluation Board Schematic SGND R7 10K 20K R8 422 ohm R11 7.5k R10 1 nF C8 3.9nF C6 33pF C7 TRK TP1 SGND C9 1.0uF SGND TP10 VREG 100K R4 C15 0.1uF SGND VREG SGND 100K R6 C2 150nF SS JP3 OPEN FREQ SYNC EN IN VREG GND COMP FB TRK SS U1 TP9 1 2 3 4 5 6 7 8 9 10 ON EN OFF JP2 CL KOUT CL KSET BST DH SW CSL PGND DL PV PGOOD ADP1828 600khz FREQ 300khz R13 SGND TP5 BST C16 1.0uF SOD-323 D1 PGND TP3 PGOOD 20 19 18 17 16 15 14 13 12 11 JP1 HI CL KSET LOW SGND 0.22uF C1 TP2 CL KOUT 0 R2 Q1A TP8 SW PGND C10 1.8uH PGND L1 C3 PGND Rsnb 3.01 ohm C17 open PGND Csnb 1.2nF Q1B FET- N_DUAL _POWERP AK 2.87k PGND 0 R3 R1 TP7 DL TP6 DH FET- N_DUAL _POWERP AK Si7958DP 7 J8 22uF /16V/X5R/1210 not fitted GND C4 C11 22uF/1 6V/X5R/1210 100uF /6.3V/X5R/1210 VI N C5 C12 22uF /16V/X5R/1210 47uf /6.3V/X5R/1206 SYNC J7 C14 C13 J9 J10 GND TP 2 5V GND GND 12V P1 Red yellow 1 1 1 1 GND J2 1.8V J1 GND J4 Vin= 5.5-13.2V J3 MOL EX-15244441 4 VOUT TP 1 PGND 3 2 1 06906-011 TP11 SYNC EVAL-ADP1828LC EVALUATION BOARD SCHEMATIC EVAL-ADP1828LC 06906-012 06906-015 EVALUATION BOARD LAYOUT 06906-013 06906-016 Figure 15. Third Layer (GND Layer) Figure 12. Silkscreen Layer Figure 13. Top Layer 06906-014 Figure 16. Bottom Layer Figure 14. Second Layer Rev. 0 | Page 10 of 12 EVAL-ADP1828LC ORDERING INFORMATION BILL OF MATERIALS Table 5. Component Listing Item 1 Qty 3 Designator C10, C11, C12 Description Capacitor, ceramic, 22 μF, 16 V, X5R, 1210 Manufacturer Murata Part No. GRM32ER61C226KE20 2 1 C4 Capacitor, ceramic, 100 μF, 6.3 V, X5R, 1210 Murata GRM32ER60J107ME20 3 1 C5 Capacitor, ceramic, 47 μF, 6.3 V, X5R, 1206 Murata GRM31CR60J476ME20 4 1 C2 Capacitor, ceramic, 150 nF, 16 V, X7R, 0603 Vishay VJ0603Y154KXJA 5 1 C15 Capacitor, ceramic, 0.1 μF, 6.3 V, X5R, 0603 Vishay VJ0603Y104MXQ 6 1 C1 Capacitor, ceramic, 0.22 μF, 10 V, X5R, 0603 7 4 R2, R3, R5, R12 Resistor (dummy), 0 Ω, 1/10 W, 1%, 0603 Taiyo Yuden Murata Vishay TMK107BJ224MA-T GRM188R61A224KA61 CRCW06030R00F 8 1 R8 Resistor, 20 kΩ, 1/10 W, 1%, 0603 Vishay CRCW06032002F 9 1 R7 Resistor, 10 kΩ, 1/10 W, 1%, 0603 Vishay CRCW06031002F 10 1 R11 Resistor, 422 Ω, 1/10 W, 1%, 0603/0402 Vishay CRCW06034220F 11 1 R10 Resistor, 7.5 kΩ, 1/10 W, 1%, 0603 Vishay CRCW06037501F 12 3 R4, R6, R9 Resistor, 100 kΩ, 1/10 W, 1%, 0603 Vishay CRCW06031003F 13 1 R1 Resistor, 2.87 kΩ, 1/10 W, 1%, 0603 (current-limit resistor) Vishay CRCW06032801F 14 1 Rsnb Resistor, 3.01 Ω, 0805 Vishay CRCW08053R01F 15 1 Csnb Capacitor, ceramic, 1.2 nF, 0805 Vishay VJ0603Y122KXXA 16 1 C8 Capacitor, ceramic, 1 nF, 0603 Vishay VJ0603Y102KXXA 17 18 19 1 1 2 C7 C6 C9, C16 Capacitor, ceramic, 33 pF, 0603 Capacitor, ceramic, 3.9 nF, 0603 Capacitor, ceramic, 1.0 μF, 10 V, X5R, 0603 20 1 L1 Inductor, 1.8 μH, 18 mΩ, 6.6 A, iron powder core (Alternative: 2.0 μH, 16 mΩ, 6.5 A, flat wire) VJ0603A330KXXA VJ0603Y392KXXA LMK107BJ105MK-T GRM185R61A105KE36 FDV0630-1R8M (744310200) 21 22 23 1 1 1 D1 Q1A, Q1B P1 Schottky diode, 30 V, VF = 0.5 V @ 30 mA, SOD-323 Transistor, N-MOSFET, 40 V, PowerPAK SO-8, 20 mΩ @ 4.5 V Disk drive power connector Vishay Vishay Taiyo Yuden Murata Toko (Würth Elektronik) Vishay Vishay Molex Inc. 24 3 JP1, JP2, JP3 3-terminal jumpers, 0.1" spacing Any 25 1 J8 2-terminal jumper, 0.1" spacing Any 26 13 Test points for VREG, SW, DH, DL, TRK, SS, PGOOD, BST, FB, SYNC, CLKOUT, GND, VOUT Any 40 mil (1 mm) through hole 27 1 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, VOUT TP 1, GND TP 2 U1 DUT, 10-lead QSOP Analog Devices ADP1828 Rev. 0 | Page 11 of 12 BAT54WS Si7958DP 15244441 EVAL-ADP1828LC ESD CAUTION ORDERING GUIDE Model ADP1828LC-EVALZ1 1 Description Evaluation Board Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06906-0-8/07(0) Rev. 0 | Page 12 of 12