Evaluation Board for Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking EVAL-ADP1829 INTRODUCTION This data sheet describes the design, operation, and test results obtained with the ADP1829 evaluation board. The input range for this evaluation board is 5.5 V to 18 V. The output voltages are configured for VOUT1 = 1.8 V (with a maximum current limit of 15 A) and for VOUT2 = 1.2 V (with a maximum current limit of 15 A). All of the results tested on the evaluation board ran at a switching frequency (fSW) of 300 kHz with VIN = 12 V, VOUT1 = 1.2 V at up to 15 A, and VOUT2 = 1.8 V at up to 15 A. GENERAL DESCRIPTION The ADP1829 operates at a pin selectable fixed switching frequency of either 300 kHz or 600 kHz. For some noise sensitive applications, it can also be synchronized to an external clock to achieve switching frequency between 300 kHz and 1 MHz. The ADP1829 includes an adjustable soft start to limit input inrush current, voltage tracking for sequencing or DDR termination, independent power good output, and a power enable pin. It also provides current-limit and short-circuit protection by sensing the voltage on the synchronous MOSFET. The ADP1829 evaluation board schematic is shown in Figure 16. The switching frequency chosen is 300 kHz to provide good efficiency over a wide range of input and output conditions. Table 2 is the bill of materials (BOM) for the evaluation board. 06808-020 ADP1829 is a versatile, dual output, interleaved, synchronous PWM buck controller that generates two independent outputs from an input voltage of 2.9 V to 18 V. It is ideal for a wide range of high power applications, such as DSP and processor core, general-purpose power in telecommunications, medical imaging, PC gaming, and industrial applications. Each channel can be configured to provide output voltage from 0.6 V to 85% of the input voltage. The two channels operate 180° out of phase, which reduces the current stress on the input capacitor and allows the use of a smaller and lower cost input capacitor. Figure 1. Digital Picture of the ADP1829 Evaluation Board Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. EVAL-ADP1829 TABLE OF CONTENTS Introduction ...................................................................................... 1 Voltage Tracking............................................................................5 General Description ......................................................................... 1 Compensation Design ..................................................................5 Revision History ............................................................................... 2 Test Results .........................................................................................7 Component Design .......................................................................... 3 PCB Layout Guidelines.....................................................................9 Input Capacitor............................................................................. 3 Evaluation Board Schematic and Layout .................................... 11 Inductor Selection ........................................................................ 3 Ordering Information.................................................................... 13 Output Capacitor Selection......................................................... 3 Bill of Materials........................................................................... 13 MOSFET Selection....................................................................... 4 Ordering Guide .......................................................................... 14 Soft Start ........................................................................................ 4 ESD Caution................................................................................ 14 Current Limit ................................................................................ 4 REVISION HISTORY 7/07—Revision 0: Initial Version Rev. 0 | Page 2 of 16 EVAL-ADP1829 COMPONENT DESIGN INPUT CAPACITOR OUTPUT CAPACITOR SELECTION The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. Select the input bulk capacitor based on its ripple current rating. The two channels in the ADP1829 operate 180° out of phase, thus reducing the current rating on the input capacitor. Choose the output capacitor to set the desired output voltage ripple. The output voltage ripple is a function of the inductor ripple current and the capacitor impedance at the switching frequency. The output voltage ripple can be approximated as If the maximum output load currents are about the same, the input ripple current for both Channel 1 and Channel 2 is less than half of the higher of the output load currents. The input capacitor current is approximated as IinRipple ≈ IL (1) 2 where IL is the current though the inductor. If the load currents of the two channels are significantly different (the smaller is less than 50% of the larger), in this case, if the duty cycle D is between 20% and 80%, the input capacitor ripple current is approximately IL√D(1 − D). If duty cycle D is less than 20% or greater than 80%, the ripple current is approximately 0.4IL. INDUCTOR SELECTION The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output voltage ripple and conduction losses in the MOSFETs, but allows using smaller inductors and less output capacitance for a specified peak-to-peak voltage overshoot at load transient. Generally, choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output current. Use the following equation to calculate the inductor value: L= VOUT (1 − D) (2) ΔI L f SW where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. D is the duty cycle. ΔIL is the inductor ripple current, typically 1/3 of the dc load. ⎛ 1 ΔVOUT = ΔI L ⎜ ESR + ⎜ 8 f SW C OUT ⎝ ⎞ ⎟ ⎟ ⎠ (3) For high ESR capacitors, the ripple is dominated by the ESR, while for low ESR capacitors, the output ripple is dominated by the capacitor. ESL of the capacitor also affects the output ripple, especially the though-hole electrolytic capacitors. In practical designs, multiple types of capacitors are used. For instance, a MLCC (multilayer ceramic capacitor) can be paralleled with an electrolytic capacitor to reduce the ESL and ESR. Another factor that should be considered is the load-step transient response on the output, where the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. A minimum capacitance at the output is needed in order to have a fast load-step response and reasonable overshoot voltage. The minimum capacitance can be calculated as COUT, min1 = ΔI OUT 2 L 2VOUT ΔVup (4) COUT,min2 = ΔIOUT 2 L 2(VIN − VO UT) ΔVdown (5) where: ΔIO is the step load. ΔVup is the output voltage overshoot when the load is stepped down. ΔVdown is the output voltage overshoot when the load is stepped up. VIN is the input voltage. COUT,min1 is the minimum capacitance according to the overshoot voltage ΔVup. COUT,min2 is the minimum capacitance according to the overshoot voltage ΔVdown. Select an output capacitance that is greater than both COUT, min1 and COUT, min2. Make sure that the ripple current rating of the output capacitors is greater than the following current: I COUT = Rev. 0 | Page 3 of 16 ΔI L 2 12 (6) EVAL-ADP1829 MOSFET SELECTION The high-side MOSFET conduction loss can be calculated as The choice of MOSFET directly affects the dc-to-dc converter performance. The MOSFET must have low on resistance (RDSON) to reduce the conduction loss, and low gate charge to reduce switching loss. For the low-side (synchronous) MOSFET, the dominant loss is the conduction loss. It can be calculated as ΔI 2 ⎞ ⎛ PC .low = (1 − D) ⎜ IOUT 2 + L ⎟ RDSON 12 ⎠ ⎝ (7) The gate charge loss is dissipated by the ADP1829 regulator and gate drivers. The gate charge loss is approximated by the following equation: PG = VG QG f SW (8) where: VG is the driver voltage. QG is the MOSFET total gate charge. The high-side (main) MOSFET has to be able to handle two main power dissipations: conduction loss and switching loss. The switching loss is related to rise and fall times of the MOFSET, the switching frequency, the inductor current, and the input voltage. The high-side MOSFET switching loss is approximated by the equation PT = V IN I L (t R + t F ) f SW 2 SOFT START The ADP1829 uses an adjustable soft start to limit the output voltage ramp-up period, thus limiting the input inrush current. The soft start is set by selecting the capacitor, CSS, from SS1 and SS2 to GND. The ADP1829 charges CSS to 0.8 V through an internal 90 kΩ resistor. The voltage on the soft-start capacitor while it is charging is t ⎛ − SS ⎞ RC SS ⎟ ⎜ = 0.8 1 − e ⎜ ⎟ ⎝ ⎠ C SS = (9) t SS 0.6 ⎞ ⎛ −R ln ⎜1 − ⎟ 0.8 ⎠ ⎝ where R = 90 kΩ and tss is the soft-start time. Therefore, Q GS + Q GD 2 tR = VG − VSP RG C SS = 8.015 t SS × 10 −6 F (11) CURRENT LIMIT The ADP1829 employs a unique, programmable cycle-by-cycle lossless current-limit circuit. In every switching cycle, the voltage drop across the synchronous MOSFET RDSON is measured to determine if the current is too high. and Q GS + Q GD 2 tF = VSP RG where: QGS and QGD are the parameters of MOSFET, provided from the MOSFET data sheet. RG is the resistor on the driver. VSP is approximated using where gm is the MOSFET transconductance. Make sure that the selection MOSFET can meet the total power dissipation when combining the switching and conduction loss (generally about 1.5 W for a single D-Pak, 0.8 W for an SO-8, and 1.2 W for a PowerPak-SO8). The soft start period ends when the voltage on the soft-start pin reaches 0.6 V. They can be calculated by IO U T gm (10) It is important to choose a high-side MOSFET that balances the conduction loss and the switching loss. VCSS where tR and tF are the rise and fall times of the MOSFET. VSP ≈ VTH + ΔI 2 ⎞ ⎛ PC ,high = D ⎜ IOUT 2 + L ⎟RDSON 12 ⎠ ⎝ This measurement is done by an internal comparator and an external resistor. The CSL1 and CSL2 pins are the inverting inputs of the current-limit comparators and the noninverting inputs are referenced to PGND1 and PGND2, respectively. A resistor is tied between the CSL pin and the switch node, which is the drain of the synchronous MOSFET. A 50 μA current is forced though the resistor to set an offset voltage drop across it. When the synchronous MOSFET is on and the voltage drop on it exceeds the offset voltage on the external resistor, an overcurrent fault is flagged. When the ADP1829 senses an overcurrent condition, the next switching cycle is suppressed, and the soft-start capacitor is discharged. The ADP1829 remains in this mode as long as the overcurrent condition persists. When the overcurrent condition is removed, operation resumes in soft-start mode. Rev. 0 | Page 4 of 16 EVAL-ADP1829 L The external current-limit resistor can be calculated by the following equation: R ESR (12) Z1 PWM COMPARATOR VOLTAGE TRACKING Note that the soft-start time of the master voltage should be set to be longer than the soft start of the slave voltage. That forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start of the slave voltage is longer, the slave comes up more slowly and the tracking relationship is not seen at the output. The slave channel should still have a soft-start capacitor to give a small but reasonable soft-start time to protect in case of restart after a current-limit event. For more information about the voltage tracking, see the ADP1829 data sheet. Figure 2. Voltage Mode Buck Converter VO C1 R3 R2 R4 C2 C3 COMP R1 REFERENCE Figure 3. Type III Compensation Circuit The buck converter control to output transfer function can be described by the following equation: s 1+ 2 π fZ VIN vo (s ) Gvd (s) = = × s s2 d (s ) 1 + 1 1+ + R Q2π fO (2π fO)2 where: fZ = 1 2πRC C R COMPENSATION DESIGN Figure 2 shows the voltage mode control loop for a synchronous buck converter. Usually, design the compensator to get adequate phase margin and high cross frequency for stable operation and good transient response. There are two types of compensation circuits for the ADP1829, Type II and Type III. For more details, see the ADP1829data sheet. REFERENCE COMPARATOR The ADP1829 features tracking inputs, TRK1 and TRK2, which make the output voltage track another voltage. This is especially useful in core and I/O voltage sequencing applications. The ADP1829 tracking input is an additional positive input to the error amplifier. The feedback voltage is regulated to the lower of the 0.6 V reference or the voltage at TRK, so a lower voltage on TRK limits the output voltage. This feature allows implementation of two different types of tracking: coincident tracking, where the output voltage is the same as the master voltage until the master voltage reaches regulation, or ratiometric tracking, where the output voltage is limited to a fraction of the master voltage. In all tracking configurations, the master voltage should be higher than the slave voltage. ERROR AMP Z2 06808-002 where Ilimit is the limit current. 06808-003 RCLS ΔI L ⎞ ⎛I ⎜ limit + ⎟RDSON 2 ⎠ ⎝ = 50 μA C VIN fO = Q= R + RC 2π LC 1+ R 1 × L + R RCC 2 π fO RC is the ESR of the output capacitor. Rev. 0 | Page 5 of 16 (13) EVAL-ADP1829 The compensation network consists of the error amplifier and the impedance networks Z1 and Z2. Figure 3 shows a Type III compensation circuit. It provides two poles and two zeros. The transfer function of this compensator is − AEA s GEA (s) = ⎛ s ⎞ ⎛ 2 ⎞ ⎟ ⎜1 + ⎟ ⎜ ⎜ 2π f ⎟ × ⎜ 1 + 2π f ⎟ Z1 ⎠ ⎝ Z2 ⎠ ⎝ × ⎛ s ⎞ ⎛ s ⎞ ⎜1 + ⎟ ⎜ ⎟ ⎜ 2π f ⎟ × ⎜1 + 2π f ⎟ P1⎠ ⎝ P2 ⎠ ⎝ The loop gain can be written as T (s) = f Z1 = f Z2 = f P1 = f P2 = 1 (C1 + C2 ) × R2 (14) Use the following guidelines to select the compensation components: 1. Set the loop gain cross frequency fC. A good choice is to place the cross frequency fC at fs/10 for fast response. 2. Cancel ESR zero fZ by compensator pole fP1. 3. Place the high frequency pole fP2 to achieve maximum attenuation of switching ripple and high frequency noise. A good choice is fP2 = (5 ~ 10) fC. 4. Place two compensator zeros near the power stage resonant frequency fO. In general, place fZ1 below fO and place fZ2 between fO and fC. 5. Check the phase margin to obtain good regulation performance. 1 2π R 4 C 2 1 2π (R2 + R3 ) × C3 1 2π R3 C 3 1 2π R4 × (15) where VRamp is the PWM ramp peak voltage; in the ADP1829, VRamp = 1.3 V. where: AEA = Gvd (s) × GEA (s) VRamp C1C2 C1 + C2 Rev. 0 | Page 6 of 16 EVAL-ADP1829 TEST RESULTS T 1 2 2 B W CH2 5.00V CH1 20.0mV M2.00µs T 53.60% A CH2 5.90V 06808-004 1 95 90 90 85 85 M2.00µs T 67.40% A CH2 5.90V 80 EFFICIENCY (%) 80 75 70 65 75 70 65 60 60 55 55 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO (A) 50 06808-006 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO (A) Figure 5. Efficiency vs. Load Current, VOUT = 1.8 V, fSW = 300 kHz Figure 8. Efficiency vs. Load Current, VOUT = 1.2 V, fSW = 300 kHz T T 1 1 2 2 3 3 4 A CH2 2.70V CH1 10.0V CH3 1.00V CH2 5.00V CH4 1.00V M10.0ms T 34.40% A CH2 2.70V 06808-009 M10.0ms T 32.80% 06808-008 4 CH1 10.0V BW CH2 5.00V CH3 1.00V BW CH4 1.00V Figure 9. Soft Start of Channel 2, Channel 1: EN2, Channel 2: PG2, Channel 3: SS2, Channel 4: VOUT2 Figure 6. Soft Start of Channel 1, Channel 1: EN1, Channel 2: PG1, Channel 3: SS1, Channel 4: VOUT1 Rev. 0 | Page 7 of 16 06808-007 EFFICIENCY (%) CH2 5.00V Figure 7. Output Ripple of Channel 2, VOUT = 1.2 V, fSW = 300 kHz, Channel 1: VOUT2, Channel 2: SW2 Figure 4. Output Ripple of Channel 1, VOUT = 1.8 V, fSW = 300 kHz, Channel 1: VOUT1, Channel 2: SW1 50 B W CH1 20.0mV 06808-005 T EVAL-ADP1829 T T 1 1 2 2 3 3 4 M4.00ms T 52.20% A CH2 2.70V CH1 10.0V CH2 5.00V CH3 1.00V BW CH4 1.00V Figure 10. Disable Channel 1, Channel 1: EN1, Channel 2: PG1, Channel 3: SS1, Channel 4: VOUT1 M10.0ms T 56.80% A CH2 2.70V 06808-011 CH2 5.00V B CH4 1.00V W 06808-010 4 CH1 10.0V CH3 1.00V Figure 13. Disable Channel 2, Channel 1: EN2, Channel 2: PG2, Channel 3: SS2, Channel 4: VOUT2 T T 1 1 M400µs T 76.80% A CH3 9.60A 06808-012 CH1 50.0mV CH3 5.00A Ω BW Figure 11. Load Transient Response of Channel 1, 5 A to 15 A , VIN = 12 V, VOUT = 1.8 V A CH3 9.60A Figure 14. Load Transient Response of Channel 2, 5 A to 15 A, VIN = 12 V, VOUT = 1.2 V T T 1 2 2 3 3 4 4 M4.00ms T 32.80% A CH4 2.80V 06808-014 1 CH1 10.0V BW CH2 5.00V CH3 1.00V BW CH4 1.00V M400µs T 76.80% CH1 10.0V BW CH2 5.00V CH3 1.00V BW CH4 5.00V Figure 12. Start into Precharged Channel 1, Channel 1: VIN, Channel 2: Low-Side Gate, Channel 3: VOUT, Channel 4: POK M4.00ms T 25.80% A CH4 2.80V 06808-015 CH1 50.0mV CH3 5.00A Ω BW 06808-013 3 3 Figure 15. Start into Precharged Channel 2 Channel 1: VIN, Channel 2: Low-Side Gate, Channel 3: VOUT, Channel 4: POK Rev. 0 | Page 8 of 16 EVAL-ADP1829 PCB LAYOUT GUIDELINES In any switching converter, some circuit paths carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. Still others carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and copper area accordingly. The following is a list of recommended layout practices for ADP1829, arranged in approximately decreasing order of importance: 1. Keep the high current loops small. While the inductor is considered to have continuous high current, this current is switched alternately through the top and bottom FETs. The current waveform in each FET is a pulse with very high dI/dt, so the path to, through, and from each individual FET should be as short as possible. In designs that use a pair of D-Pak or SO-8 FETs on one side of the PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high-side drain can be bypassed to the low-side source with a suitable ceramic bypass capacitor, placed as close as possible to the FETs. This minimizes inductance around this loop through the FETs and capacitor. In designs that place the two FETs on opposite sides of the board, it may work well to place one FET directly opposite to (above and below) the other to form a minimal current loop area. Again, make sure that the high-side drain is bypassed to the low-side source with a suitable ceramic bypass capacitor, connected as closely as possible to the FETs to minimize the loop area. may include SYNC, FREQ, or LDOSD. This ground area should be connected through one wide trace to the negative terminal of the output filter capacitors. Because the ADP1829 is a dual output controller, it is desirable to place the output filters of the two output voltages adjacent to each other. This provides the best accuracy for the two outputs. 3. PGND pins handle high dI/dt gate drive current returning from the source of the low-side MOSFET. The voltage at this pin also establishes the 0 V reference for the OCP function and the CSL pins. A small PGND plane should connect the PGND pins and the PV bypass capacitors through a wide and direct path to the source of the appropriate low-side MOSFET. 4. Gate drive traces (DH and DL) handle high dI/dt so they tend to produce noise and ringing. They should be as short and direct as possible. If the overall PCB layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. For this reason, it is occasionally helpful to place small value resistors (such as 10 Ω) in series with the gate traces. These can be populated with 0 Ω if resistance is not needed. 5. The switch node is the interconnection of the source of the high-side FET with the drain of the low-side FET and the inductor. This is the noisiest place in the switcher circuit with large ac and dc voltage and current. This node should be wide to keep resistive voltage drop down. However, to minimize the generation of capacitively coupled noise, the total area should be small. The best layout generally places the FETs and inductor all close together on a small copper plane to minimize series resistance and keep the copper area small. Recommended ceramic capacitor values range from 4.7 μF to 22 μF depending upon the output current. This bypass capacitor is usually connected to a larger value bulk filter capacitor. 2. GND, IN bypass, VREG bypass, soft-start capacitors, and the bottom ends of the output feedback divider resistors should be tied to an (almost isolated) small ground plane under the IC. No high current or high dI/dt signals should be connected to this ground plane. One via should connect GND to the die paddle heat sink area. The AGND and PGND planes should be separated before joining them together. Other low current signal grounds can also be connected here if a ground connection is needed; these Rev. 0 | Page 9 of 16 Connect a direct and moderately sized trace from the switch node back to the SW pin and the CSL resistor. This trace handles the high dI/dt gate current for the high-side FET. The voltage on this trace is also sensed through the CSL resistors and pins to sense an overcurrent condition. The high dI/dt and sensing overcurrent do not occur at the same time. Keep the compensation and feedback components away from the switch nodes and their associated components. EVAL-ADP1829 6. 7. The negative terminal of the output filter capacitors should be tied closely to the source of the low-side FET. Doing this helps to minimize voltage differences between GND and PGND at the ADP1829. The current in these capacitors is not very high in a buck converter, but the output trace handles the full output current of the converter. High dc current flows through this trace to the input filter capacitors, so it is generally helpful to place a bulk input filter capacitor close to the output filter capacitors on this output ground plane. The GND connection of the ADP1829 should be connected to this output ground at the output filter capacitors. concerns such as stray inductance or dc voltage drop. Any dc voltage differential in connections between ADP1829 GND and the converter power output ground can cause a significant output voltage error, as it affects converter output voltage according to the ratio with the 600 mV feedback reference. For example, a 6 mV offset between ground on the ADP1829 and the converter power output causes a 1% error in the converter output voltage. 8. Generally, be sure that all traces are sized according to the current to be handled as well as their sensitivity in the circuit. Standard PCB layout guidelines mainly address heating effects of current in a copper conductor. While these are completely valid, they do not fully cover other Rev. 0 | Page 10 of 16 The CSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. Adding thermal vias to the PCB provides a thermal path to the inner or bottom layers. Because the thermal pad is attached to the die substrate, the planes that the thermal pad is connected to must be electrically isolated or connected to GND. Rev. 0 | Page 11 of 16 R25 100K Figure 16. ADP1829 Evaluation Board Schematic, fSW = 300 kHz C27 NOT FITTED C28 NOT FITTED GND R10 0ohm R21 50 R22 OPEN R20 OPEN R14 392 C22 1uF C14 5600pF R12 2k L2 2.2uH C2 180uF 20V R8 100K 300kHz 600kHz R18 2K SS2 C16 820pF R16 10K 8 7 6 5 4 3 2 1 TRK2 COMP2 FB2 UV2 GND FREQ SYNC FB1 32 C17 6800pF C15 1500pF R15 4.7K Q8 IRFR3709Z C18 4700pF Q2 IRLR7807Z R11 1K R9 2K C13 10nF 9 31 30 SS1 11 R6 0ohm R4 1.5k R2 0ohm C10 0.47uF C12 100nF 10 29 100nF C11 ADP1829 U1 28 12 SW2 13 27 J2 14 26 ON OFF J3 15 25 OFF 16 PV DL1 PGND1 CSL1 SW1 DH1 BST1 POK1 OFF ON ON J4 D2 17 18 19 20 21 22 23 24 DL1 R23 100K R5 0ohm R3 1.5K R1 0ohm C9 0.47uF BST1 POK1 DH1 D1 R7 100K C1 180uF 20V R19 100K R17 100K L1 2.2uH C21 1uF SW1 SPECIFICATIONS: VIN = 5.5V TO 18V VOUT1 = 1.8V @ 15A VOUT2 = 1.2V @ 15A FSW = 300kHz. J1 DEFAULT. J1 TO SELECT BETWEEN 300kHz AND 600kHz VOUT1 = 1.8V TRK2 C30 NOT FITTED VOUT2 = 1.2V POK2 FB2 SYNC TRK1 J1 TRK1 POK2 R24 100K C19 1uF SS1 BST2 R13 200 VREG DH2 C20 100nF LDOSD CSL2 VREG IN SW2 COMP1 SS2 EN2 PGND2 EN1 DL2 FB1 Q1 IRLR7807Z R26 100K Q7 IRFR3709Z GND GND C32 NOT FITTED 06808-001 VIN 5.5V TO 18V EVAL-ADP1829 EVALUATION BOARD SCHEMATIC AND LAYOUT C31 NOT FITTED C29 NOT FITTED C7 10uF 6.3V C24 1200uF 6.3V C5 1200uF 6.3V C3 1200uF 6.3V Q6 IRFR3709Z C4 820uF 2.5V C6 820uF 2.5V C23 NOT FITTED C8 10uF 6.3V C25 NOT FITTED C26 NOT FITTED Q5 IRFR3709Z 06808-016 06808-018 EVAL-ADP1829 Figure 19. Top and Bottom Layers 06808-017 06808-019 Figure 17. Silk Screen Layer Figure 18. Inner Layer 1 Figure 20. Inner Layer 2 Table 1. Jumper Description Jumper J1 Description Frequency Selection J2 LDO Shunt Down or Enable J3 Channel 1 Enable or Disable J4 Channel 2 Enable or Disable Function VREG: fSW = 600 kHz GND: fSW = 300 kHz VREG: LDO shunt down GND: LDO enable VIN: Channel 1 enable GND: Channel 1 disable VIN: Channel 2 enable GND: Channel 2 disable Rev. 0 | Page 12 of 16 EVAL-ADP1829 ORDERING INFORMATION BILL OF MATERIALS Table 2. Item 1 2 Description Capacitor, OS-CON, 180 μF, 20 V Capacitor, Polymer Aluminum, 820 μF, 2.5 V Manufacturer Sanyo United Chemi-con 3 4 5 Capacitor, Aluminum Electrolytic, 1200 μF, 6.3 V Capacitor, Ceramic, 10 μF, 6.3 V, X5R, 0805 Capacitor, Ceramic, 0.47 μF, 10 V, X5R, 0603 6 7 8 9 10 11 12 13 Capacitor, Ceramic, 0.1 μF, 10 V, X7R, 0603 Capacitor, Ceramic, 10 nF, 50 V, NPO, 0603 Capacitor, Ceramic, 5600 pF, 50 V, NPO, 0603 Capacitor, Ceramic, 1500 pF, 50 V, NPO, 0603 Capacitor, Ceramic, 820 pF, 50 V, NPO, 0603 Capacitor, Ceramic, 6800 pF, 10 V, NPO, 0603 Capacitor, Ceramic, 4700 pF, 10 V, NPO, 0603 Capacitor, Ceramic, 1.0 μF, 10 V, X5R, 0603 14 15 Capacitor, Ceramic, 0.1 μF, 50 V, Y5V, 0603 Capacitor, Ceramic, 1.0 μF, 25 V, X5R, 0805 Rubycon Murata Taiyo Yuden Murata Vishay Vishay Vishay Vishay Vishay Vishay Vishay Taiyo Yuden Murata Taiyo Yuden Taiyo Yuden Murata 16 Capacitor, Ceramic 17 18 19 Resistor, 0 Ω, 1/10 W, 1%, 0603 Resistor, 1.5 kΩ, 1/10 W, 1%, 0603 Resistor, 100 kΩ, 1/10 W, 1%, 0603 Vishay Vishay Vishay CRCW06030R00F CRCW06031501F CRCW06031003F 20 21 22 23 24 25 26 27 28 29 30 31 32 Vishay Vishay CRCW06032001F CRCW06031001F Not used CRCW06034751F CRCW06031002F CRCW06032000F CRCW06032920F CRCW120649R9F FDA1254-2R2M=P3 CMPD4448 IRLR7807Z IRFR3709Z ADP1829 33 34 Resistor, 2.0 kΩ, 1/10 W, 1%, 0603 Resistor, 1.0 kΩ, 1/10 W, 1%, 0603 Resistor, 100 kΩ, 1/10 W, 1%, 0603 Resistor, 4.75 kΩ, 1/10 W, 1%, 0603 Resistor, 10 kΩ, 1/10 W, 1%, 0603 Resistor, 200 Ω, 1/10 W, 1%, 0603 Resistor, 392 Ω, 1/10 W, 1%, 0603 Resistor, 49.9 Ω, 1/4 W, 1%, 1206 Inductor, 2.2 μH, 15 A, 4.5 mΩ DCR Diode, Switching, 250 mA, 75 V, SOT-23 Transistor, N MOSFET, 30 A, D-Pak, 18 mΩ Transistor, N MOSFET, 60 A, D-Pak, 8 mΩ IC, Dual Interleaved Step-Down Controller with Tracking Jumper, 0.1” Spacing Test Points 35 Terminal 36 BNC Vishay Vishay Vishay Vishay Vishay Toko Central Semi IR IR Analog Devices Any Any Part No. 20SP180M APSA2R5ELL821MHB5S Mouser: 661-PSA2.5VB820M 6.3 ZLG1200M 10×16 GRM21BR60J106K LMK107BJ474MA-T GRM188R61A474KA61 VJ0603Y104MXQ VJ0603Y123KXXA VJ0603Y562 KXXA VJ0603Y152 KXXA VJ0603Y821 KXXA VJ0603Y822 KXXA VJ0603Y472 KXXA LMK107BJ105MK-T GRM185R61A105KE36 UMK107F104ZA-T TMK212BJ105KG-T GRM21BR61E105KA99 Not used Designator C1, C2 C4, C6 Qty. 2 2 C3, C5, C24 C7, C8 C9, C10 3 2 2 C11, C12 C13 C14 C15 C16 C17 C18 C19 2 1 1 1 1 1 1 1 C20 C21, C22 1 2 C 23, C25, C26, C27, C28, C29, C30, C31, C32 R1, R2, R5, R6, R10 R3, R4 R7, R8, R17, R19, R23, R24, R25, R26 R9, R12, R18 R11 R20, R22 R15 R16 R13 R14 R21 L1, L2 D1, D2 Q1, Q2 Q5, Q6, Q7, Q8 U1 9 J1, J2, J3, J4 VREG, TRK1, TRK2, POK1, POK2, FB1, FB2, SS1, SS2, BST1, SW1, SW2, DH1, DL1 VIN, GND, VOUT1, GND, VOUT2, GND SYNC Rev. 0 | Page 13 of 16 5 2 8 3 1 2 1 1 1 1 1 2 2 2 4 1 4 14 6 1 EVAL-ADP1829 ORDERING GUIDE Model ADP1829-EVALZ1 1 ESD CAUTION Package Description Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 EVAL-ADP1829 NOTES Rev. 0 | Page 15 of 16 EVAL-ADP1829 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06808-0-7/07(0) Rev. 0 | Page 16 of 16