Evaluation Board for 20 A Step-Down DC-to-DC Controller EVAL-ADP1821 clock at any frequency between 300 kHz and 1.2 MHz. The internal gate drivers control an all N-channel power stage to regulate a converter output voltage as low as 0.6 V with up to 20 A load current. EVALUATION BOARD DESCRIPTION This data sheet describes the design, operation, and test of the ADP1821 standard evaluation board. In all tests, the board is operated from an input voltage range of 9 V to 15 V, and generates up to 10 A at VOUT = 1.8 V. The switching frequency is fixed at 600 kHz. The ADP1821 includes an adjustable soft start to limit input inrush current and facilitate sequencing. It provides currentlimit and short-circuit protection, and a power-good logic output. ADP1821 DEVICE DESCRIPTION The ADP1821 is well suited for a wide range of power applications, such as DSP and processor core power in telecom, medical imaging, high performance servers, and industrial applications. The ADP1821 is a versatile and inexpensive synchronous buck pulse-width modulation (PWM) controller. The converter power input voltage range is 1 V to 24 V and the ADP1821 controller is specified from 3.0 V to 5.5 V. The ADP1821 freerunning frequency is logic-selectable at either 300 kHz or 600 kHz. Alternatively, it can be synchronized to an external EVALUATION BOARD INPUT CAPACITOR INPUT TERMINAL HIGH-SIDE MOSFET OUTPUT INDUCTOR LOW-SIDE MOSFET OUTPUT CAPACITOR OUTPUT CAPACITOR (MLCC) OUTPUT TERMINAL 06360-017 ADP1821 Figure 1. Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards as supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. EVAL-ADP1821 TABLE OF CONTENTS Evaluation Board Description......................................................... 1 PCB Layout Guidelines.....................................................................7 ADP1821 Device Description......................................................... 1 Evaluation Board Schematic and Artwork.....................................8 Evaluation Board .............................................................................. 1 PCB Layout ....................................................................................9 Revision History ............................................................................... 2 Ordering Information.................................................................... 11 Evaluation Board Hardware ............................................................ 3 Bill of Materials........................................................................... 11 Component Selection................................................................... 3 Ordering Guide .......................................................................... 11 Design and Control Loop Equations ......................................... 4 ESD Caution................................................................................ 11 Test Results and Waveforms............................................................ 6 REVISION HISTORY 11/06—Revision 0: Initial Version Rev. 0 | Page 2 of 12 EVAL-ADP1821 EVALUATION BOARD HARDWARE COMPONENT SELECTION Current Limit Set Resistor Output Inductor The voltage on the CSL pin can be calculated with the following formula: The output inductor can be chosen according to the following equation: L= VOUT I O × K CR × f SW × (1 − D ) ΔI ⎞ ⎛ VCSL = I CSL × (R CSL + R RDSON _ LOW ) − ⎜ I L + L ⎟ × R RDSON _ LOW 2 ⎠ ⎝ where: VCSL is the voltage on the CSL pin. ICSL is the source current out of the CSL pin, 42 μA. RCSL is the current limited resistor. RDSON_LOW is the conduction resistor of the low-side MOSFET. IL is the output current. ΔIL is the output current ripple. where: VOUT is the output voltage, 1.8 V. Io is the rated output current, 10 A. KCR is the ratio of current ripple, KCR = ΔI/IO. fSW is the switching frequency. V D is the duty cycle, D = OUT = 0.15 VIN In normal operation, the direction of current flow through the low-side MOSFET causes a negative voltage to appear on its drain, Generally, KCR can be set at 20% to 40%. Thus, the inductance of L can be set at 0.63 μH to 1.2 μH. where I is the instantaneous MOSFET current and R is RDSON. Choosing the Output Capacitor The capacitance and ESR of the output capacitor have a major impact on the performance of the converter, including output ripple and transient response. Voltage ripple caused by the capacitance can be calculated by the following formula: t ΔVCAP = ∫0 V=I×R 1 ΔI COUT ( τ )dτ C Voltage ripple caused by the ESR can be calculated by the following formula: ΔVESR _ MAX = ΔI L × RESR _ C Generally, the voltage ripple caused by the capacitance or ESR depends on the capacitor chosen. A 42 μA current source at the ADP1821 CSL pin causes a fixed voltage drop in the current sense resistor that is connected from the CSL pin to the drain of the low-side MOSFET. This current through the current limit set resistor produces a voltage in the opposite direction, thus raising in the positive direction the potential at the CSL pin. The resulting net voltage on the CSL pin is compared with ground. During normal operation, the CSL pin stays above ground potential. The overcurrent protection circuitry is triggered when an increased MOSFET current produces increased negative voltage on the low-side MOSFET drain, thus causing the voltage on the CSL pin to go negative with respect to ground. The resistor RCSL can be calculated from the following equation: In the evaluation board, the parameters of the output filter OSCON capacitors are as follows: C = 2720 μF, RESR_C = 1.75 mΩ at 600 kHz RCSL where ILIMIT is the desired load current limit. Setting the Output Voltage Setting the Soft Start The regulation threshold at the FB pin is 0.6 V, and the maximum input bias current is 100 nA. This bias current can introduce significant errors if the divider impedance is too high. In order to get the best accuracy, the bottom resistor R2 should be no higher than 50 kΩ. However, very low values of R2 will dissipate excess power. It is recommend that R2 be a 1% resistor with a value between 1 kΩ and 10 kΩ. The soft start characteristic is set by the capacitor connected from SS to GND. The ADP1821 charges CSS to 0.8 V through an internal resistor. The soft start period tSS is achieved with V (CSS) = 0.6 V. C SS = The upper divider is then set with the following formula: R1 = R2 × VOUT − 0.6 0.6 ΔI L ⎞ ⎛ ⎜ I LIMIT + ⎟ × R DSON _ LOW 2 ⎠ ⎝ = I CSL t SS 0.6 ⎞ ⎛ − ln⎜1 − ⎟ × 100 kΩ ⎝ 0.8 ⎠ where 100 kΩ is the internal resistor. Rev. 0 | Page 3 of 12 EVAL-ADP1821 DESIGN AND CONTROL LOOP EQUATIONS 30 0 20 –20 10 –40 GAIN 0 L1 GAIN (dB) VOUT RL1 RC LOW-SIDE DRIVER C1 R9 VRAMP C21 COMP R11 C22 06360-002 R10 VREF PHASE –100 –40 –120 –50 –140 –60 VFB OUT –80 –20 –30 R8 C20 OUT –60 –10 Figure 2. Control Loop 10 100 Figure 3. Power Stage Gain and Phase Margin Control Circuit and Transfer Function The power stage transfer function of ADP1821 is given by the following equations. Figure 3 shows the Bode plots of the phase and gain margin. VOUT C19 R4 VOUT (s) ⎞ ⎛⎜ ⎟ ⎜ 1 + (R × C × s ) C ⎟×⎜ 2 ⎟⎟ ⎜ 1 + s + s ⎠ ⎜⎝ Q × ω0 ω02 ⎞ ⎟ ⎟ ⎟ ⎟⎟ ⎠ Q= RC is the ESR of output capacitor. RL is the series resistor of output inductor. ω0 is the resonant frequency. VCOMP VREF VCOMP (s) VOUT (s) ⎛ s ⎞⎛ s ⎞ ⎜1 + ⎟⎜ ⎟ ⎜ 2πf ⎟⎜1 + 2πf ⎟ Z 1 ⎠⎝ Z2 ⎠ ⎝ GEA (s) = k × ⎛ x ⎞⎛ x ⎞ ⎜1 + ⎟⎜ ⎟ ⎜ 2πf ⎟⎜1 + 2πf ⎟ P 1 ⎠⎝ P2 ⎠ ⎝ L ×C × OUT The equation for the compensation transfer function is: RL + R RC + R R × RL × C L + (RL + RC ) × C + C R R C17 Figure 4. Compensation Circuit G EA (s) = RL +1 R R3 VFB R2 where: ω0 = R1 C18 D( s ) ⎛ ⎜ V GVD (s) = ⎜ IN ⎜⎜ 1 + RL R ⎝ –160 1M 100k The compensation circuit is used for the control circuit and transfer function as shown in Figure 4. Power Stage Transfer Function GVD (s) = 1k 10k FREQUENCY 06360-004 HIGH-SIDE DRIVER PHASE (Degrees) VIN 06360-003 See Figure 2 for a simplified schematic diagram of the overall control loop. 1 ω0 where: VCOMP is the voltage at the COMP pin. fZ1 is the first compensator zero frequency produced by R3 and C17. fZ2 is the second compensator zero frequency produced by R1, R2, and C18. fP1 is the first compensator pole frequency produced by C17 and C19. fP2 is the second compensator pole frequency produced by C18. k=− 1 2 × π × R3 × C17 1 = 2 × π × (R1 + R2) × C18 f Z1 = fZ2 Rev. 0 | Page 4 of 12 R3 R1 EVAL-ADP1821 Overall Loop Results 1 C17 × C19 ⎞ 2 × π × R3⎛⎜ ⎟ ⎝ C17 + C19 ⎠ 1 = 2 × π × R 4 × C18 f P1 = fP2 The overall control loop gain can be shown as: T (s ) = The switching frequency is 600 kHz. For best performance, setting the crossover frequencies to ~1/10 of switching frequency, fSW, or ~60 kHz is recommend. Lower crossover frequencies cause poor dynamic response, and higher crossover frequencies can cause instability. The best performance usually results from the highest possible crossover frequency that allows adequate gain and phase margins. A phase margin in the range of 40 to 60 degrees is recommended (see Figure 5). 50 GVD (s) × G EA (s) VRAMP where: GVD is the power stage transfer function. GEA is the compensation transfer function. VRAMP is the peak ramp voltage (typically 1.25 V) of the ADP1821 PWM controller. The overall control loop Bode plot is shown in Figure 6. 180 80 250 160 60 140 45 120 200 GAIN GAIN (dB) PHASE 25 100 20 PHASE (Degrees) 150 30 80 0 60 40 –40 fp2:320kHz 10 0 10 100 PHASE 15 5 GAIN 20 –20 fp1:32kHz fz1:1.46kHz –60 fz2:3.9kHz 0 100 1k 10k FREQUENCY 100k 20 50 1M 06360-005 GAIN (dB) 35 Figure 5. Compensation Gain and Phase Rev. 0 | Page 5 of 12 10 100 1k 10k FREQUENCY (Hz) 100k 0 1M Figure 6. Overall Control Loop Gain Cross Frequency: 63 kHz, Phase Margin: 55 Degrees 06360-006 40 PHASE (Degrees) 40 EVAL-ADP1821 TEST RESULTS AND WAVEFORMS T T Δ: 35.6mV @: 22.0mV 1 1 M1.00µs T 49.60% A CH1 5.60mV CH1 20.0mV CH4 5.00AΩ Figure 7. Output Voltage Ripple of Channel 1 VIN = 12 V, VOUT = 1.8 V, Load = 10 A M200µs T 20.20% A CH4 6.50A 06360-014 CH1 20.0mV 06360-011 4 Figure 10. Transient Response, Channel 1: VOUT, Channel 4: IOUT VIN = 12 V, VOUT = 1.8 V, Load = 2 A to 10 A T T 2 1 2 3 M1.00ms T 19.60% A CH2 2.20V CH2 1.00V CH4 10.0AΩ Figure 8. Enable On, Channel 1: VOUT, Channel 2: EN, Channel 3: PWGD VIN = 12 V, VOUT = 1.8 V, Load = 10 A M1.00ms T 20.20% A CH4 15.2A 06360-015 CH1 500mV CH2 2.00V CH3 2.00V 06360-012 4 Figure 11. Load Short, Channel 2: VOUT, Channel 4: IOUT VIN = 12 V, VOUT = 1.8 V T VIN = 9V EFFICIENCY (%) 90 1 2 VIN = 12V 80 VIN = 15V 70 60 M1.00ms T 39.60% A CH2 1.52V 50 06360-013 CH1 500mV CH2 2.00V CH3 2.00V Figure 9. Enable Off, Channel 1: VOUT, Channel 2: EN, Channel 3: PWGD VIN = 12 V, VOUT = 1.8 V, Load = 10 A Rev. 0 | Page 6 of 12 0 2 4 6 IO (A) 8 Figure 12. Efficiency vs. Load Current 10 12 06360-016 3 EVAL-ADP1821 PCB LAYOUT GUIDELINES PLACE THE CERAMIC CAPACITOR NEAR THE TOP MOSFET. DH 1 VIN 2 C3 180µF 20V C4 180µF 20V C1 1µF 25V C2 1µF 25V INPUT VOUT L1 1µH, 2.1mΩ SW J2 1 Q2 IRFR37 11Z DL KEEP THE POWER STAGE LOOP AS SHORT AS POSSIBLE. LARGE COPPER AREA NEEDED AT THE MOSFET DRAIN FOR THERMAL CONSIDERATION. 2 OUTPUT Q3 MMBT2222 R5 1.2kΩ D1 BZX84C5V6 C9 C10 680µF, 4V, 7mΩ C11 C5 1µF 10V R6 10Ω C13 1µF SYNC 1 FREQ 1 JP1 SHORT PIN C8 PLACE THE BOOTSTRAP CAPACITOR NEAR THE IC. R10 10kΩ R9 10kΩ D2 BAT54 R8 10kΩ C15 0.1µF DH SW ON/OFF 1 PWGD 1 SW2 SW1 R11 10kΩ C14 1µF U1 1 2 3 4 5 6 7 8 BST DH SW SYNC FREQ SHDN PWGD GND PVCC DL PGND CSL VCC COMP FB SS ADP1821 16 15 14 13 12 11 10 9 C7 10µF 10V C6 1µF 10V A CERAMIC CAPACITOR WAS ADDED TO FILTER THE NOISE ABOVE SWITCHING FREQUENCY. C12 22nF R3 82kΩ KEEP THE COMPENSATION COMPONENT NEAR THE IC. SW VOUT C16 2.2pF C19 18pF CONTROL GROUND AND POWER STAGE GROUND SHOULD BE SEPARATED. GROUND PLANE IS OFTEN USED. CONNECT THE FEEDBACK POINT FROM THE CERAMIC CAPACITOR AND KEEP THE TRACE AS SHORT AS POSSIBLE. DL R7 3kΩ 1% C17 1nF R1 20kΩ 1% R4 2.7kΩ C18 1.8nF R2 10kΩ 1% 06360-007 J1 Q1 IRFR37 11Z CERAMIC CAPACITOR WAS USED TO FILTER THE HIGH SWITCHING NOISE AND IT WAS PLACED NEAR THE LOAD. Figure 13. PCB Layout Guide To keep the inductance down, the traces running from the high-side MOSFET and the low-side MOSFET to the DH and DL pins of the ADP1821, respectively, need to be relatively short and wide. The source of Q1 and drain of Q2 should be placed as close as possible to minimize the inductance in this portion of the circuit. Keep this connection short and wide. However, too much copper area on this switch node increases capacitively coupled common-mode noise. The analog GND of the ADP1821 and the ground of the signal components should be connected to the AGND plane. The PGND of the ADP1821 and the ground of all the power components, such as the low-side MOSFET, and input and output bulk capacitors, should be connected to the PGND plane. The connection between the ground of the power components and the PGND plane needs to be kept as short as possible. This minimizes noise, electromagnetic interference (EMI), and ground bouncing. Note the following: • • • Ceramic input decoupling capacitors C1 and C2 should be located as close as possible to the drain of Q1 and source of Q2. C13 and C14 should be close to the VIN pin of IC. The compensation components should also be placed closed to the IC. Rev. 0 | Page 7 of 12 EVAL-ADP1821 EVALUATION BOARD SCHEMATIC AND ARTWORK Q1 IRFR3711Z DH J1 1 VIN 2 C3 180µF 20V C4 180µF 20V C1 1µF 25V C2 1µF 25V INPUT SW J2 DL Q2 IRFR3711Z C8 680µF 4V 7mΩ C9 680µF 4V 7mΩ C10 680µF 4V 7mΩ C11 680µF 4V 7mΩ C5 1µF 10V C6 1µF 10V 1 2 C7 10µF 10V OUTPUT Q3 MMBT2222 R5 1.2kΩ D1 BZX84C5V6 R6 10Ω C13 1µF R10 10kΩ R9 10kΩ C15 0.1µF R8 10kΩ D2 BAT54 C14 1µF U1 SYNC 1 FREQ 1 JP1 SHORT PIN 1 2 1 2 3 4 5 6 7 8 DH SW ON/OFF 1 PWGD 1 SW2 SW1 R11 10kΩ BST DH SW SYNC FREQ SHDN PWGD GND PVCC DL PGND CSL VCC COMP FB SS ADP1821 16 15 14 13 12 11 10 9 DL R7 3kΩ 1% C12 22nF R3 82kΩ C19 18pF SWITCH 1: OPEN = 600kHz SHORT = 300kHz SWITCH 2: OPEN = ENABLE SHORT = DISABLE SW VOUT C16 2.2pF C17 1nF R1 20kΩ 1% R2 10kΩ 1% Figure 14. ADP1821 Typical Application Schematic Diagram Rev. 0 | Page 8 of 12 R4 2.7kΩ C18 1.8nF 06360-001 VIN VOUT L1 1µH, 2.1mΩ EVAL-ADP1821 06360-008 PCB LAYOUT 06360-009 Figure 15. Silkscreen Top Figure 16. Top Layer Rev. 0 | Page 9 of 12 06360-010 EVAL-ADP1821 Figure 17. Bottom layer Rev. 0 | Page 10 of 12 EVAL-ADP1821 ORDERING INFORMATION BILL OF MATERIALS Typical application circuit (12 V to 1.8 V@ 10 A, fSW = 600 kHz) Table 1. Qty 2 2 Reference Designator C1,C2 C3, C4 4 1 4 C5, C6, C13, C14 C7 C8, C9, C10, C11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 4 C12 C15 C16 C17 C18 C19 D1 D2 L1 Q1 Q2 Q3 R1 R2 R3 R4 R5 R6 R7 R8, R9, R10, R11 U1 VOUT, GND Description Capacitor, ceramic, 1 μF, 25 V, X5R, 0603 Capacitor, OS-CON, 180 μF, 20 V, 20 mΩ, 11 mm x 10 mm x 5 mm Capacitor, ceramic, 1 μF, 10 V, X5R, 0603 Capacitor, ceramic, 10 μF, 10 V, X5R, 1206 Capacitor, OS-CON, 680 μF, 4 V, 7 mΩ, 13 mm x 8 mm x 3.5 mm Capacitor, ceramic, 22 nF, 16 V, X7R, 0603 Capacitor, ceramic, 0.1 μF, 16 V, X7R, 0603 Capacitor, ceramic, 2.2 pF, 16 V, NPO, 0603 Capacitor, ceramic, 1 nF, 16 V, X7R, 0603 Capacitor, ceramic, 1.8 nF, 16 V, X7R, 0603 Capacitor, ceramic, 18 pF, 50 V, NPO, 0603 Diode_Zener, 5.6 V, SOT-23 Diode, 30 V, 200 mA, 4 ns, SOT-23 Inductor, 1 μH, 2.1 mΩ, 20.3 A N-MOSFET, 20 V, D-PAK, 5.7 mΩ, 18 nC N-MOSFET, 20 V, D-PAK, 5.7 mΩ, 18 nC BJT- NPN, 40 V, 600 mA, SOT-23 Resistor, 20 kΩ, 1/10 W, 1%, 0603 Resistor, 10 kΩ, 1/10 W, 1%, 0603 Resistor, 82 kΩ, 1/10 W, 1%, 0603 Resistor, 2.7 kΩ, 1/10 W, 1%, 0603 Resistor, 1.2 kΩ, 1/10 W, 1%, 0603 Resistor, 10 Ω, 1/10 W, 1%, 0603 Resistor, 3 kΩ, 1/10 W, 1%, 0603 Resistor, 10 kΩ, 1/10 W, 1%, 0603 Step-down dc-to-dc controller Terminals ORDERING GUIDE Model ADP1821-EVAL Description Evaluation Board ESD CAUTION Rev. 0 | Page 11 of 12 Supplier Murata Sanyo Supplier Number GRM188RC1E105KA 20SP180M Murata Murata Sanyo GRM188R61A105KA GRM319R61A106KE19 4SEPC680M Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent ON Semiconductor® Fairchild Coiltronics IR IR ON Semiconductor® Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Vishay or equivalent Analog Devices, Inc. VJ0603Y223KXXA VJ0603Y104MXQ VJ0603Y2R2KXXA VJ0603Y102KXXA VJ0603Y182KXXA VJ0603Y180KXXA BZX84C5V6 BAT54 HC7-1R0 IRFR3711Z IRFR3711Z MMBT2222 CRCW06032002F CRCW06031002F CRCW06038202F CRCW06032701F CRCW06031201F CRCW060310R0F CRCW06033001F CRCW06031002F ADP1821 EVAL-ADP1821 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06360-0-11/06(0) Rev. 0 | Page 12 of 12