Evaluation Board User Guide UG-205 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluation Board for the ADP1850DP Step-Down DC-to-DC Controller power MOSFETs. The two PWM outputs are phase shifted 180°, which reduces the input RMS ripple current, thus minimizing required input capacitance. The two outputs can be combined for dual-phase PWM operation that can deliver more than 50 A output current. The internal parameters of the two channels are optimized for current sharing. FEATURES Input range: 10 V to 15 V Output voltage: 1.09 V Output current: 50 A Switching frequency: 300 kHz Operates in PWM Compact, low cost, and efficient design In addition, boost diodes are integrated into the ADP1850, thus lowering the overall system cost and component count. The ADP1850 can be set to operate in pulse skip, high efficiency mode under light load or in PWM continuous conduction mode. EVALUATION BOARD DESCRIPTION This document describes the design, operation, and test results of the ADP1850DP-EVALZ operating in dual-phase mode. The input range for this evaluation board is 10 V to 15 V, and the regulated output voltage is 1.09 V with a maximum 50 A output current. A switching frequency (fSW) of 300 kHz is chosen to achieve a good balance between efficiency and the sizes of the power components. The ADP1850 includes externally adjustable soft start, output overvoltage protection, externally adjustable current limit, power good, tracking function, and a programmable oscillator frequency that ranges from 200 kHz to 1.5 MHz. The ADP1850 provides an output voltage accuracy of ±0.85% from −40°C to +85°C and ±1.5% from −40°C to +125°C junction temperature. This controller may be powered from a 2.75 V to 20 V supply is available in a 32-lead 5 mm × 5 mm LFCSP package. ADP1850 DEVICE DESCRIPTION The ADP1850 is a dual-channel, step-down switching controller with integrated drivers for external N-channel synchronous ADP1850DP EVALUATION BOARD GND TERMINAL ADP1850 GND TERMINAL 09456-001 VOUT TERMINAL VIN TERMINAL Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 12 UG-205 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Output Capacitors .........................................................................3 Evaluation Board Description......................................................... 1 MOSFET Selection........................................................................3 ADP1850 Device Description......................................................... 1 Test Results .........................................................................................4 ADP1850DP Evaluation Board....................................................... 1 Evaluation Board Operating Instruction .......................................5 Revision History ............................................................................... 2 Other Information About the Evaluation Board PCB Layout......6 Component Design .......................................................................... 3 Evaluation Board Schematics and Artwork...................................7 Inductor Selection ........................................................................ 3 Ordering Information.................................................................... 11 Input Capacitors ........................................................................... 3 Bill of Materials........................................................................... 11 REVISION HISTORY 8/11—Rev. 0 to Rev. A Changes to Table 3.......................................................................... 11 11/10—Revision 0: Initial Version Rev. A | Page 2 of 12 Evaluation Board User Guide UG-205 COMPONENT DESIGN For information about selecting power components and calculating component values, see the ADP1850 data sheet. OUTPUT CAPACITORS INDUCTOR SELECTION A 0.47 μH inductor with a 50 A saturation current rating and a 30 A average current rating (744355147 from Würth Elektronik) is selected. This is a compact inductor with an iron alloy core, which offers high performance in terms of low RDC and low core loss. An alternative to the 744355147 is the SER1408-301M (300 nH with about 40 A in saturation current and average current rating) from Coilcraft. If higher efficiency or lower DCR is desired, choose a physically larger inductor with approximately the same inductance value. INPUT CAPACITORS Because of the large input current ripple requirement, four 180 μF/16 V OS-CON™ capacitors have been selected for the input bulk capacitance. In addition, one MLCC decoupling capacitor (10 μF/25 V) is used at each of the high-side MOSFET. A total of six 560 μF/2.5 V OS-CON™ capacitors is used at the output. These aluminum solid capacitors with conductive polymer have low ESR and high current ripple rating. In addition, four 47 μF MLCCs are added for filtering out the high frequency voltage ripples. MOSFET SELECTION For low output or low duty cycle, select a high-side MOSFET with fast rise and fall times and with low input capacitance to minimize charging and switching power loss. As for the synchronous rectifier (low-side MOSFET), select a MOSFET with low RDSON because the switching speed is not critical and there is no switching power loss in the low-side MOSFET. For the high-side MOSFETs of each channel, two BSC080N03LS connected in parallel from Infineon Technologies in the PGTDSON-8 or Super-SO8 package are selected. This part has low input capacitance (1.2 nF) and fast transition time (3 ns). For the low-side MOSFET, two BSC030N03LS connected in parallel, with RDSON of 4.7 mΩ at a VGS of 4.5 V, are selected. Rev. A | Page 3 of 12 UG-205 Evaluation Board User Guide TEST RESULTS TA = 25°C. 100 90 SW1 80 1 SW2 60 3 50 40 4 30 20 VIN = 12V VOUT = 1.09V fSW = 300kHz 0 0 10 20 30 40 OUTPUT RIPPLE 50 LOAD (A) 09456-002 10 CH1 10V CH3 10V Figure 2. Efficiency CH4 20mV M2µs A CH3 10.2V 09456-005 EFFICIENCY (%) 70 Figure 5. Output Ripple, 50 A Load 0.10 fSW = 300kHz, 25A LOAD 0.08 LINE REGULATION (%) 0.06 0.04 1A TO 16A STEP LOAD 0.02 3 0 –0.02 OUTPUT RESPONSE VOUT = 1.09V 4 –0.04 –0.10 0 5 10 15 20 25 VIN (V) 09456-003 –0.08 Figure 3. Line Regulation VIN = 12V, fSW = 300kHz 0.2 0.1 0 VOUT = 1.09V –0.2 –0.3 –0.4 –0.5 0 10 20 30 40 50 09456-004 LOAD REGULATION (%) 0.3 –0.1 M100µs A CH3 Figure 6. Step Load Transient, VOUT 0.5 0.4 CH3 10A Ω CH4 20mV LOAD (A) Figure 4. Load Regulation Rev. A | Page 4 of 12 10.2A 09456-006 –0.06 Evaluation Board User Guide UG-205 EVALUATION BOARD OPERATING INSTRUCTION 1. 2. Connect Jumper J3 (EN) to the high position to enable Channel 1 and Channel 2 of the ADP1850. Jumper J3 is connected to both EN1 and EN2. Connect Jumper J4 (FREQ) to the low position for 300 kHz operation. 3. 4. Connect Jumper J1 (SYNC) to the high position for PWM operation. Connect the positive terminal of the input power supply to the input terminal, T1. The input range is 10 V to 15 V. Table 1. Jumper Description Jumper J1 Description SYNC Default Factory Setting High J3 EN High J4 FREQ Low Function Connect high for PWM. For synchronization to an external clock, run the external clock source to this pin. Connect high to enable Channel 1 and Channel 2 of the ADP1850 or low to disable both channels. Connect low for 300 kHz or high for 600 kHz operation. This 50 A evaluation board is configured for operation at 300 kHz. Connect J4 low. Table 2. Performance Summary (TA = 25°C) Parameter VIN fSW VOUT IOUT VOUT Ripple, DC Load VOUT Deviation upon Step Load Release Condition 10 V to 15 V Switching frequency, 300 kHz 1.09 V 0 A to 50 A 16 mV at 50 A load 3.3% with a 20 A step load Rev. A | Page 5 of 12 UG-205 Evaluation Board User Guide OTHER INFORMATION ABOUT THE EVALUATION BOARD PCB LAYOUT As seen in Figure 1, the layout of this evaluation board is not optimized for the smallest PCB area. It is laid out in such a way that any of the components can be desoldered and replaced easily with different components with a hand soldering iron so that the user can modify the existing design without acquiring a new PCB layout. The physical size of the compensation components is 0603, which is selected for its ease of hand soldering when reworking the board is needed. The size of these components can be 0402 or even smaller in the final design. Note that there are extra place holders for input bulk capacitors, output filter capacitors, and MOSFETs. The user can remove, add, or change any of these power components to achieve a particular design objective. The track functions, where TRK1 and TRK2 are pulled up to VCCO through 0 Ω dummy resistors, are not used on this evaluation board. Also dummy 0 Ω resistors are placed at the driver gates, DHx and DLx, for evaluation purpose only and can be removed in the final design. Furthermore, many test points are placed on the evaluation board so that the user can easily evaluate the performances of the ADP1850 with an oscilloscope. See Figure 7, the evaluation board schematic, for more information. Rev. A | Page 6 of 12 1 1 VDL 1 2 3 4 1 VDL TP16 TURRET T11 T2 TURRET 2 RB0 open RFREQ 100nf CVIN 1 J1 VCC 2 T10 VIN 1 TP3 J4 SYNC 3 2 Way Link VCC 1 J3 VCC RT22 RT21 0 1.0uF TP5 CDR VDL VCC 1.0uF TRK2 EN1 0 R103 CV5 2 1 REN11 RVCC0 REN12 VIN 3 2 Way Link FREQ open RV5 SYNC 2 Way Link 3 1 2 1 2 3 4 2 T1 VIN 137k RR2 EN2 8 7 6 5 4 3 2 1 8.87k EN2 FREQ AGND VDL VCCO VIN SYNC EN1 U1 3300pF 180pF RC1 CC11 CC12 COMP1 137k RR1 10K FB1 32 9 TRK2 8.25k RF11 SS1 23 20 21 SW2 TP4 DH2 RPG2 open TP10 SW2 0 RDL2 22pF FB1 COMP1 SS1 1.74k RILIM21 CLIM2 VCC TP14 100nf CBST2 0 RDH2 0 RDL1 0 RDH1 100nf CBST1 TP8 SW1 1.74k ADP1850-LFCSP 17 18 PGND2 19 DL2 DL1 PGND1 22 DH1 SW1 24 22pF CLIM RILIM11 TP2 100nf R1 0 CSS1 TP6 TP17 1 RF12 30 31 FB1 TRK1 FB2 COMP1 COMP2 10 27 11 28 29 RAMP2 12 SS1 SS2 13 PGOOD1 PGOOD2 14 RAMP1 1 26 1 25 ILIM1 ILIM2 15 BST1 BST2 16 1 0 DH1 DH2 DL2 DL1 TP11 TP7 TP13 VCC TP12 open RPG1 1 RT12 RGCS2 22.6k 1 Vin = 10V to 15V 1 1 1 TRK1 1 RT11 RGCS1 22.6k TP9 1 QH1 BSC080N03 D4 S3 D3 S2 D2 S1 D1 QL3 BSC030N03 D4 D3 D2 D1 S3 S2 S1 D4 D3 D2 D1 BSC030N03LS S3 S2 S1 QL1 G G QH3 BSC080N03 D4 S3 D3 S2 D2 S1 D1 G 10uF/25V QH4 D4 D3 D2 D1 S3 S2 S1 D4 D3 D2 D1 10uF 25V CIN21 BSC080N03LS S3 S2 S1 BSC030N03LS QL4 QL2 BSC030N03 D4 S3 D3 S2 D2 S1 D1 S3 S2 S1 D4 D3 D2 D1 BSC080N03LS QH2 Cin11 10uF 25V VIN Cin12 G G G 1 1 Figure 7. Evaluation Board Schematic G Rev. A | Page 7 of 12 G TP1 0.47uH L2 10uF/25V CIN22 VIN RSNB2 open open CSNB2 CSNB1 open RSNB1 open L1 0.47uH VOUT1 180uF + CIN20 CON12 J8 1 2 3 4 5 6 7 8 9 10 11 12 560uF 560uF 560uF open VOUT1 560uF CON12 J9 560uF + COV6 + COV4 + COV2 560uF + COV8 open + COV7 + COV5 + COV3 + COV1 180uF + CIN10 VIN CIN13 180uF 1 2 3 4 5 6 7 8 9 10 11 12 VOUT2 47uF + COV23 47uF COV22 47uF + 47uF GND 1 2 3 4 T5 T8 T9 TURRET 1 T6 TURRET 1 1 2 3 4 VOUT1 = 1.09V 180uF + CIN23 + COV12 + COV13 + 09456-007 VCC Evaluation Board User Guide UG-205 EVALUATION BOARD SCHEMATICS AND ARTWORK Evaluation Board User Guide 09456-008 UG-205 09456-009 Figure 8. Top Silkscreen Figure 9. Top Layer Rev. A | Page 8 of 12 UG-205 09456-010 Evaluation Board User Guide 09456-011 Figure 10. Second Layer (AGND Plane) Figure 11. Third Layer (PGND Layer) Rev. A | Page 9 of 12 Evaluation Board User Guide 09456-012 UG-205 09456-013 Figure 12. Bottom Layer (PGND Layer) Figure 13. Bottom Silk Screen Rev. A | Page 10 of 12 Evaluation Board User Guide UG-205 ORDERING INFORMATION BILL OF MATERIALS Table 3. Quantity 1 4 4 4 2 2 2 2 6 4 Reference Designator U1 CIN10, CIN13, CIN20, CIN23 CIN11, CIN12, CIN21, CIN22 CSS1, CBST1, CBST2, CVIN CV5, CDR RB0, RVCCO RGCS1, RGCS2 RR1, RR2 COV1, COV2, COV3, COV4, COV7, COV8 COV12, COV13, COV22, COV23 L1, L2 RF12 RF11 QH1, QH2, QH3, QH4 QL1, QL2, QL3, QL4 CC11 CC12 RC1 RLIM11, RLIM21 CLIM1, CLIM2 J1, J2, J3, J4 R103, RT11, RT21, RDH1, RDH2, RDL1, RDL2, R1, R2 T8, T9, T10, T11 4 T1, T2, T5, T6 4 2 1 1 4 4 1 1 1 2 2 4 9 Description DUT OSCON, 180 μF, 16 V MLCC, 10 μF, X7R, 25 V MLCC, 100 nF, X7R, 25 V MLCC, 1.0 μF, X5R, 6.3 V Resistor, 2 Ω Resistor, 22.6 kΩ Resistor, 137 kΩ OSCON, 560 μF, 2.5V Manufacturer Analog Devices, Inc. Sanyo Murata Murata Murata Vishay Vishay Vishay Sanyo Part No. ADP1850 16SEP180M GRM32DR71E106KA12 GRM188R71E104KA01 GRM185R60J105KE21 CRCW06032R00F CRCW06032262F CRCW06031373F 2SEPC560MZ MLCC, 47 μF, X5R, 1206 Inductor, 0.47 μH Resistor, 10 kΩ Resistor, 8.25 kΩ N MOSFET, 30 V, 9 mΩ N MOSFET, 30 V, 4.5 mΩ MLCC, 3300 pF MLCC, 180 pF Resistor, 8.87 kΩ Resistor, 1.74 kΩ MLCC, 22 pF 3-terminal jumpers, 0.1" spacing Resistor, 0 Ω Murata Wurth Elektronik Vishay Vishay Infineon Infineon Vishay Vishay Vishay Vishay Vishay GRM31CR60J476ME19 744355147 CRCW06031002F CRCW06038251F BSC080N03LS BSC030N03LS VJ0603Y332KXAA VJ0603Y181KXAA CRCW06038871F CRCW06031741F VJ0603A220KXAA Vishay CRCW06030R00F Test points, turret, 110-mil through hole Terminals, 20 A rated Keystone Electronics Corp. 1502-1 Keystone Electronics Corp. 8191 Rev. A | Page 11 of 12 UG-205 Evaluation Board User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. 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