Application Note 1758 Author: Manjing Xie ISL6420BEVAL7Z - User Guide Introduction The ISL6420BEVAL7Z is a negative buck boost converter, which features the ISL6420B PWM controller. The ISL6420B is a wide input range, synchronous buck controller. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology for up to 25A load current. The ISL6420B integrates control, output adjustment, monitoring and protection functions into a single package. The ISL6420BEVAL7Z is configured with the ISL6420B in an inverting buck/boost topology. The output voltage is set at 5V. At 12V input, the maximum load current is 25A. All the necessary components are with 2.2”x 1.25” PCB area. The ISL6420B provides simple, voltage mode control with fast transient response. The operating frequency can be adjustable from 100kHz to 1.4MHz. The ISL6420B is offered in a space saving 4x4 QFN and easy-to-use 20 Ld QSOP package. When used in an inverting buck/boost converter, the ISL6420B sees the VIN + VOUT and the inductor current as higher than the load current. FIGURE 1. ISL6420BEVAL7Z TOP VIEW (ONE-SIDE PLACEMENT) Evaluation Board Specifications TABLE 1. BOARD ELECTRICAL SPECIFICATIONS SPEC DESCRIPTION MIN. TYP. MAX. UNIT VIN Input Voltage VOUT Output Voltage, 0A <IOUT <20A -4.75 -5.0 -5.25 V IOUT Maximum Load Current, VIN > 10V 20 A Fsw Switching Frequency 280 kHz η Efficiency, VIN = 12V, IOUT = 20A 93 % 5 16 V Controller Key Features • Wide VIN Range - 5.6V to 28V - 4.5V to 5.5V • Resistor-Selectable Switching Frequency from 100kHz to 1.4MHz • Voltage Margining and External Reference Tracking Modes • Upper MOSFET rDS(ON) for Current Sensing • Support Pre biased Start-Up Recommended Equipment • Programmable Soft-Start The following equipment is recommended for evaluation: • Extensive Protection Functions: - Overvoltage, Overcurrent, Undervoltage • 0V to 20V power supply with 20A source current capability • Electronic load capable of sinking 25A • Digital Multimeters (DMMs) • 100MHz Quad-Trace Oscilloscope TABLE 2. RECOMMENDED COMPONENT SELECTION FOR QUICK EVALUATION VIN (v) VOUT (V) IOUT (A) UPPER MOSFET LOWER MOSFET INDUCTOR FSW/RT TOTAL CERAMIC CIN 12 -5 20 2X BSC057N03 LS 2X BSC057N03 LS SER2010-901ML 300kHz/52.3kΩ 4 x 10µF 12 -5 10 1X BSC057N03 LS 1X BSC030N03 LS SER2009-901ML 500kHz/31.6kΩ 2 x 10µF Please contact Intersil Sales for assistance. June 8, 2012 AN1758.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2012. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1758 Quick Test Setup Probe Set-up 1. Ensure that the Evaluation board is correctly connecting to the power supply and the electronic load prior to applying any power. Please refer to Figure 2 for proper set-up. 2. Connect jumpers J1, J2, J3 and J8 in the positions specified in Table 3. OUTPUT CAP OUTPUT OUTPUT CAP CAP OR ORMOSFET MOSFET 3. Turn on the power supply, VIN < 16V. 4. Adjust input voltage VIN within the specified range and observe output voltage. The output voltage variation should be within 5%. 5. Adjust load current within 20A. The output voltage variation should be within 5%. 6. Use oscilloscope to observe output ripple voltage and phase node ringing. For accurate measurement, please refer to Figure 3 for proper probe set-up. 7. Optimization. Please refer to Table 2 on page 1 for optimization recommendation. NOTE: Test points: P3, 4, 5, 6 (GND, VOUT, GND, VIN) are for voltage measurement only. Do not allow high current through these test points. FIGURE 3. OSCILLOSCOPE PROBE SET-UP Evaluation Board Usage Component Voltage Stress The controller, ISL6420B, MOSFETs and the ceramic input capacitors are connected from the VIN rail to the VOUT rail. Thus, these components see a voltage stress of the sum of VIN and VOUT. Setting VOUT V + _ LOAD The output voltage is set by the resistor divider, R4 and R1. R1 + R4 V OUT = -------------------- × 0.6V R4 (EQ. 1) Duty Cycle Calculation A The duty cycle of the inverting buck/boost converter can be calculated by Equation 2: V V OUT D = ---------------------------V OUT + V IN − VIN + _ + (EQ. 2) Component Selection Inductor A The inductor is selected by the DC current, saturation current and overall thermal performance. The inductor DC current can be calculated by Equation 3: FIGURE 2. ISL6420BEVAL7Z TEST SET-UP I OUT I LDC = ------------1–D TABLE 3. JUMPER POSITION SHUTDOWN J1/GPIO1 J2/GPIO2 J3/VMSET J8/EN/SS LOW LOW DOES NOT MATTER DISABLE NORMAL LOW LOW VCC5 ENABLE Margining Up LOW HIGH OPEN/R12 set ΔVO ENABLE Margining Down HIGH LOW OPEN/R12 set ΔVO ENABLE (EQ. 3) Maximum DC current occurs at minimum input with Equation 4: V inmin + V OUT I LDCmax = I OUT × ------------------------------------V (EQ. 4) inmin Inductor core loss is related to the switching frequency and the inductor ripple current. Please refer to Equation 5 for inductor ripple estimation ( 1 – D ) × V OUT Δi P-P = ------------------------------------L × F SW (EQ. 5) Inductor vendors provide formula and/or design tools for core loss estimation. Please refer to the inductor datasheet for thermal stress estimation. 2 AN1758.0 June 8, 2012 Application Note 1758 Output Capacitors The peak inductor current is as shown with Equation 6: Δi P-P I LPK = I LDCmax + ------------2 (EQ. 6) Please select inductor with saturation current higher than the maximum peak inductor current. For overcurrent protection setting, please set IOC higher than the maximum peak current and refer to the ISL6420B datasheet, FN6901 for details. It is recommended to use a combination of aluminum electrolytic capacitors with high capacitance and low ESR ceramic capacitors at the output for optimum ripple and load transient performance. The total output RMS current can be estimated with Equation 8: ( Δi P-P ) 2 D I OUTRMS = I O × ------------- + --------------------- ( 1 – D ) 12 1–D (EQ. 8) Where ΔiP-P is the inductor peak-to-peak ripple. Input Capacitors The input capacitors can be connected from VIN to GND, e.g. C7, C14 and C18, or from VIN to VOUT, e.g. C8 and C9. Several trade-offs need to be considered regarding the arrangement of the input capacitors. It is generally recommended that bulk input capacitors (which are usually of the aluminum electrolytic type), be connected from VIN to GND, C18 with small ceramic capacitors, Cin_ce (C7 and C14, as shown in the schematic in parallel). These capacitors are for lowering the input power supply impedance, thus stabilizing the overall system. Worst case for the total output RMS current is at minimum VIN and maximum load. The input capacitor across the MOSFETs, CF can alleviate the RMS current through the output capacitors. Accurate RMS current distribution can be obtained by simulation. The rule of thumb calculation of the RMS through the output capacitors is as shown with Equation 9: ( Δi P-P ) 2 D CF I CORMS = I O × ------------- + --------------------- ( 1 – D ) × --------------------------12 1–D Coce + CF (EQ. 9) Ceramic capacitors, CF (C8 and C9, as shown in the schematic) are connected from VIN to VOUT for ripple current filtering. C8 and C9 should be rated above the sum of VOUT and VIN. Where Coce is the total output ceramic capacitance. The total input RMS current can be estimated with Equation 7: Prior to the enabling or the VCC reaching UVLO threshold, the ISL6420B draws 3mA current. This shutdown current forward bias the low-side MOSFET body diode. Thus, the output voltage is reversed with the voltage amplitude clamped at the diode-forward voltage. ( Δi P-P ) 2 D I INRMS = I O × ------------- + --------------------- ( D ) 12 1–D (EQ. 7) Where ΔiP-P is the inductor peak-to-peak ripple. Worst case for input RMS current is at minimum VIN. The rule of thumb is that the input ripple current be shared by all the input ceramic capacitors, C7, C14, C8 and C9. From the output ripple perspective, is preferred to place all capacitors from VIN to VOUT. In some applications, the voltage across VIN and VOUT is so high, that the cost of the high voltage ceramic capacitors does not justify the benefit. However, it is required to place a small ceramic capacitor across the MOSFETs. 3 Starting with No Load If this condition is not acceptable, a dummy load can be used to bypass this shutdown current. The dummy resistor can be calculated by Equation 10: V neg R DUMMY = -----------I OP (EQ. 10) where, Vneg is the allowable negative voltage at the output. IOP is the operating current by the ISL6420B, which is 3mA maximum. AN1758.0 June 8, 2012 Application Note 1758 Typical Performance Curves 98 -5.05 96 -5.03 94 REGULATION (V) EFFICIENCY (%) -5.02 92 VIN = 12V 90 88 86 -5.01 5V/20A -5.00 -4.99 84 -4.98 82 -4.97 80 -4.96 0 5 10 15 LOAD (A) 20 25 0 5 10 15 20 25 LOAD (A) FIGURE 4. EFFICIENCY vs LOAD CURRENT (VIN = 12V, REFER TO TABLE 2 FOR COMPONENTS) FIGURE 5. LOAD REGULATION, (V IN = 12V) VO(AC) AT 50mV/DIV TIME AT 2µs/DIV FIGURE 6. OUTPUT RIPPLE (V IN = 12V, V 0 = 5V, LOAD = 0A) VO(AC) AT 50mV/DIV TIME AT 2µs/DIV FIGURE 7. OUTPUT RIPPLE (V IN = 12V, V 0 = 5V, LOAD = 20A) VO AT 1V/DIV VO AT 1V/DIV VIN AT 5V/DIV VIN AT 5V/DIV VEN/SS AT 2V/DIV VEN/SS AT 2V/DIV TIME AT 50ms/DIV FIGURE 8. SOFT - START (CSS - 0.47µF, CDEL = 0.1µF, NO LOAD, All SIGNAL REFERRING TO GND) 4 TIME AT 50ms/DIV FIGURE 9. SOFT - START (CSS - 0.47µF, CDEL = 0.1µF, 20A LOAD, SIGNAL REFERRING TO GND) AN1758.0 June 8, 2012 Application Note 1758 Typical Performance Curves (Continued) VO AT 1V/DIV VO (AC) AT 200mV/DIV VIN AT 2V/DIV ISTEP AT 10A/DIV VEN/SS AT 2V/DIV TIME AT 50µs/DIV TIME AT 100ms/DIV FIGURE 10. LOAD TRANSIENT (LOAD STEP FROM 5A TO 15A, di/dt = 2A/µs) 5 FIGURE 11. OVERCURRENT PROTECTION AN1758.0 June 8, 2012 ISL6402BEVAL7Z Schematic P6 1 J3 VCC5BB VOUT 2 2 1 2 2 VOUT C30 DNP VOUT 1 R3 1k 1 2 J7 C33 DNP 2 1 N16246185 C3 2 2 1 C23 DNP 1 2 C25 DNP 2 2 1 R4 16.5K R11 2 P4 1 VOUT R1 121K VOUT VOUT 2 VCC5BB 1 C29 1uF 2 2 2 1 C27 47uF C32 47uF C19 1000pF VOUT C10 0.47uF VOUT 1 1 1 BSC057N03LS R19 51K 2 2 3 1 1 3 1 R17 1 C13 0.1uF 1 1 C26 180uF 2 10uF C17 GND C28 DNP 1 1 2 EN/SS C15 47uF Q4 U1 J8 C31 47uF 2 2 CDEL C24 180uF R9 1.2 Q2 BSC057N03LS 3 PGND 1 L1 0.9uH 5 LGATE 1 1 R2 12.1K 1 PGOOD 1 4 1 2 PVCC ENSS 20 1 VOUT PHASE FB COMP 19 2 C2 100pF C1 1.5nF 18 COMP1 RT J6 2 2 1 ENSS_BB 2 UGATE 6 PHASEBB 0.22uF 2 1 RT116 FB1 17 SGND 7 1 C11 1 1 R5 52.3K BOOT DNP 2 1 D5 2 BAT54-02-V-G R14 0 GND R18 51K 2 1 470pF 1 0 2 VOUT Application Note 1758 2 VIN 8 1 GND 2 2.26K 2 15 GPI02 9 1 P3 GND 1 14 GPI01 VCC5 2D2 Q3 BSC057N03LS 1 1 VMSET R8 10 2 VCC5BB 13 BSC057N03LS 1 C16 0.1uF 1000pF 1 OCSET GND P5 2 12 VIN 2 REFOUT VOUT 1 1 1 11 J5 1 1 isl6420BIA VIN C18 100uF C20 DNP C6 2 6 C4 10uF 1 C7 22uF 2 GPIO2 VOUT 2 Q1 2 VOUT 1 2 3 1 2 1 R6 DNP C14 22uF C9 22uF J2 2 2 C8 22uF GPIO1 2 1 1 1 3 1 2 VMSET 1 2 J4 VIN J1 C12 2.2uF 2 VIN 1 1 3 AN1758.0 June 8, 2012 Application Note 1758 TABLE 4. BILL OF MATERIALS ITEM QTY PART REFERENCE VALUE DESCRIPTION PART NUMBER MANUFACTURER ESSENTIAL COMPONENTS 1 1 C1 1500pF Ceramic CAP, NP0 or C0G, sm0603 GENERIC GENERIC 2 1 C2 100pF Ceramic CAP, NP0 or C0G, sm0603 GENERIC GENERIC 3 1 C3 470pF Ceramic CAP, NP0 or C0G, sm0603 GENERIC GENERIC 4 2 C4, C17 10µF Ceramic CAP, X5R, 10V, sm0805 GENERIC GENERIC 5 2 C6, C19 1000pF Ceramic CAP, NP0 or C0G, sm0603 GENERIC GENERIC 6 3 C7, C8, C9, C14 22µF Ceramic CAP, X5R , 25V, sm1210 GENERIC GENERIC 7 1 C10 0.47µF Ceramic CAP, X5R, 16V, sm0603 GENERIC GENERIC 8 1 C11 0.22µF Ceramic CAP, X5R, 16V, sm0603 GENERIC GENERIC 9 1 C12 2.2µF Ceramic CAP, X5R, 16V, sm0603 GENERIC GENERIC 10 2 C13, C16 0.1µF Ceramic CAP, X5R, 50V, sm0603 GENERIC GENERIC 11 4 C15, C27, C31, C32 47µF Ceramic CAP, X5R, 10V, sm1210 GENERIC GENERIC 12 1 C18 100µF Alum. Cap, 50V EMVA500ADA101MHA0G United Chemi-Con 13 2 C24, C26 180µF OSCON, 16V, Radial 8x9 16SEPC180MX SANYO 14 1 C29 1µF GENERIC GENERIC 15 1 D5 BAT54-02-V-G Vishay 16 1 L1 Inductor SER2010-901ML Coilcraft 17 4 Q1, Q2, Q3, Q4 Single Channel NFET, 30V BSC057N03LS G Infineon 18 1 R1 121kΩ Resistor, sm0603, 1% GENERIC GENERIC 19 1 R2 12.1kΩ Resistor, sm0603, 1% GENERIC GENERIC 20 1 R3 1kΩ Resistor, sm0603, 1% GENERIC GENERIC 21 1 R4 16.5kΩ Resistor, sm0603, 1% GENERIC GENERIC 22 1 R5 52.3kΩ Resistor, sm0603, 1% GENERIC GENERIC 23 1 R8 2.26kΩ Resistor, sm0603, 1% GENERIC GENERIC 24 1 R9 1.2Ω Resistor, sm0603, 10% GENERIC GENERIC 25 2 R11, R14 0Ω Resistor, sm0603, 10% GENERIC GENERIC 26 1 R17 1Ω Resistor, sm0603, 1% GENERIC GENERIC 27 2 R18, R19 51kΩ Resistor, sm0603, 10% GENERIC GENERIC 28 1 U1 ISL6420BIAZ INTERSIL Ceramic CAP, X5R, 25V, sm0603 Schottky Diode, 30V, SOD523 0.9µH PWM CONTROLLER, 20Ld QSOP OPTIONAL COMPONENTS 29 D2, R6, C20, C28, C23, C25, C30, C33 DO NOT POPULATE EVALUATION HARDWARE 30 4 J4, J5, J6, J7 HDWARE, MTG, CABLE TERMINAL, 6-14AWG, LUG&SCREW, ROHS KPA8CTP BERG/FCI 31 4 J1, J 2, J3, J8 1x3 Header GENERIC GENERIC 32 4 J1, J2, J3, J8 Connector Jumper SPC02SYAN Sullins 33 7 P3, P4, P5, P6 1514-2 Keystone 7 Test Points AN1758.0 June 8, 2012 Application Note 1758 ISL6420BEVAL7Z PCB Layout FIGURE 12. TOP SILKSCREEN 8 FIGURE 13. TOP LAYER AN1758.0 June 8, 2012 Application Note 1758 ISL6420BEVAL7Z PCB Layout FIGURE 14. SECOND LAYER (SOLID GROUND) 9 (Continued) FIGURE 15. THIRD LAYER AN1758.0 June 8, 2012 Application Note 1758 ISL6420BEVAL7Z PCB Layout FIGURE 16. BOTTOM LAYER (Continued) FIGURE 17. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 10 AN1758.0 June 8, 2012