Data Sheet No. PD60322 iP2004 SYNCHRONOUS BUCK LGA POWER BLOCK Features • • • • • • • • • • 40A Multiphase building block No derating up to TC = TPCB = 95ºC Optimized for low power loss Bias supply range of 4.5V to 6.0V Operation up to 1.5MHz Over temperature protection Bi-directional Current flow Under Voltage Lockout LGA interface 7.7mm x 7.7mm x 2.2mm package Applications • • • High frequency, Multi-phase Converters Low Duty-Ratio, High Current Microprocessor Power Supplies High Frequency Low Profile DC-DC Converters Description The iP2004 is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 7.7mm x 7.7mm x 2.2mm power block. The only additional components required for a complete multiphase converter are a PWM controller, the output inductors, and the input and output capacitors. Package Description Interface Connection Standard Quantity T&R Orientation iP2004 LGA 10 N/A iP2004TR LGA 2000 Figure 18 Typical Application VIN VIN Enable Seq VCC Sync Track1 5V_sns Vo3 Track2 Ph_En1 Vref VP1 VOUT VP2 FB1 VP2 FB2 FB2 NC OCSet1 Rt Comp2 PGOOD1 VIN VSW 1 VOUT VSW PWM VSW 1 PGND PGND VP2 iP2004 PWM2 Comp1 VSWS2 ENABLE PWM1 Ph_En2 VSWS1 VDD OCSet1 VSW 2 PGOOD2 SS1 SS2 GND IR3623 NC VSWS1 VSWS2 VDD VIN ENABLE VSW2 VSW PWM PGND PGND FB2 iP2004 Page 1 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Absolute Maximum Ratings VIN to PGND ……………………..…….…. -0.5V to 16V VDD to PGND …………………….….……. -0.5V to 6.5V PWM to PGND ………………….………… -0.5V to VDD + 0.5V (Note 1) ENABLE to PGND ………………………... -0.5V to VDD + 0.5V (Note 1) Storage Temperature …………..…………. -60ºC to 150ºC Block Temperature …………...…………… -40ºC to 150ºC (Note 5) ESD Rating………………………….………. HBM Class 1B (500V) MM Class B (200V) MSL Rating………………………….………. 3 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those listed in the “Recommended Operating Conditions” section of this specification is not implied. Recommended Operating Conditions PARAMETER Min Typ Max Units Supply Voltage (VDD) 4.5 - 6.0 V Input Voltage (VIN) 3.3 - 13.2 V Output Voltage (VOUT) - - 8.0 V Output Current (IOUT) - - 40 A 250 - 1500 kHz - - 85 % Minimum VSW On Time 60 - - ns Block Temperature -40 - 125 ºC Switching Frequency (FSW) On Time Duty Cycle Conditions VDD = 5.0V, VIN = 12V Electrical Specifications These specifications apply for TBLK = 0ºC to 125ºC and VDD = 5.0V, unless otherwise specified. PARAMETER Min Typ Max Units Conditions Ploss - 7.4 9.1 W VIN = 12V, VDD = 5.0V, VOUT = 1.3V, IOUT = 40A, FSW = 1MHz, LOUT = 0.3uH, TA = 25ºC (Note 3) Quiescent Current - - 1.0 mA VIN = 12V, ENABLE = 0V Page 2 of 15 www.irf.com Power Block Losses VIN 12/22/2007 Data Sheet No. PD60322 iP2004 PARAMETER Min Typ Max Units Conditions Supply Current (Stand By) - 1.1 2.0 mA VDD = 5.0V, ENABLE = 0V Supply Current (Operating) - 70 110 mA VIN = 12V, VDD= EN ABLE = 5.0V, FSW = 1MHz, 10% DC, VCC Rising 3.7 - 4.5 V Hysterisis 140 185 230 mV Logic Level Low Threshold (VIL) - - 0.8 V Logic Level High Threshold (VIH) 2.0 - - V Threshold Hysterisis - 100 - mV Weak pull-down current - 10 - µA Rising Propagation Delay (TPDH) - 40 - ns Falling Propagation Delay (TPDL) - 75 - ns VDD Power-On Reset (POR) VI Rising & Falling ENABLE INPUT Schmitt Trigger Input VCC = POR to 6.0V PWM INPUT Logic Level Low Threshold (VIL) - - 0.8 V Logic Level High Threshold (VIH) 2.0 - - V Threshold Hysterisis - 100 - mV Weak pull-down current - 2 - µA Rising Propagation Delay (TPDH) - 50 - ns Falling Propagation Delay (TPDL) - 35 - ns Schmitt Trigger Input VCC = POR to 6.0V (Note 4) Notes: 1. Must not exceed 6.5V. 2. Guaranteed by design, not tested in production. 3. Measurement made with six 10µF (TDK C3225X5R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins (see Figure 9). 4. TPDH and TPDL are not associated with rise and fall times. Does not affect Power Loss (see Figure 10). 5. Block Temperature is defined as any Die temperature within the package. Page 3 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Power Loss Curve 14 13 VI = 12V VD = 5.0V VO = 1.3V FSW = 1MHz LO = 300nH T BLK = 125ºC 12 11 10 Maximum Power Loss(W) 9 8 7 Typical 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Output Current(A) Figure 1Power Loss versus Output Current SOA Curve Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 44 40 36 Safe Operating Area Output Current (A) 32 28 24 20 Tx 16 12 VI = 12V VD = 5.0V VO = 1.3V Fsw = 1MHz LO = 300nH 8 4 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) Figure 2 Safe Operating Area (SOA) versus PCB and CASE temperatures (See page 6 for details) Page 4 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Typical Performance Curves 9.6 1.40 7.1 1.30 VD = 5.0V VO = 1.3V 1.35 VI = 12.0V 8.4 IO = 40A FSW = 1MHz 4.8 1.15 3.6 1.10 2.4 1.05 1.2 1.00 0.0 0.95 -1.2 -2.4 0.90 3 4 5 6 7 8 9 10 11 12 Power Loss (Normalized) 1.20 4.7 LO = 300nH T BLK = 125ºC 3.5 1.15 2.4 1.10 ` 1.05 1.2 1.00 0.0 0.95 -1.2 -2.4 0.90 13 0.8 1.1 1.3 1.6 1.8 Input Voltage (V) 2.1 2.3 2.6 2.8 Figure 3 Normalized Power Loss vs. Input Voltage 1.12 2.8 VI = 12.0V VI = 12.0V VO = 1.3V VDD = 5.0V IO = 40A 1.04 1.10 1.0 FSW = 1MHz 0.0 0.98 -0.5 0.96 -1.0 0.94 -1.5 5.50 1.08 Power Loss (Normalized) Power Loss (Normalized) 1.00 1.06 1.4 1.04 0.9 1.02 0.5 1.00 0.0 0.98 -0.5 0.20 0.30 0.40 Figure 5 Normalized Power Loss versus Drive Voltage VDD = 5.0V 100 VO = 1.3V VO = 1.3V 4.7 IOUT = 40A 90 LO = 300nH LO = 300nH 1.10 2.4 1.05 1.2 1.00 0.0 0.95 -1.2 0.90 -2.4 0.85 -3.6 0.80 -4.7 0.75 -5.9 0.70 -7.1 1500 Average Supply Current (mA) 3.5 T BLK = 125ºC SOA Temp Adjustment (ºC) Power Loss (Normalized) Figure 6 Normalized Power Loss vs. Inductance 5.9 IOUT = 40A 1.15 -0.9 0.80 0.70 VI = 12.0V VI = 12.0V VDD = 5.0V 1.20 0.60 110 7.1 1.25 0.50 Output Inductor (µH) Drive Voltage (V) 1.30 1.9 T BLK = 125ºC 0.96 0.10 -2.0 6.00 5.75 FSW = 1MHz SOA Temp Adjustment (ºC) 0.5 SOA Temperature Adjustment (ºC) T BLK = 125ºC 1.02 5.25 2.4 VO = 1.3V IOUT = 40A LO = 300nH 5.00 3.3 Figure 4 Normalized Power Loss vs. Output Voltage 1.5 4.75 3.1 Output Voltage (V) 1.06 0.92 4.50 SOA Temp Adjustment (ºC) 6.0 SOA Temp Adjustment (ºC) Power Loss (Normalized) 1.20 T BLK = 125ºC 5.9 IOUT = 40A 7.2 LO = 300nH 1.25 V DD = 5.0V 1.25 FSW = 1MHz 1.30 T BLK = 125ºC 80 70 60 50 40 30 250 375 500 625 750 875 1000 1125 1250 1375 Switching Frequency (kHz) 10 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 Switching Frequency (kHz) Figure 7 Normalized Power Loss vs. Switching Frequency Page 5 of 15 20 www.irf.com Figure 8 VDD supply current vs. Frequency 12/22/2007 1500 Data Sheet No. PD60322 iP2004 90% PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT Average VDD Current A Average VDD Voltage V DC Average Input Current ENABLE 10% A NC VSWS1 VSWS2 VIN Average Output Current VSW A VDD DC PWM Average Input Voltage V 90% PWM VSW PGND PGND iP2004 Averaging Circuit V 10% Average Output Voltage tPDH tPDL Figure 10 Timing Diagram Figure 9 Power Loss Test Circuit Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case. Please refer to International Rectifier Application Note AN1047 for further details on using this SOA curve in your thermal environment. Procedure 1. Calculate (based on estimated Power Loss) or measure the Case temperature on the device and the Board temperature near the device (1mm from the edge). 2. Draw a line from Case Temperature axis to the PCB Temperature axis. 3. Draw a vertical line from the TX axis intercept to the SOA curve. 4. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 44 40 36 Safe Operating Area Output Current (A) 32 28 24 20 Tx 16 12 VI = 12V VD = 5.0V VO = 1.3V Fsw = 1MHz LO = 300nH 8 4 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) Figure 11 SOA Example, Continuous current ≈ 30A for TPCB = 95ºC & TCASE = 110ºC Page 6 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Calculating Power Loss and SOA for Different Operating Conditions To calculate Power Loss for a given set of operation conditions, the following procedure should be followed: Power Loss Procedure 1. Determine the maximum current for each iP2004 and obtain the maximum power loss from Figure 1 2. Use the Normalized curves in page 5 to obtain power loss values that match the operating conditions in the Application 3. The maximum power loss under the Application conditions is then the product of the power loss from Figure 1 and the normalized values. To calculate the Safe Operating Area (SOA) for a given set of operating conditions, the following procedure should be followed: SOA Procedure 1. Determine the maximum PCB and CASE temperature at the maximum operating current for each iP2004 2. Use the Normalized curves in page 5 to obtain SOA temperature adjustments that match the operating conditions in the Application 3. Then, add the sum of the SOA temperature adjustments to the TX axis intercept in Figure 2 Design Example Operating Conditions: Output Current = 30A Switching Freq = 750kHz Input Voltage = 10V Inductor = 0.2µH Output Voltage = 3.3V Drive Voltage (VDD) = 5.5V Calculating Maximum Power Loss: (Figure 1) (Figure 3) (Figure 4) (Figure 5) (Figure 6) (Figure 7) Maximum power loss = 8.0W Normalized power loss for input voltage ≈ 0.98 Normalized power loss for output voltage ≈ 1.23 Normalized power loss for drive voltage (VDD) ≈ 0.96 Normalized power loss for output inductor ≈ 1.03 Normalized power loss for switch frequency ≈ 0.91 Calculated Maximum Power Loss ≈ 8.0W x 0.98 x 1.23 x 0.96 x 1.03 x 0.91 ≈ 8.68W Page 7 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Calculating SOA Temperature: SOA temperature adjustment for input voltage ≈ -0.5ºC SOA temperature adjustment for output voltage ≈ 5.5ºC SOA temperature adjustment for drive voltage (VDD) ≈ -0.8 ºC SOA temperature adjustment for output inductor ≈ 0.6 ºC SOA temperature adjustment for switch frequency ≈ -1.9 ºC (Figure 3) (Figure 4) (Figure 5) (Figure 6) (Figure 7) TX axis intercept adjustment ≈ -0.5 ºC + 5.5 ºC - 0.8 ºC + 0.6 ºC - 1.9 ºC ≈ 2.9 ºC Assuming TPCB = 95ºC & TCASE = 110ºC The following example shows how the SOA current is adjusted for TX increase of 2.9ºC Case Temperature (ºC) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 44 40 36 Safe Operating Area Output Current (A) 32 28 24 20 Tx 16 12 VI = 12V VD = 5.0V VO = 1.3V Fsw = 1MHz LO = 300nH 8 4 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) 1. Draw a line from Case Temperature axis to the PCB Temperature axis. 2. Draw a vertical line from the TX axis intercept to the SOA curve. 3. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. 4. Draw a new vertical line from the TX axis by adding or subtracting the SOA adjustment temperature from the original TX intercept point. 5. Draw a horizontal line from the intersection of the new vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the new SOA continuous current. The SOA adjustment indicates the part is still allowed to run at a continuous current of 30A. Page 8 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Internal Block Diagram VSWS1 VSWS2 8 NC ENABLE PWM VDD PGND 9 1 7 2 MOSFET Driver with dead time control 3 4 5 6 10 VIN VSW PGND Figure 12 Internal Block Diagram Pin Description Pin Number Pin Name 1 NC 2 ENABLE When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the Control and Synchronous FETs are turned off. 3 PWM TTL level input to MOSFET drivers. When PWM is HIGH, the Control FET is on and the Sync FET is off. When PWM is LOW, the Sync FET is on and the Control FET is off. 4 VDD Supply voltage to internal circuitry. 5 VSW Voltage Switching Node – pin connection to the output inductor. 6, 10 PGND 7 VIN 8 VSWS1 Floating pin. Externally connect to VSWS2 only. 9 VSWS2 Floating pin. Externally short to VSWS1 only. Page 9 of 15 Description No Connect. This pin is not for electrical connection Power Ground Input voltage pin. Connect input capacitors close to this pin. www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Package Pinout Diagram NC 1 VSWS1 8 VIN 7 VSWS2 9 ENABLE 2 PWM 3 PGND 6 PGND 10 VSW 5 VDD 4 Figure 13 Top Side Transparent View Page 10 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Recommended PCB Layout Figure 14 Top copper and Solder-mask layer of PCB layout Page 11 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Figure 15 Top & Bottom Component and Via Placement (Topside, Transparent view down) PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance. • All pads on the iP2004 footprint design need to be Solder-mask defined (see Figure 14). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance. • Place as many vias around the Power pads (VIN, VSW, and PGND) for both electrical and optimal thermal performance. o Vias in between the different power pads may overlap the pad opening and solder mask edge without the need to plug the via hole. Vias with a 13mil drill hole and 25mil capture pad were used in this example. • A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2004 are needed for greater than 25A operation. This will result in the lowest loss due to input capacitor ESR. • Placement of the ceramic input capacitors is critical to optimize switching performance. In cases where there is a heatsink on the case of iP2004, place all six ceramic capacitors right underneath the iP2004 footprint (see Bottom Component Layer). In cases where there is not heatsink, C1 and C6 on the bottom layer may be moved to the C1x and C6x locations (respectively) on the top component layer (see Top Component Layer). In both cases, C2 – C5 need to be placed right underneath the iP2004 PCB footprint. • Dedicate at least two layer to for PGND only • Duplicate the Power Nodes on multiple layers (refer to AN1029). Page 12 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Mechanical Outline Drawing 0.15 [.006] C 7.65 [0.301] A B NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 3. CONTROLLING DIMENSION: MILLIMETER CORNER ID 4 7.65 [0.301] PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SOLDER RESIST OPENING 5. DRAWING NOT TO SCALE. 0.15 [.006] C TOP VIEW 0.07 [.0027] C 7.319 6.303 5.795 0.334 CORNER ID 4.779 2.379 5.821 4 C 2.21 [.087] 4.132 0.322 1.858 2.010 3.459 3.865 5.021 5.300 6.583 7.345 2.54 6X 0.762 7X 1.016 SIDE VIEW BOTTOM VIEW 7 VIN 8 VSWS1 1 NC 9 VSWS2 6 2 ENABLE PGND 10 PGND 5 VSW 3 PWM 4 VDD BOTTOM VIEW ELECTRICAL I/O Figure 16 Mechanical Outline Drawing Page 13 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Recommended Solder Paste Stencil Design Figure 17 Solder Paste Stencil Design Tape and Reel Information Figure 18 Tape & Reel Information Page 14 of 15 www.irf.com 12/22/2007 Data Sheet No. PD60322 iP2004 Part Marking Figure 19 Part Marking Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Page 15 of 15 www.irf.com 12/22/2007