4M × 36-Bit EDO-DRAM Module HYM 364035S/GS-60 Advanced Information • 4 194 304 words by 36-Bit organization • Fast access and cycle time 60 ns RAS access time 15 ns CAS access time 104 ns cycle time • Hyper page mode (EDO) capability 25 ns cycle time • Single + 5 V (± 10 %) supply • Low power dissipation max. 7260 mW active CMOS – 66 mW standby TTL – 132 mW standby • CAS-before-RAS refresh RAS-only-refresh Hidden-refresh • 12 decoupling capacitors mounted on substrate • All inputs, outputs and clocks fully TTL compatible • 72 pin Single in-Line Memory Module (L-SIM-72) with 22.9 mm (900 mil) height • Utilizes 12 4M x 3 DRAM’s in 300 mil SOJ packages • 2048 refresh cycles / 32 ms • Optimized for use in byte-write parity applications • Tin-Lead contact pads (HYM 364035S-60) • Gold contact pads (HYM 364035GS-60) Semiconductor Group 1 4.96 HYM 364035S/GS-60 4M × 36-Bit EDO-Module The HYM 364035S/GS-60 is a 16 MByte EDO-DRAM module organized as 4 194 304 words by 36Bit in a 72-pin single-in-line package comprising twelve HYB 5117305BJ 4M × 3 DRAMs in 300 mil wide SOJ-packages mounted together with twelve 0.2 µF ceramic decoupling capacitors on a PC board. The HYB 5117305BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 364035S-60 dictates the use of early write cycles. Ordering Information Type Ordering Code Package Description HYM 364035S-60 Q67100-Q3016 L-SIM-72-13 DRAM Module (access time 60 ns) HYM 364035GS-60 Q67100-Q3017 L-SIM-72-13 DRAM Module (access time 60 ns) Semiconductor Group 2 HYM 364035S/GS-60 4M × 36-Bit EDO-Module Pin Configuration (top view) Pin Names A0-A10 Address Inputs for HYM 364035S/GS DQ0-DQ35 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0, RAS2 Row Address Strobe WE Read/Write Input VCC Power (+ 5 V) VSS Ground PD Presence Detect Pin N.C. No Connection Presence Detect Pins -60 Semiconductor Group 3 PD0 VSS PD1 N.C. PD2 N.C. PD3 N.C. HYM 364035S/GS-60 4M × 36-Bit EDO-Module Block Diagram Semiconductor Group 4 HYM 364035S/GS-60 4M × 36-Bit EDO-Module Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 ˚C Storage temperature range......................................................................................... – 55 to 125 ˚C Input/output voltage ........................................................................ – 0.5 V to min (VCC + 0.5, 7.0) V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................... 9.24 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C, VCC = 5 V ± 10 % Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 VCC + 0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) – 80 80 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) – 10 10 µA 1) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -60 ns version ICC1 – 1320 mA 2),3),4) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 24 mA Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 ns version ICC3 – 1320 mA Semiconductor Group 5 2),4) HYM 364035S/GS-60 4M × 36-Bit EDO-Module DC Characteristics1) (cont’d) Parameter Symbol Average VCC supply current during hyper page mode (EDO) (RAS = VIL, CAS, address cycling, tPC = tPC min) -60 ns version ICC4 Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 ns version ICC6 Limit Values Unit Test Condition min. max. – 660 mA 2),3),4) – 12 mA 1) – 1320 mA 2),4) Capacitance TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A10) CI1 – 90 pF Input capacitance (RAS0, RAS2) CI2 – 45 pF Input capacitance (CAS0 - CAS3) CI3 – 40 pF Input capacitance (WE) CI4 – 90 pF I/O capacitance(DQ0-DQ35) CIO1 – 20 pF Semiconductor Group 6 HYM 364035S/GS-60 4M × 36-Bit EDO-Module AC Characteristics 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Unit Note -60 min. max. Common Parameters Random read or write cycle time tRC 104 – ns RAS precharge time tRP 40 – ns RAS pulse width tRAS 60 10k ns CAS pulse width tCAS 10 10k ns Row address setup time tASR 0 – ns Row address hold time tRAH 10 – ns Column address setup time tASC 0 – ns Column address hold time tCAH 10 – ns RAS to CAS delay time tRCD 14 45 ns RAS to column address delay time tRAD 12 30 ns RAS hold time tRSH 15 – ns CAS hold time tCSH 60 – ns CAS to RAS precharge time tCRP 5 – ns Transition time (rise and fall) tT 1 50 ns Refresh period tREF – 32 ms Access time from RAS tRAC – 60 ns 8, 9 Access time from CAS tCAC – 15 ns 8, 9 Access time from column address tAA – 30 ns 8,10 Column address to RAS lead time tRAL 30 – ns Read command setup time tRCS 0 – ns Read command hold time tRCH 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – ns 11 CAS to output in low-Z tCLZ 0 – ns 8 Output buffer turn-off delay tOFF 0 15 ns 12 7 Read Cycle Semiconductor Group 7 HYM 364035S/GS-60 4M × 36-Bit EDO-Module AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Unit Note -60 min. max. Early Write Cycle Write command hold time tWCH 10 – ns Write command pulse width tWP 10 – ns Write command setup time tWCS 0 – ns Write command to RAS lead time tRWL 15 – ns Write command to CAS lead time tCWL 15 – ns Data setup time tDS 0 – ns 14 Data hold time tDH 10 – ns 14 Hyper page mode (EDO) cycle time tHPC 25 – ns CAS precharge time tCP 10 – ns Access time from CAS precharge tCPA – 32 ns Output data hold time tCOH 5 – ns RAS pulse width in hyper page mode tRAS 60 200k ns CAS precharge to RAS Delay tRHCP 32 – ns CAS setup time tCSR 10 – ns CAS hold time tCHR 10 – ns RAS to CAS precharge time tRPC 5 – ns Write to RAS precharge time tWRP 10 – ns Write hold time referenced to RAS tWRH 10 – ns 13 Hyper Page Mode (EDO) Cycle CAS before RAS Refresh Cycle Semiconductor Group 8 7 HYM 364035S/GS-60 4M × 36-Bit EDO-Module Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA. tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge. Semiconductor Group 9 HYM 364035S/GS-60 4M × 36-Bit EDO-Module Package Outline L-SIM-72-13 (Single In-line Module) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 10 Dimensions in mm