2M × 72-Bit EDO-DRAM Module (ECC - Module) HYM 72V2005GS-50/-60 168 pin buffered DIMM Module • 168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module for PC main memory applications • 1 bank 2 M x 72 organisation • Optimized for ECC applications • Extended Data Out (EDO) • Performance: -50 -60 tRAC RAS access time 50 60 ns tCAC CAS access time 18 20 ns tAA Access time from address 30 35 ns tRC Read/Write cycle time 84 104 ns tHPC Fast page mode cycle time 20 25 ns • Single + 3.3V ± 0.3 V supply • CAS-before-RAS refresh, RAS-only refresh • Decoupling capacitors mounted on substrate • All inputs, outputs and clock fully LVTTL & LVCMOS compatible • 4 Byte interleave enabled, Dual Address inputs (A0/B0) • Buffered inputs excepts RAS and DQ • Parallel Presence Detects • Utilizes nine 2M × 8 -DRAMs and BiCMOS buffers/line drivers • 2048 refresh cycles / 32 ms with 11 / 10 addressing • Gold contact pad • Double sided module with 25.35 mm (1000 mil) height Semiconductor Group 1 11.96 HYM72V2005GS-50/-60 2M x 72-ECC Module The HYM 72V2005GS-50/-60 is a 16 MByte DRAM module organized as 2 097 152 words by 72bit in a 168-pin, dual read-out, single-in-line package comprising nine HYB3117805BSJ 2M × 8 EDO DRAMs in 400 mil wide SOJ-28 - packages mounted together with ceramic decoupling capacitors on a PC board. All inputs except RAS and DQ are buffered by using BiCMOS buffers/ line drivers. Each HYB3117805BSJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The density and speed of the module can be detected by the use of presence detect pins. Ordering Information Type Ordering Code Package Descriptions HYM 72V2005GS-50 L-DIM-168-22 DRAM module (access time 50 ns) HYM 72V2005GS-60 L-DIM-168-22 DRAM module (access time 60 ns) Pin Names A0-A11,B0 A0-A10,B0 DQ0 - DQ71 RAS0, RAS2 CAS0 , CAS2 WE0, WE2 OE0, OE2 Vcc Vss PD1 - PD8 PDE ID0 , ID1 N.C. Row Address Inputs Column Address Inputs Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+3.3 Volt) Ground Presence Detect Pins Presence Detect Enable ID indentification bit No Connection Presence-Detect and ID-pin Truth Table: Module ID0 ID1 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 HYM 72V2005GS-50 Vss Vss 1 0 0 1 1 0 0 0 HYM 72V2005GS-60 Vss Vss 1 0 0 1 1 1 1 0 Note: 1 = High Level ( Driver Output) , 0 = Low Level (Driver Output) for PDE active ( ground) . For PDE at a high level all PD terminal are in tri-state. Semiconductor Group 2 HYM72V2005GS-50/-60 2M x 72-ECC Module Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CAS0 NC RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 NC VCC NC NC Semiconductor Group PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS OE2 RAS2 CAS4 NC WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 3 Symbol VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC NC NC NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC B0 PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS NC NC NC NC PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC HYM72V2005GS-50/-60 2M x 72-ECC Module RAS0 CAS0 RAS2 CAS4 WE0 OE0 WE2 OE2 DQ0-DQ7 DQ40-DQ47 I/O1-I/O8 I/O1-I/O8 D0 DQ8-DQ15 D5 I/O1-I/O8 DQ48-DQ55 I/O1-I/O8 D1 DQ16-DQ23 D6 I/O1-I/O8 DQ56-DQ63 I/O1-I/O8 D2 DQ24-DQ31 D7 I/O1-I/O8 DQ64-DQ71 I/O1-I/O8 D3 DQ32-DQ39 D8 I/O1-I/O8 D4 A0 D0 - D4 Vcc B0 D5 - D8 Vss A1-A10 D0 - D8 PDE Vcc or Vss Block Diagram Semiconductor Group 4 D0-D8, buffers PD1-PD8 HYM72V2005GS-50/-60 2M x 72-ECC Module Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 °C Storage temperature range...................................................................................... – 55 to + 125 °C Input/output voltage ............................................................................... -0.5 to min (Vcc+0.5, 4.6) V Power supply voltage................................................................................................. – 0.5V to 4.6 V Power dissipation.................................................................................................................... 5,8 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Test Condition Input high voltage VIH 2.0 Vcc + 0.3 V 1) Input low voltage VIL VOH – 0.3 0.8 V 1) 2.4 – V 1) Output low voltage (LVTTL) Output „L“ level voltage ( IOUT = + 2 mA) VOL – 0.4 V 1) Output high voltage (LVCMOS) Output „H“level voltage ( IOUT = – 100 µA) VOH Vcc-0.2 – V 1) Output low voltage (LVCMOS) Output „L“ level voltage ( IOUT = + 100 µA) VOL – 0.2 V 1) Input leakage current (0 V < VIN < Vcc, all other pins = 0 V) II(L) – 20 20 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < Vcc) IO(L) – 20 20 µA 1) Average VCC supply current: ICC1 – – 1080 990 mA mA 2) 3) 4) – 50 mA – Output high voltage (LVTTL) Output „H“level voltage ( IOUT = – 2 mA) -50 version -60 version (RAS, CAS, address cycling, tRC = tRC min.) Standby VCC supply current (RAS = CAS = 2.4V, one address change within 15,6 µs trc ) Semiconductor Group ICC2 5 HYM72V2005GS-50/-60 2M x 72-ECC Module Parameter Symbol Limit Values min. Average VCC supply current during RAS ICC3 only refresh cycles: -50 version -60 version Unit max. Test Condition 2) 4) – – 1080 990 mA mA – – – 630 495 mA mA 2) 3) 4) ICC5 – 30 mA – ICC6 Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version – – 1080 990 mA mA 2) 4) (RAS cycling, CAS = VIH , t RC = tRC min.) Average VCC supply current during hyper ICC4 page mode (EDO): -50 version -60 version (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V, one address change within 15,6 µs trc) (RAS, CAS cycling, tRC = tRC min.) Capacitance TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11,B0) CI1 – 10 pF Input capacitance (RAS0, RAS2) CI2 – 50 pF Input capacitance (CAS0, CAS4) CI3 – 15 pF Input capacitance (WE0,WE2,OE0,OE2) CI4 – 15 pF I/O capacitance (DQ0-DQ71) CIO1 – 15 pF Semiconductor Group 6 HYM72V2005GS-50/-60 2M x 72-ECC Module AC Characteristics (note: 5,6,7,8) TA = 0 to 70 °C,VCC = 3.3 ± 0.3 V Parameter Symbol -50 min. -60 max. min. Unit Note max. common parameters Random read or write cycle time tRC 84 – 104 – ns RAS precharge time tRP 30 – 40 – ns RAS pulse width tRAS 50 100k 60 100k ns CAS pulse width tCAS 8 10k 10 10k ns Row address setup time tASR 5 – 5 – ns 9 Row address hold time tRAH 6 – 8 – ns 10 Column address setup time tASC 2 – 2 – ns 11 Column address hold time tCAH 13 – 15 – ns 9 RAS to CAS delay time tRCD 10 32 12 40 RAS to column address delay time tRAD 8 20 10 25 ns 12 RAS hold time tRSH 18 – 20 – ns 9 CAS hold time tCSH 38 – 48 – ns 10 CAS to RAS precharge time tCRP 10 – 10 – ns 9 Transition time (rise and fall) tT 1 30 1 30 ns 7 Refresh period tREF – 64 – 64 ms Access time from RAS tRAC – 50 – 60 ns 13,14 Access time from CAS tCAC – 18 – 20 ns 9,13,14 Access time from column address tAA – 30 – 35 ns 9,13, 15 OE access time tOEA – 18 – 20 ns 9,13 Column address to RAS lead time tRAL 30 – 35 – ns 9 Read command setup time tRCS 2 – 2 – ns 11 Read command hold time tRCH 2 – 2 – ns 11,16 Read command hold time referenced to RAS tRRH 0 – 0 – ns 16 tCLZ 2 – 2 – ns 11,13 tOFF – 18 – 20 ns 9,17 12 Read Cycle CAS to output in low-Z Output buffer turn-off delay Semiconductor Group 7 HYM72V2005GS-50/-60 2M x 72-ECC Module AC Characteristics (cont’d) (note: 5,6,7,8) TA = 0 to 70 °C,VCC = 3.3 ± 0.3 V Parameter Symbol -50 min. -60 max. min. Unit Note max. Output buffer turn-off delay from OE tOEZ – 18 – 20 ns 9,17 CAS delay time from Din tDZC 0 – 0 – ns 18 Data to OE low delay tDZO 0 – 0 – ns 18 CAS high to data delay tCDD 15 – 18 – ns 9,19 OE high to data delay tODD 15 – 18 – ns 9,19 Write command hold time tWCH 13 – 15 – ns 9 Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 2 – 2 – ns 11,20 Write command to RAS lead time tRWL 18 – 20 – ns 9 Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS -2 – -2 – ns 10,21 Data hold time tDH 13 – 15 – ns 9,21 Read-write cycle time tRWC 118 – 143 – ns 9 RAS to WE delay time tRWD 66 – 77 – ns 11,21 CAS to WE delay time tCWD 29 – 34 – ns 11,21 Column address to WE delay time tAWD 41 – 49 – ns 11,21 OE command hold time tOEH 8 – 11 – ns 10 Hyper page mode cycle time tPC 20 – 25 – ns CAS precharge time tCP 8 – 10 – ns Access time from CAS precharge tCPA – 32 – 37 ns 9,13 Output data hold time tCOH 3 – 3 – ns 10 RAS pulse width tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHCP 32 – 37 – ns OE setup time prior to CAS tOES 5 – 5 – ns Write Cycle Read-Modify-Write Cycle Hyper Page Mode (EDO) Cycle Semiconductor Group 8 9 HYM72V2005GS-50/-60 2M x 72-ECC Module AC Characteristics (cont’d) (note: 5,6,7,8) TA = 0 to 70 °C,VCC = 3.3 ± 0.3 V Parameter Symbol -50 min. -60 max. min. Unit Note max. Hyper Page Mode Read-Modify-Write Cycle Hyper page mode read-write cycle time tPRWC 60 – 70 – ns 11 CAS precharge to WE tCPWD 43 – 51 – ns 11,21 CAS setup time tCSR 12 – 12 – ns 11 CAS hold time tCHR 8 – 8 – ns 10 RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 12 – 12 – ns 11 Write hold time referenced to RAS tWRH 8 – 8 – ns 10 PDE to valid presence detect data tPD – 10 – 10 ns PDE inactive to presence detects inactive tPDOFF 0 10 0 10 ns CAS-before-RAS Refresh Cycle Presence Detect Read Cycle Semiconductor Group 9 HYM72V2005GS-50/-60 2M x 72-ECC Module Notes: 1) 2) 3) 4) All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle ( thpc). 5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (CAS, WE, OE, addresses) maximum delay, no pulse shrinkage to the DRAM device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specification of 50ns and 60ns. 9) A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers. 10) A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 11) A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 12) A -2ns (min.) and a -5ns (max.) timing skew from the DRAM to the module resulted from the addition of line drivers. 13) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA, tOEA. tCAC is measured from tristate. 14) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 15) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 16) Either tRCH or tRRH must be satisfied for a read cycle. 17) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 18) Either tDZC or tDZO must be satisfied. 19) Either tCDD or tODD must be satisfied. 20) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 21) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in ReadModify-Write cycles. Semiconductor Group 10 HYM72V2005GS-50/-60 2M x 72-ECC Module L-DIM-168-22 Module package (dual read-out, single in-line memory module) 133,35 127,35 3,0 1 10 11 40 84 41 25,40 17,78 9,0 43,18 66,68 A 124 94 95 125 168 6,35 3,125 3,125 6,35 C 2,0 Detail A 1,27 1,0 +- 0.5 2,54 min. 85 B 2,0 0,2 +- 0,15 Detail C Detail B DM168-22.WMF preliminary drawing Semiconductor Group 11