INFINEON HYB3117805BSJ-60

2M × 8-Bit Dynamic RAM
2k Refresh
(Hyper Page Mode-EDO)
HYB 5117805/BSJ-50/-60
HYB 3117805/BSJ-50/-60
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode-EDO-operation
• Performance:
-50
-60
tRAC
RAS access time
50
60
ns
tCAC
CAS access time
13
15
ns
tAA
Access time from address
25
30
ns
tRC
Read/Write cycle time
84
104
ns
tHPC
Hyper page mode (EDO) cycle time
20
25
ns
• Power dissipation:
Power Supply
Active
HYB 5117805
HYB 3117805
-50
-50
-60
5 ± 10%
440
-60
3.3 ± 0.3 V
385
288
252
mW
TTL Standby
11
7.2
mW
CMOS Standby
5.5
3.6
mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• 2048 refresh cycles / 32 ms (2k-refresh)
• Plastic Package: P-SOJ-28-3 400 mil
Semiconductor Group
1
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
The HYB 5(3)117805 are 16 MBit dynamic RAMs based on the die revisions “G” & “F” and
organized as 2 097 152 words by 8-bits. The HYB 5(3)117805 utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117805BJ
to be packaged in a standard SOJ-28 plastic packages. Package with 400 mil width are available.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYB 5117805BSJ-50
Q67100-Q1104
P-SOJ-28-3 400 mil
5V
50 ns EDO-DRAM
HYB 5117805BSJ-60
Q67100-Q1105
P-SOJ-28-3 400 mil
5V
60 ns EDO-DRAM
HYB 3117805BSJ-50
on request
P-SOJ-28-3 400 mil
3.3 V 50 ns EDO-DRAM
HYB 3117805BSJ-60
on request
P-SOJ-28-3 400 mil
3.3 V 60 ns EDO-DRAM
Pin Names and Configuration
A0 - A10
Row Address Inputs
A0 - A9
Column Address Inputs
RAS
Row Address Strobe
OE
Output Enable
I/O1 - I/O8
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
VCC
Power Supply
+ 5 V for HYB 5117800
+ 3.3 V for HYB 3117805
VSS
Ground (0 V)
N.C.
Not Connected
P-SOJ-28 400 mil
V CC
I/O1
I/O2
I/O3
I/O4
WE
RAS
N.C.
A10
A0
A1
A2
A3
V CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 V SS
27 I/O8
26 I/O7
25 I/O6
24 I/O5
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15 V SS
SPP02803
Semiconductor Group
2
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
I/O1 I/O2
Data IN
Buffer
I/O8
Data OUT
Buffer
OE
&
WE
8
CAS
8
No.2 Clock
Generator
Column
Address
Buffers (10)
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (11)
4
1024
x8
11
11
RAS
Row
Address
Buffers (11)
11
Row
Decoder
2048
Memory Array
2048 x 1024 x 8
No.1 Clock
Generator
Voltage Down
Generator
VCC
VCC
(internal)
SPB03456
Block Diagram
Semiconductor Group
3
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 °C
Storage temperature range....................................................................................... – 55 to 150 °C
Input/output voltage (5 V versions) .................................................... – 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions) ................................................. – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................. 1.0 W
Power dissipation (3.3 V versions) .......................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
V
5 V Versions
Power supply voltage
VCC
4.5
5.5
Input high voltage
VIH
2.4
VCC + 0.5 V
1
Input low voltage
VIL
– 0.5
0.8
V
1
Output high voltage (IOUT = – 5 mA)
VOH
2.4
–
V
1
Output low voltage (IOUT = 4.2 mA)
VOL
–
0.4
V
1
Power supply voltage
VCC
3.0
3.6
V
Input high voltage
VIH
2.0
VCC + 0.5 V
1
Input low voltage
VIL
– 0.5
0.8
V
1
TTL Output high voltage (IOUT = – 2 mA)
VOH
2.4
–
V
1
TTL Output low voltage (IOUT = 2 mA)
VOL
–
0.4
V
1
CMOS Output high voltage (IOUT = – 100 µA)
VOH
VCC – 0.2 –
V
CMOS Output low voltage (IOUT = 100 µA)
VOL
–
0.2
V
Input leakage current
(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)
II(L)
– 10
10
µA
1
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)
IO(L)
– 10
10
µA
1
Semiconductor Group
4
3.3 V Versions
Common Parameters
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
min.
max.
Unit Test
Condition
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC MIN.)
–
–
80
70
mA
mA
2, 3, )4
Standby VCC supply current (RAS = CAS = VIH) ICC2
–
2
mA
–
Average VCC supply current, during RAS-only ICC3
refresh cycles
-50 ns version
-60 ns version
(RAS cycling, CAS = VIH, tRC = tRC MIN.)
–
–
80
70
mA
mA
2, 4
Average VCC supply current, during hyper page ICC4
mode (EDO)
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC = tPC MIN.)
–
–
35
30
mA
mA
2, 3, 4
ICC5
–
1
mA
1
Average VCC supply current, during CASICC6
before-RAS refresh mode
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC MIN.)
–
–
80
70
mA
mA
2, 4
Average VCC supply current
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
Symbol
Limit Values
ICC1
2, 3, 4
2, 4
2, 3, 4
2, 4
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A10)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
I/O capacitance (I/O1 - I/O8)
CIO
–
7
pF
Semiconductor Group
5
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
AC Characteristics 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
tRC
84
–
104
–
ns
RAS precharge time
tRP
30
–
40
–
ns
RAS pulse width
tRAS
50
10k
60
10k
ns
CAS pulse width
tCAS
8
10k
10
10k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
8
–
10
–
ns
RAS to CAS delay time
tRCD
12
37
14
45
ns
RAS to column address delay
tRAD
10
25
12
30
ns
RAS hold time
tRSH
13
–
15
–
ns
CAS hold time
tCSH
40
–
50
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
Refresh period
tREF
–
32
–
32
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
25
–
30
ns
8, 10
OE access time
tOEA
–
13
–
15
ns
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to RAS tRRH
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
ns
12
Output turn-off delay from OE
tOEZ
0
13
0
15
ns
12
7
Read Cycle
Semiconductor Group
6
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
10
–
13
–
ns
14
OE high to data delay
tODD
10
–
13
–
ns
14
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
8
–
10
–
ns
Write command to CAS lead time
tCWL
8
–
10
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
8
–
10
–
ns
16
Read-write cycle time
tRWC
113
–
138
–
ns
RAS to WE delay time
tRWD
64
–
77
–
ns
15
CAS to WE delay time
tCWD
27
–
32
–
ns
15
Column address to WE delay time
tAWD
39
–
47
–
ns
15
OE command hold time
tOEH
10
–
13
–
ns
Hyper page mode (EDO) cycle time
tHPC
20
–
25
–
ns
CAS precharge time
tCP
8
–
10
–
ns
Access time from CAS precharge
tCPA
–
27
–
32
ns
Output data hold time
tCOH
5
–
5
–
ns
RAS pulse width in EDO mode
tRAS
50
200k 60
200k ns
CAS precharge to RAS delay
tRHCP
27
–
32
–
ns
OE setup time prior to CAS
tOES
5
–
5
–
5
Write Cycle
15
Read-Modify-Write Cycle
Hyper Page Mode (EDO) Cycle
Semiconductor Group
7
7
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode (EDO) read-write cycle
time
tPRWC
58
–
68
–
ns
CAS precharge to WE
tCPWD
41
–
49
–
ns
CAS setup time
tCSR
10
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
tCPT
35
–
40
–
ns
Write command setup time
tWTS
10
–
10
–
ns
Write command hold time
tWTH
10
–
10
–
ns
CAS hold time
tCHRT
30
–
30
–
ns
RAS hold time in test mode
tRAHT
30
–
30
–
ns
CAS-before-RAS Refresh Cycle
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
Test Mode
Semiconductor Group
8
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
Notes
All voltages are referenced to VSS.
ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required.
6. AC measurements assume tT = 2 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access
time is determined by the latter of tRAC, tCAC, tAA, tCPA, tOEA. tCAC is measured from tristate.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
1.
2.
3.
4.
Semiconductor Group
9
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAD
t ASR
t RAL
t CAH
t ASC
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t RCH
t RRH
t RCS
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t DZO
I/O
(Inputs)
t ODD
VIH
VIL
t OFF
t CAC
t CLZ
VOH
Hi Z
I/O
(Outputs) V
OL
t OEZ
Valid Data OUT
Hi Z
t RAC
"H" or "L"
SPT03025
Read Cycle
Semiconductor Group
10
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAL
t RAD
t ASR
t ASC
t CAH
t ASR
VIH
Address
Row
VIL
Column
t RAH
t CWL
t WCS
VIH
Row
t WP
WE
VIL
t WCH
t RWL
VIH
OE
VIL
t DS
I/O
(Inputs)
t DH
VIH
Valid Data IN
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03026
Write Cycle (Early Write)
Semiconductor Group
11
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CAS
VIH
t CRP
CAS
VIL
t RAD
t RAL
t CAH
t ASC
t ASR
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t CWL
t RWL
t WP
VIH
WE
VIL
t OEH
VIH
OE
VIL
t ODD
t DZO
t DZC
I/O
(Inputs)
t DH
t DS
VIH
Valid Data
VIL
t CLZ
t OEZ
t OEA
VOH
I/O
(Outputs) V
OL
Hi Z
Hi Z
"H" or "L"
SPT03027
Write Cycle (OE Controlled Write)
Semiconductor Group
12
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RWC
t RAS
VIH
RAS
VIL
t CSH
t RP
t RSH
t CAS
t RCD
t CRP
VIH
CAS
VIL
t RAH
t ASR
t CAH
t ASC
t ASR
VIH
Address
Row
Column
Row
VIL
t RAD
t CWL
t AWD
t CWD
t RWL
t WP
t RWD
VIH
WE
VIL
t AA
t RCS
t OEA
t OEH
VIH
OE
VIL
t DZC
t DS
t DZO
I/O
(Inputs)
t DH
VIH
Valid
Data IN
VIL
t ODD
t CAC
t OEZ
t CLZ
VOH
I/O
(Outputs) V
OL
Data
OUT
t RAC
"H" or "L"
SPT03028
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
13
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RAS
t RCD
t RHCP
VIH
RAS
VIL
t HPC
t RP
t RSH
t CP
t CRP
t CAS
t CAS
t CAS
t CRP
VIH
CAS
VIL
t CSH
t RAH
t ASR
t RAL
t CAH
t ASC
t CAH
t CAH
t ASC
Column 2
Column N
t ASC
VIH
Address
Row
Column 1
VIL
t RAD
t RRH
t RCS
t RCH
VIH
WE
VIL
t CAC
t AA
t OES
t OEA
t CPA
t CAC
t AA
t CPA
t OFF
VIH
OE
VIL
t RAC
t AA
t CAC
t CLZ
VOH
I/O
(Output) V
OL
t COH
Data OUT 1
t COH
Data OUT 2
t OEZ
Data OUT N
"H" or "L"
SPT03038
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
14
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RAS
t RCD
t RHCP
VIH
RAS
VIL
t HPC
t RP
t CP
t CRP
t CAS
t RSH
t CAS
t CAS
t CRP
VIH
CAS
VIL
t CSH
t RAH
t ASR
VIH
Address
VIL
t ASC
Row
Address
t CAH
t ASC
Column 1
t CAH
t RAL
t CAH
t ASC
Column 2
Column N
t RAD
t CWL
t WCS
t CWL
t WCS
t WCS
t WCH
t WCH
t WP
t RWL
t CWL
t WCH
t WP
t WP
VIH
WE
VIL
VIH
OE
VIL
t DH
t DS
I/O
(Input)
t DH
t DS
t DH
t DS
VIH
Data IN 1
Data IN 2
Data IN N
VIL
"H" or "L"
SPT03039
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
15
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RAS
VIH
RAS
VIL
t CSH
t RP
t CP
t RCD
t PRWC
t CAS
t RSH
t CAS
t CAS
t CRP
VIH
CAS
VIL
t ASR
t RAD
t RAH
t ASC
t RAL
t CAH
t CAH
t CAH
t ASC
t ASC
t ASR
VIH
Address
Row
Column
Column
Column
Row
VIL
t RWD
t CWD
t RCS
t CPWD
t CWD
t CWL
t CPWD
t CWD
t CWL
t RWL
t CWL
VIH
WE
VIL
t AWD
t AA
t AWD
t WP
t OEA
t AWD
t WP
t OEA
t WP
t OEA
t OEH
t OEH
t OEH
VIH
OE
VIL
t CLZ
t DZC
t CLZ
t ODD
t CLZ
t CPA
t ODD
t DZC
t DZO
VIH
I/O
(Inputs) V
IL
Data IN
t CAC
t RAC
VOH
I/O
(Outputs) V
t OEZ
t CPA
t ODD
Data IN
t DH
t DS
t DZC
Data IN
t DH
t AA
t DS
t OEZ
t DS
t AA
Data
OUT
Data
OUT
t DH
t CAC
t OEZ
Data
OUT
OL
"H" or "L"
SPT03031
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycle
Semiconductor Group
16
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CRP
t RPC
VIH
CAS
VIL
t RAH
t ASR
t ASR
VIH
Row
Address
Row
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03032
RAS-only Refresh Cycle
Semiconductor Group
17
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t CHR
t RPC
t CSR
t CRP
VIH
CAS
VIL
t WRH
t WRP
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
VIL
t CDD
t OEZ
VOH
Hi Z
I/O
(Outputs) V
OL
t OFF
"H" or "L"
SPT03033
CAS-before-RAS Refresh Cycle
Semiconductor Group
18
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RC
t RP
t RP
t RAS
t RAS
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t WRP
t RAH
t ASR
t WRH
t CAH
t ASR
VIH
Address
Row
VIL
Column
Row
t RCS
t RRH
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t DZO
I/O
(Inputs)
t ODD
VIH
VIL
t CLZ
t CAC
t OFF
t RAC
t OEZ
VOH
I/O
(Outputs) V
OL
Valid Data OUT
"H" or "L"
Hi Z
SPT03034
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
19
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RC
t RAS
t RP
t RAS
t RP
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t RAH
t ASR
t ASR
t CAH
VIH
Address
Row
VIL
Column
Row
t WCS
t WCH
t WP
t WRH
t WRP
VIH
WE
VIL
t DS
t DH
I/O
(Input)
VIN
Valid Data
VIL
VOH
I/O
(Output) V
OL
Hi Z
"H" or "L"
SPT03035
Hidden Refresh Early Write Cycle
Semiconductor Group
20
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
Read Cycle
t RAS
t RP
VIH
RAS
VIL
t CHR
t CSR
t RSH
t CP
VIH
t CAS
CAS
VIL
t RAL
t CAH
t ASR
t ASC
VIH
Address
Column
VIL
t WRP
Row
t AA
t RRH
VIH
WE
VIL
t WRH
t CAC
t RCS
t RCH
t OEA
VIH
OE
VIL
t CDD
t DZC
VIH
I/O
(Inputs) V
IL
t ODD
t OFF
t DZO
t CLZ
t OEZ
VOH
I/O
(Outputs) V
Write Cycle
Data OUT
t WCS
OL
t RWL
t CWL
t WRP
t WCH
VIH
WE
VIL
t WRH
t DH
VIH
OE
VIL
t DS
VIH
I/O
(Inputs) V
IL
Data IN
VOH
I/O
(Outputs) V
Hi Z
OL
"H" or "L"
SPT03036
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
21
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t RPC
t CHR
t CRP
t CSR
VIH
CAS
VIL
t RAH
t ASR
VIH
Row
Address
VIL
t WTH
t WTS
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
Hi Z
VIL
t CDD
t OEZ
VOH
Hi Z
I/O
(Outputs) V
OL
t OFF
"H" or "L"
SPT03042
Test Mode Entry
Semiconductor Group
22
1998-10-01
HYB 5(3)117805/BSJ-50/-60
2M × 8 EDO-DRAM
Package Outlines
GPJ05699
Plastic Package P-SOJ-28-3 (400mil) (SMD)
(Plastic small outline J-leaded)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
23
Dimensions in mm
1998-10-01