INFINEON Q67006

5-V Low Drop Voltage Regulator
TLE 4262
Bipolar IC
Features
●
●
●
●
●
●
●
●
●
Output voltage tolerance ≤ ± 2 %
Low-drop voltage
Very low standby current consumption
Overtemperature protection
Reverse polarity protection
Short-circuit proof
Settable reset threshold
Wide temperature range
Suitable for use in automotive electronics
Type
Ordering Code Package
TLE 4262 G
Q67006-A9068
P-DSO-20-6 (SMD)
▼ TLE 4262 GM Q67006-A9356
P-DSO-14-4 (SMD)
P-DSO-20-6
▼ New type
P-DSO-14-4
Functional Description
TLE 4262 G is a 5-V low-drop voltage regulator in a P-DSO-20-6 SMD package. The
maximum input voltage is 45 V. The maximum output current is more than 200 mA. The
IC is short-circuit proof and incorporates temperature protection that disables the IC at
overtemperature.
The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQrated = 5.0 V. A
reset signal is generated for an output voltage of VQ < 4.5 V. This voltage threshold can
be decreased to 3.5 V by external connection. The reset delay can be set externally with
a capacitor. The IC can be switched off via the inhibit input, which causes the current
consumption to drop from 720 µA to < 50 µA.
Semiconductor Group
1
1998-11-01
TLE 4262
Dimensioning Information on External Components
The input capacitor CI is necessary for compensating line influences. Using a resistor of
approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input
capacitance can be damped. The output capacitor is necessary for the stability of the
regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω within
the operating temperature range. For small tolerances of the reset delay, the spread of
the capacitance of the dalay capacitor and its temperature coefficient should be noted.
Pin Configuration
(top view)
TLE 4262 GM
TLE 4262 G
INH
QRES
GND
GND
GND
DRES
SRES
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VΙ
N.C.
GND
GND
GND
N.C.
VQ
AEP02588
Semiconductor Group
2
1998-11-01
TLE 4262
Pin Definitions and Functions
Pin
Symbol
Function
1
INH
Inhibit; TTL-compatible, low-active input
2
QRES
Reset output; open-collector output internally connected to
the output via a resistor of 30 kΩ.
4-7, 14-17
GND
Ground
9
DRES
Reset delay; connected to ground by a capacitor
10
SRES
Reset threshold; for setting the switching threshold connect
by a voltage divider from output to ground. If this input is
connected to GND, reset is triggered at an output voltage of
4.5 V.
11
VQ
5-V output voltage; block to ground by a 22−µF capacitor.
20
VI
Input voltage; block to ground directly at the IC by a ceramic
capacitor.
3, 8, 12,
13, 18, 19
N.C.
Not connected
Semiconductor Group
3
1998-11-01
TLE 4262
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element. If the externally scaled down
output voltage at the reset threshold input drops below 1.35 V, the external reset delay
capacitor is discharged by the reset generator. If the voltage on the capacitor reaches
the lower threshold VST, a reset signal is issued on the reset output and not cancelled
again until the upper threshold VdT is exceeded. If the reset threshold input is connected
to GND, reset is triggered at an output voltage of 4.5 V. The IC can be switched at the
TTL-compatible, low-active inhibit input. It also incorporates a number of internal circuits
for protection against:
●
●
●
Overload
Overtemperature
Reverse polarity
Block Diagram
Semiconductor Group
4
1998-11-01
TLE 4262
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
VI
II
– 42
–
45
–
V
–
–
internally limited
VR
IR
– 0.3
–
42
–
V
–
–
internally limited
VRE
– 0.3
6
V
–
Vd
Id
– 0.3
–
42
–
V
–
–
internally limited
VQ
IQ
– 5.25
–
VI
–
V
–
–
internally limited
Ve
– 42
45
V
–
IGND
– 0.5
–
A
–
Input
Input voltage
Input current
Reset Output
Voltage
Current
Reset Input
Reset threshold
Reset Delay
Voltage
Current
Output
Voltage
Current
Inhibit
Voltage
Ground
Current
Semiconductor Group
5
1998-11-01
TLE 4262
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
Tj
Tstg
–
– 50
150
150
°C
°C
–
–
Input voltage
VI
5.2
45
V
*)
Junction temperature
Tj
– 40
150
°C
–
Thermal resistance
junction-ambient
junction-case
Rth JA
Rth JC
–
–
70
25
K/W soldered
K/W –
Temperature
Junction temperature
Storage temperature
Operating Range
*)
Corresponds with characteristics of drop voltage, output current and power
description (see diagrams).
Semiconductor Group
6
1998-11-01
TLE 4262
Characteristics
VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Normal Operation
Output voltage
VQ
4.9
5.00
5.10
V
5 mA ≤ IQ ≤ 150 mA;
6 V ≤ VI ≤ 28 V;
– 40 °C ≤ Tj ≤ 125 °C
Output voltage
VQ
4.95
5.00
5.05
V
6 V ≤ VI ≤ 32 V;
IQ = 100 mA
Tj > 100 °C
Output current limiting
IQ
200
250
mA
–
Current consumption;
Iq = Ii – IQ
Iq
–
–
50
µA
Ve < 0.8 V
Iq
Iq
Iq
–
–
–
720
10
15
–
15
20
µA
mA
mA
IQ = 0 mA
IQ = 150 mA
IQ = 150 mA; Vi = 4.5 V
Drop voltage
VDr
–
0.35
0.6
V
IQ = 150 mA *)
Load regulation
∆VQ
–
–
25
mV
IQ = 5 mA to 150 mA
Supply-voltage
regulation
∆VQ
–
15
25
mV
VI = 6 V to 28 V;
IQ = 150 mA
Ripple rejection
SVR
–
54
–
dB
fr = 100 Hz;
Vr = 0.5 Vpp
Switching threshold
VRT
4.2
4.5
4.8
V
VRE = 0 V
Switching voltage
VRE
1.28
1.35
1.42
V
VQ > 3.5 V
Saturation voltage
VR
–
0.10
0.40
V
IR = 1 mA
Reset Generator
*)
Drop voltage VI ≥ 4.5 V; drop voltage = VI – VQ (below regulating range)
Note: The reset output is low within the range VQ = 1 V to VRT.
Semiconductor Group
7
1998-11-01
TLE 4262
Characteristics (cont’d)
VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise)
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit Test Condition
Saturation voltage
VC
–
50
100
mV
VQ < VRT
Charge current
Id
7
10
14
µA
–
Delay switching
threshold
VdT
1.5
1.7
2.1
V
–
Switching threshold
VST
0.2
0.35
0.55
V
–
Delay time
tD
–
17
–
ms
Cd = 100 nF
Delay time
tt
–
2
–
µs
Cd = 100 nF
Switch-ON voltage
Ve ON
3.5
–
–
V
IC turned on
Switch-OFF voltage
Ve OFF
–
–
0.8
V
IC turned off
Input current
Ie
5
10
15
µA
Ve = 5 V
Inhibit
Note: The reset output is low within the range VQ = 1 V to VRT.
Semiconductor Group
8
1998-11-01
TLE 4262
Input
6 V...45 V
11
20
Output
470 nF
9
1
KL15
22 µ F
TLE 4262G
Reset
to MC
2
100 k Ω
100 nF
10
56 k Ω
4
AES01084
Application Circuit
ΙΙ
1000 µF
Ι
11 Q
20
22 µF
470 nF
TLE 4262G
Ιe 1
VΙ + Vr
9
Ιd
Ve
VΙ
5.6 k Ω
Ι
2 R
Cd
100 nF
4
10
Ι GND
V cd
VQ
VR
V Dr = V Ι - V Q *)
Vr
SVR = 20 log
∆V Q
*) Below Regulating Range
AES01082
Test Circuit
Semiconductor Group
9
1998-11-01
TLE 4262
VΙ
<tt
V Q V RT
Vcd
dV Ι d
=
dt C d
V dT
V ST
tt
td
VR
Power-on-Reset
Overtemperature
Voltage Drop Undervoltage
at Input
Secondary
Spike
Load
Bounce
AET01085
Time Response
Semiconductor Group
10
1998-11-01
TLE 4262 G
Switching Voltage VdT and VST
versus Temperature
Charge Current versus
Temperature
AED01086
16
µA
Ι d 14
AED01087
3.2
V
V 2.8
V Ι = 13.5 V
12
2.4
Ιd
10
V Ι = 13.5 V
V cd = 1.5 V
8
1.6
6
1.2
4
0.8
2
0.4
0
-40
V dT , V cd
2.0
V ST
0
40
80
0
-40
120 C 160
Tj
Reset Switching Threshold
versus Temperature
80
40
120 C 160
Tj
Current Consumption of Inhibit
versus Temperature
Output Current
AED01088
1.6
V
V RE 1.4
0
AED01089
12
Ιe
µA
10
1.2
8
Ve = 5 V
1.0
0.8
6
0.6
4
0.4
2
0.2
0
-40
0
-40
0
40
Semiconductor Group
80
120 C 160
Tj
11
0
40
80
120 C 160
Tj
1998-11-01
TLE 4262 G
Output Voltage versus
Temperature
Output Current versus
Input Voltage
AED01090
5.2
VQ
AED01091
300
V
ΙQ
5.1
mA
T j = 25 C
250
200
5.0
Ve = 13.5 V
4.9
150
4.8
100
4.7
50
0
4.6
-40
0
40
80
120 C 160
Tj
Input Response
∆V Ι
t r = t f ~_ 1 µ s
5
40
mV
∆V Q 20
200
mV
∆V Q 100
C Q = 22 µ F
0
0
-20
-100
0
20
40 V 50
VΙ
30
10
20
-200
-10
40 µ s 50
30
C Q = 22 µ F
0
10
20
40 µ s 50
30
t
t
Semiconductor Group
AED01093
295
mA
∆ Ι Q 150
0
-40
-10
10
Load Response
AED01092
2
V
1
0
12
1998-11-01
TLE 4262
Drop Voltage versus
Output Current
Current Consumption versus
Output Current
AED01094
800
mV
V Dr 700
600
24
500
20
T j = 125 C
25 C
400
16
12
200
8
100
4
0
50
150
100
200
mA
ΙQ
0
300
Current Consumption versus
Input Voltage
0
100
150
200
mA
ΙQ
300
AED01097
12
mA
VQ
25
V
10
20
8
R L = 25 Ω
15
6
10
4
5
0
50
Output Voltage versus
Input Voltage
AED01096
30
Ιq
V Ι = 13.5 V
300
0
AED01095
32
mA
Ι q 28
R L = 25 Ω
2
0
10
20
Semiconductor Group
30
0
40 V 50
VΙ
13
0
2
4
6
8 V 10
VΙ
1998-11-01
TLE 4262
Package Outlines
1.27
0.35 x 45˚
7.6 -0.2 1)
0.23 +0.0
9
8˚ ma
x
2.65 max
2.45 -0.2
0.2 -0.1
P-DSO-20-6
(Plastic Dual Small Outline)
0.4 +0.8
0.35 +0.15 2)
0.2 24x
20
0.1
10.3 ±0.3
11
GPS05094
1 12.8 1) 10
-0.2
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Weight approx. 0.6 g
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
14
Dimensions in mm
1998-11-01
TLE 4262
P-DSO-14-4
(Plastic Dual Small Outline)
1.27
0.1
0.35 +0.15 2)
8˚ max.
4 -0.2 1)
0.19 +0.06
1.75 max
1.45 -0.2
0.2 -0.1
0.35 x 45˚
0.4 +0.8
0.2 14x
6 ±0.2
14
8
1
7
8.75 -0.21)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.05 max. per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
15
GPS05093
Dimensions in mm
1998-11-01