Dual Low-Drop Voltage Regulator TLE 4470 Features • • • • • • • • • • • • • Stand-by output 180 mA; 5 V ± 2 % Adjustable reset switching threshold Main output 350 mA; tracked to the stand-by output Low quiescent current consumption in standby mode Disable function for main output Wide operation range: up to 45 V Very low dropout Power-On-Reset circuit sensing the stand-by voltage Early warning comparator for supply undervoltage Output protected against short circuit Wide temperature range: – 40 °C to 150 °C Over-temperature protection Over-load protection P-DSO-14-4 P-DSO-20-6 Type Ordering Code Package TLE 4470 GS Q67006-A9309 P-DSO-14-4 (SMD) TLE 4470 G Q67006-A9308 P-DSO-20-6 (SMD) Functional Description The TLE 4470 is a monolithic integrated voltage regulator with two very low-drop outputs, a main output Q2 for loads up to 350 mA and a stand by output Q1 providing a maximum of 180 mA. The device is available in both the P-DSO-14-4 and P-DSO-20-6 packages. It is designed to supply microprocessor systems under the severe conditions of automotive applications and is therefore equipped with additional protection functions against over load, short circuit and over temperature. Of course the TLE 4470 can also be used in other applications where two stabilized voltages are required. The device operates in the wide temperature range of – 40 °C to 150 °C. The stand by regulator transforms an input voltage VI in the range of 5.6 V ≤ VI ≤ 45 V to VQ1rated = 5 V within an accuracy of 2%, whereas the main regulator is adjustable. By use of an external voltage divider the main output voltage can be set to VQ2 ≥ 5 V for the Semiconductor Group 1 1998-11-01 TLE 4470 TLE 4470 G type (P-DSO-20-6 package). VQ1 is compared to the voltage at pin VA, which is proportional to the output voltage VQ2. A control amplifier drives the base of the series PNP transistor via a buffer. The main output voltage VQ2 is tracked to the accuracy of the stand by output. For the TLE 4470 GS (P-DSO-14-4 package) the output voltage is fixed to 5 V. To save energy e.g. in battery powered body electronic applications, the main regulator can be switched off via the disable input, which causes the current consumption to drop to 180 µA typical. Two additional features of the TLE 4470 are an early warning comparator (can be used e.g. to monitor the supply voltage VI) and reset generator with an adjustable reset delay time. The TLE 4470 G (P-DSO-20-6 package) has in addition an adjustable reset switching threshold. This feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 V typical. Two functions are included in the reset generator, a power on reset and an under-voltage reset. The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. The reset LOW signal is generated for a certain delay time after the output voltage VQ1 of the regulator has surpassed the reset threshold. An external delay capacitor sets the delay time. The under voltage reset circuit supervises the stand-by output voltage. In case VQ1 falls below the reset switching threshold the reset output is set LOW after a short reaction time. The reset LOW signal is generated down to an output voltage VQ1 of 1 V. Pin Configuration (top view) P-DSO-14-4 D DIS GND GND GND RQ SQ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P-DSO-20-6 RADJ D DIS GND GND GND GND RQ SQ Q1 SI Ι GND GND GND Q2 Q1 AEP02152 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SI Ι1 Ι2 GND GND GND GND Q2 Q2 ADJ2 AEP02151 Figure 1 Semiconductor Group 2 1998-11-01 TLE 4470 Pin Definitions and Functions P-DSO-20-6 Pin No. Symbol Function 1 RADJ Reset switching threshold adjust; for setting the reset switching threshold connect to a voltage divider from Q1 to GND. If this input is connected to GND, the reset is triggered at the internal threshold. 2 D Reset delay; connect a capacitor CD to GND for delay time adjustment 3 DIS Disable input main regulator; Q2 disabled with high signal 4, 5, 6, 7 GND Ground 8 RQ Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 9 SQ Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 10 Q1 Stand-by regulator output voltage; block to GND with a capacitor CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz 11 ADJ2 Main regulator adjust input; Q2 can be set to higher values by an external divider 12, 13 Q2 Main regulator output voltage; block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz 14, 15, 16, 17 GND Ground 18 I2 Main regulator input voltage; block to GND directly at the IC with a ceramic capacitor 19 I1 Stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor 20 SI Sense comparator input Semiconductor Group 3 1998-11-01 TLE 4470 P-DSO-14-4 Pin No. Symbol Function 1 D Reset delay; connect a capacitor CD to GND for delay time adjustment 2 DIS Disable input main regulator; Q2 disabled with high signal 3, 4, 5 GND Ground 6 RQ Reset output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 7 SQ Sense output; the open collector output is connected to Q1 via an integrated 30 kΩ resistor 8 Q1 Stand-by regulator output voltage; block to GND with a capacitor, CQ1 ≥ 6 µF, ESR < 10 Ω at 10 kHz 9 Q2 Main regulator output voltage; 5 V output tracking to Q1, block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 10 Ω at 10 kHz 10, 11, 12 GND Ground 13 I Main and stand-by regulator input voltage; block to GND directly at the IC with a ceramic capacitor 14 SI Sense comparator input RADJ Reset switching threshold adjust not available in P-DSO-14-4 package. Reset is always triggered at the internal threshold. ADJ2 Main regulator adjust input is internally connected to VQ2 Semiconductor Group 4 1998-11-01 TLE 4470 Ι1 19 10 Reference Ι2 DIS 18 Q1 Stand-by-Regulator 12, 13 V REF 11 3 Q2 ADJ2 Main Regulator 2 V REF 8 Ιd = V RADJTH Reset SI 30 k Ω V Q1 1 30 k Ω 9 D RQ RADJ SQ 20 4-7 14-17 GND = Sense V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AEB02153 Figure 2 Block Diagram Semiconductor Group 5 1998-11-01 TLE 4470 Absolute Maximum Ratings – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks min. max. – 42 45 V – – – mA Internally limited VI2 II2 – 42 45 V – – – mA Internally limited VQ1 IQ1 –1 7 V – – – mA Internally limited VQ2 IQ2 –1 – 36 – V mA – Internally limited VADJ2 IADJ2 – 0.3 – 18 – V mA – Internally limited VSQ ISQ – 0.3 –5 25 5 V mA – – VRQ IRQ – 0.3 25 V – –5 5 mA – Stand-by Regulator Input Voltage VI1 Voltage Current VI1 II1 Main Regulator Input Voltage VI2 Voltage Current Stand-by Output VQ1 Voltage Current Main Output VQ2 Voltage Current Main Regulator Adjust Input ADJ2 Voltage Current Sense Output SQ Voltage Current Reset Output RQ Voltage Current Semiconductor Group 6 1998-11-01 TLE 4470 Absolute Maximum Ratings (cont’d) – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks min. max. VDIS IDIS – 42 –2 45 2 V mA – – VSI ISI – 25 –2 18 2 V mA – – VD ID – 0.3 –2 7 2 V mA – – Disable Input DIS Voltage Current Sense Input SI Voltage Current Reset Delay D Voltage Current Reset Switching Threshold Adjust RADJ Voltage Current VRADJ IRADJ – 0.3 – 7 – V mA – Internally limited Tj Tstg – 50 150 °C – – 50 150 °C – Temperatures Junction temperature Storage temperature Note: ESD-Protection according to MIL Std. 883: ± 2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 7 1998-11-01 TLE 4470 Operating Range Parameter Symbol Limit Values min. max. Unit Remarks Stand-by regulator input voltage VI1 5.6 45 V – Main regulator input voltage VI2 VQnom + 0.6 V 45 V – Stand-by regulator output current IQ1 0 180 mA – Main regulator output current IQ2 0 350 mA – Disable input voltage VDIS VSI Tj – 0.3 45 V – – 0.3 17 V – – 40 150 °C – Rthj-pin Rthj-a – 25 K/W Measured to pin 4 – 65 K/W – Sense input voltage Junction temperature Thermal Resistances Junction pin Junction ambient Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 8 1998-11-01 TLE 4470 Electrical Characteristics VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. VQ1 IQ1 4.90 5.0 5.10 V 1 mA < IQ1 < 100 mA 180 280 – mA see note 1 VDRQ1 – 300 500 mV IQ1 = 100 mA; see note 1 – 180 250 µA – 180 300 µA IQ1 = 300 µA; Tj = 25 °C VDIS > VDISH IQ1 = 300 µA; Stand-by Regulator Output 1 Output voltage Output current limitation Output drop voltage; VDRQ1 = VI1 – VQ1 Current Consumption Quiescent current; stand-by Iq = II1 – IQ1 Iq VDIS > VDISH Quiescent current Iq = II1 – IQ1 Iq – 4 6 mA IQ1 = 100 mA Regulator Performance Load regulation ∆VQ1 – 15 50 mV 1 mA < IQ1 < 150 mA; Load regulation ∆VQ1 – 5 25 mV 1 mA < IQ1 < 100 mA; Line regulation ∆VQ1 – 5 20 mV IQ1 = 1 mA; 6 V < VI1 < 28 V Power-Supply-Ripple- PSRR Rejection – 60 – dB 20 Hz < fr < 20 kHz; Vr = 5 VSS Temperature output voltage drift ∆VQ1/∆T – 0.3 – mV/K – dVI1/dt stability VQ1 CQ1 4.5 – 5.5 V no reset occurs; note 3 6 – – µF – RESRQ1 – – 10 Ω at 10 kHz Value of output capacitance ESR of output capacitance Semiconductor Group 9 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Main-Regulator Output 2 Output voltage tracking accuracy VQ2 – VQ1 – 25 5 25 mV 5 mA < IQ2 < 100 mA; 6 V < VI2 < 40 V Output voltage tracking accuracy VQ2 – VQ1 – 25 5 25 mV 5 mA < IQ2 < 250 mA; 7 V < VI2 < 28 V see note 2 Adjust input current IADJ2 IQ2 –1 – 1 µA – 350 500 – mA see note 1 VDRQ2 – 300 600 mV IQ2 = 200 mA; see note 1 IQ2 = 200 mA IQ1 = 300 µA IQ2 = IQ1 = 300 µA; Output current limitation Output drop voltage VDRQ2 = VI2 – VQ2 Current Consumption Quiescent current; Iq = II – IQ Iq – 7 15 mA Quiescent current; Iq = II – IQ Iq – 250 500 µA Tj = 25 °C Regulator Performance Load regulation ∆VQ2 – 5 25 mV 5 mA < IQ2 < 200 mA; Line regulation ∆VQ2 – 5 20 mV IQ2 = 5 mA; 6 V < VI2 < 28 V – 60 – dB 20 Hz < fr < 20 kHz; Vr = 5 Vss Temperature output voltage drift ∆VQ2/∆T – 0.5 – mV/K – dVI2/dt stability VQ2 CQ2 4.5 – 5.5 V no reset occurs; note 2 10 – – µF – Power-Supply-Ripple- PSRR Rejection Value of output capacitance Semiconductor Group 10 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. RESRQ2 – – 10 Ω at 10 kHz H-input voltage threshold VDISH 1.8 2.0 2.3 V – L-input voltage threshold VDISL 1.4 1.7 2.0 V Output 2 active H-input current IDISH IDISL –2 –1 1 µA 2.3 V < VDIS < 7 V –6 –2 – 0.5 µA 0 V < VDIS < 1.4 V ESR of output capacitance Disable Input DIS L-input current Reset Timing D and Output RQ Reset switching threshold VRT 4.5 4.65 4.8 V RADJ connected to GND Reset adjust threshold VRADJTH 1.25 1.35 1.45 V VQ1 > 3.5 V Reset output low voltage VRQL – 0.15 0.3 V RRQ = 10 kΩ external connected to VQ1; VQ1 ≥ 1 V 4.5 – – V – 20 30 45 kΩ Internal connected to VQ1 3 5 9 µA VD = 1 V VRQH Reset pull up resistor RRQ Reset charging Id Reset high voltage current Upper timing threshold VDU 1.5 1.8 2.2 V – Lower timing threshold VDL 0.3 0.4 0.55 V – Reset delay time td tRR 12 15 20 ms – 0.5 2.0 µs CD = 47 nF CD = 47 nF Reset reaction time Semiconductor Group 11 1998-11-01 TLE 4470 Electrical Characteristics (cont’d) VI1 = VI2 = 14 V; VDIS < VDISL; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Sense Input SI and Output SQ Sense threshold voltage VSITH 1.28 1.35 1.45 V VSI decreasing Sense threshold hysteresis VSIHY 25 60 100 mV – Sense output low voltage VSQL – 0.15 0.4 V Sense output high voltage VSQH 4.5 – – V RSQ = 10 kΩ external connected to VQ1 VSI = 1.1 V; VI1 > 4.5 V VSI > 1.5 V 20 30 45 kΩ Internal connected to VQ1 Sense pull up resistor RSQ Note 1: Measured when the output voltage VQ has dropped 100 mV from the nominal value. Note 2: VQ2 connected to ADJ2 Note 3: Square wave at VI : 8 V to 18 V; f = 10 kHz; tr = tf ≤ 100 ns Semiconductor Group 12 1998-11-01 TLE 4470 Application Information D1 1N4004 VBatt Ι 1 19 5V 10 Q1 C Q1 10 µF ZD1 C Ι 36 V 100 nF ( R 1= R 2 ) 10 V Reference Ι 2 18 Control C Q2 22 µF Stand-by-Regulator 12, 13 Q2 V REF R1 DIS 3 11 ADJ2 R SI1 330 k Ω R2 Main Regulator V REF 2 D 8 RQ Ιd = V RADJTH Reset 30 k Ω V Q1 1 CD 100 nF RADJ 30 k Ω 9 SQ SI 20 C SI R SI2 100 kΩ 10 nF = Sense 4-7 14-17 GND V SITH Pin numbers valid for P-DSO-20-6 (TLE 4470 G) AES02154 Figure 3 Application Circuit Semiconductor Group 13 1998-11-01 TLE 4470 Input, Output The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors CQ1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF & CQ2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (P-DSO-20-6) the output voltage VQ2 of the main regulator can be adjusted to 5 V ≤ VQ2rated ≤ 20 V by connecting an external voltage divider to the voltage adjust pin VA. For VQ2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating VQ or R1 & R2 respectively the following equations can be used: VQ = Vref × (R1 + R2) / R2 or R1 = R × (VQ / Vref) R2 = R × R1 / (R1 – R) Definitions: R = R1 // R2 ; R ≈ 100 kΩ Vref = Output voltage of stand by regulator, typical 5 V Disable The main regulator of the TLE 4470 can be switched OFF by a voltage of 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor Cd which can be calculated as follows: Cd = (∆td × Id) / ∆V Cd = delay capacitor ∆td = delay time Id = charge current, typical 5 µA ∆V = Vdt, typical 1.8 V Vdt = upper delay switching threshold at Cd for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out Definitions: LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for Cd the reaction time can be estimated using the following equation: trr ≈ 20 s/F × Cd Semiconductor Group 14 1998-11-01 TLE 4470 VΙ < t RR V RT VQ dV Ι d = dt C D VDT VST VD t RR td V RO Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED01542 Figure 4 Reset Timing Reset Switching Threshold The internally set reset threshold is 4.65 V. When using the TLE 4470 G (P-DSO-20-6) this threshold can be adjusted to 3.5 V < VRTH < 4.6 V by connecting an external voltage divider to pin RADJ. If this pin is not needed, it can be left open or even better connected to GND. R1 = R2 × (VRT – Vref) / Vref Definitions: VRT = Reset threshold Vref = comparator reference voltage, typical 1.35 V (Reset adjust input current ≈ 50 nA) The reset output pin is internally connected to the stand-by output Q1 via a 30 kΩ pull-up resistor. The reset LOW signal at pin RQ in guaranteed down to an output voltage VQ1 of 1 V typical. Semiconductor Group 15 1998-11-01 TLE 4470 VQ1 V I1 30 k Ω Band-Gap Reference 1.35 V RO Band-Gap Reference 1.35 V <_ 1 + _ R1 RADJ TLE 4470 G GND R2 AES02505 Figure 5 Early Warning The early warning function compares a voltage defined by the user to an internal reference voltage. Therefore the voltage to be supervised has to be scaled down by an external voltage divider in order to compare it to internal sense threshold (reference voltage) which is typically 1.35 V. The sense out pin is set to low when the user defined voltage falls below this threshold. A typical example where this circuit can be used is to supervise the input voltage VI to give the microprocessor a prewarning of a low battery condition. Calculation of the voltage divider can be easily done since the sense input current can be neglected. To minimize transient influences the use of a capacitor in parallel to R2 is recommended. Like the reset output pin, the sense out pin SQ is internally connected to the stand-by output Q1 via a 30 kΩ pull-up resistor. The sense out LOW signal at pin SQ is generated down to an input voltage VI1 of 3 V typical. Semiconductor Group 16 1998-11-01 TLE 4470 Typical Performance Characteristics Drop Voltage Vdr versus Output 1 Current IQ1 AED02491 600 Vdr Output Voltage VQ1/VQ2 versus Output Current IQ1 Vdr = VQnom -0.1 V VQ2 OFF mV AED02493 6 VQ1 / VQ2 V 500 5 400 4 T j = 25 ˚C VQ1 300 3 T j = 125 ˚C T j = 25 ˚C T j = -40 ˚C 200 2 1 100 0 VQ2 0 0 50 100 150 200 mA 300 0 100 200 300 400 mA 500 Ι Q1 Ι Q1 Drop Voltage Vdr versus Output 2 Current IQ2 Output 1 Voltage VQ1 versus Temperature Tj AED02492 600 Vdr mV AED02494 5.2 VQ1 Vdr = VQnom -0.1 V V 5.1 500 V Ι = 13.5 V 400 5 300 4.9 200 4.8 T j = 125 ˚C T j = 25 ˚C T j = -40 ˚C 100 0 0 50 100 150 200 4.7 mA 4.6 -40 300 Ι Q2 Semiconductor Group 0 40 80 120 ˚C 160 Tj 17 1998-11-01 TLE 4470 Output Voltage VQ1, VQ2 versus Input Voltage VI (VI1 = VI2) AED02495 6 VQ Current Consumption Iq versus Output 1 Current IQ1 (low load) V T j = 25 ˚C V Ι = 13.5 V VQ2 OFF V Q1 / V Q2 5 2500 4 2000 3 1500 T j = 25 ˚C Ι Q1 = 10 mA Ι Q2 = 10 mA VQ1nom = VQ2nom = 5 V 2 1000 1 0 AED02497 3000 Ι q µA VΙ = VQ 500 0 2 6 4 8 0 V 10 0 10 20 30 VΙ Ι Q1 Current Consumption Iq versus Input Voltage VI Current Consumption Iq versus Output 1 Current IQ1 (high load) AED02496 6 5 25 20 3 15 2 10 1 5 0 10 20 30 0 V 40 0 50 100 150 200 mA 250 Ι Q1 VΙ Semiconductor Group T j = 25 ˚C V Ι = 13.5 V VQ2 OFF Ι q mA 4 0 AED02498 30 T j = 25 ˚C Ι Q1 < 1 mA Ι Q2 = 10 mA Ι q mA mA 40 18 1998-11-01 TLE 4470 Current Consumption Iq versus Output 2 Current IQ2 (low load) Reset Adjust Threshold VRADJTH versus Temperature Tj AED02499 1800 Ι q µA 1500 1.5 1200 1.4 900 1.3 600 1.2 300 1.1 0 0 10 20 AED02501 1.6 V RADJTH V T j = 25 ˚C V Ι = 13.5 V Ι Q1 = 0 mA 30 40 1.0 -40 mA 60 0 40 80 Ι Q2 Tj Current Consumption Iq versus Output 2 Current IQ2 (high load) Ιq Switching Voltage VDU, VDL versus Temperature Tj AED02500 30 mA VD 2,4 V 25 2.0 20 1.6 15 1.2 10 0.8 5 0.4 0 0 50 100 150 200 0 -40 mA 300 Ι Q2 Semiconductor Group 120 ˚C 160 AED02502 VΙ = 13,5 V V DU 0 40 80 120 ˚C 160 Tj 19 1998-11-01 TLE 4470 Charge Current Id versus Temperature Tj AED02503 8 Ι d µA Sense Threshold VSITH versus Temperature Tj VSITH V V Ι = 13.5 V VD = 1 V 7 1.5 6 1.4 5 1.3 4 1.2 3 1.1 2 -40 AED02504 1.6 V Ι = 13.5 V 0 40 80 1 -40 120 ˚C 160 40 80 120 ˚C 160 Tj Tj Semiconductor Group 0 20 1998-11-01 TLE 4470 Package Outlines P-DSO-14-4 (Plastic Dual Small Outline) 1.27 0.1 0.35 +0.15 2) 8˚ max. 4 -0.2 0.19 +0.06 1.75 max 1.45 -0.2 0.2 -0.1 0.35 x 45˚ 1) 0.4 +0.8 0.2 14x 6 ±0.2 14 8 1 7 8.75 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 21 GPS05093 Dimensions in mm 1998-11-01 TLE 4470 1.27 0.35 x 45˚ 7.6 -0.2 1) 0.23 +0.0 9 8˚ ma x 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-20-6 (Plastic Dual Small Outline) 0.4 +0.8 0.35 +0.15 2) 0.2 24x 20 0.1 10.3 ±0.3 11 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 22 Dimensions in mm 1998-11-01