5-V Low-Drop Fixed Voltage Regulator TLE 4278 G Features • • • • • • • • • • • • Output voltage tolerance ≤ ±2% Very low current consumption Separated reset and watchdog output Low-drop voltage Watchdog Adjustable watchdog activating threshold Settable reset threshold Overtemperature protection Reverse polarity protection Short-circuit proof Suitable for use in automotive electronics Wide temperature range P-DSO-14-4 Type Ordering Code Package TLE 4278 G Q67006-A9291 P-DSO-14-4 (SMD) Functional Description The TLE 4278 is a monolithic integrated low-drop fixed-voltage regulator which can supply loads up to 200 mA. The device is available in the P-DSO-14-4 package. It is designed to supply microprocessor systems under the severe conditions of automotive applications and therefore is equipped with additional protection functions against over load, short circuit and over temperature. Of course the TLE 4278 can also be used in other applications where a stabilized voltage is required. An input voltage VI in the range of 5.5 V ≤ VI ≤ 45 V is regulated to VQrated = 5 V within an accuracy of ± 2%. The device operates in the wide temperature range of Tj = – 40 to 150 °C. Semiconductor Group 1 1998-11-01 TLE 4278 G Two additional features of the TLE 4278 are a load dependent watchdog function as well as a power on reset and under voltage reset function with an adjustable reset delay time and adjustable reset switching threshold. The watchdog function monitors whether the microcontroller is functioning appropriately, including time base failures. In the case that there is no positive-going edge within a certain pulse repetition-time the watchdog output is set to LOW. Programming of the max. repetition time is done by the reset delay capacitor so that no additional external components are necessary. To prevent the microcontroller from a automatic reset in case of missing pulses, the watchdog output WO is separated from the reset output RO for the TLE 4278. The watchdog output can be used as an interrupt signal for the microcontroller. Pin WO can be externally connected to pin RO. When the controller is set to sleep mode or low power mode its current consumption drops and no watchdog pulses are created. In order to prevent the microcontroller from unnecessary wake ups due to missing pulses at pin WI the watchdog feature can be disabled as a function of the load. The switch off threshold is set by an external resistor to pin WADJ. This function can also be used as a timer, which periodically wakes up the controller. Therefore the pin WADJ has to be connected to the output Q. The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. For a certain delay time after the output voltage of the regulator has surpassed the reset threshold, a reset signal is generated. The delay time is set by an external delay capacitor. The under voltage reset circuit supervises the output voltage. In case VQ falls below the reset threshold the reset output is set LOW after a short reaction time. The reset LOW signal is generated down to an output voltage VQ of 1 V. In addition the reset switching threshold can be adjusted by an external voltage divider. This feature is useful with microprocessors which guarantee a safe operation down to voltages below the internally set reset threshold of 4.65 V typical. Semiconductor Group 2 1998-11-01 TLE 4278 G Pin Configuration (top view) P-DSO-14-4 WO WADJ GND GND GND D RADJ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 RO VΙ GND GND GND VQ WΙ AEP02113 Figure 1 Pin Definitions and Functions Pin Symbol Function 1 WO Watchdog Output; the open collector output is connected to the 5-V output via an integrated resistor of 30 kΩ. 2 WADJ Watchdog Adjust; an external resistor to GND determine the watchdog activating threshold. 3, 4, 5, GND 10, 11, 12 Ground 6 D Reset Delay; connect a capacitor to ground for delay time adjustment. 7 RADJ Reset Switching Threshold Adjust; for setting the switching threshold, connect a voltage divider from output to ground. If this input is connected to ground, the reset is triggered at the internal threshold. 8 WI Watchdog input; positive-edge-triggered input for monitoring a microcontroller. 9 VQ 5-V output voltage; block to ground with min. 10 µF capacitor, ESR < 10 Ω at 10 kHz. 13 VI Input voltage; block to ground directly on the IC with ceramic capacitor. 14 RO Reset output; the open collector output is connected to the 5-V output via an integrated resistor of 30 kΩ. Semiconductor Group 3 1998-11-01 TLE 4278 G Block Diagram VΙ 12 13 Temperature Sensor Protection Circuit 14 VQ RO Reset Generator + - Control Amplifier 7 1 Bandgap Reference 6 Watchdog 2 3-5, 10-12 WADJ GND RADJ WO D 8 WΙ AEB02114 Figure 2 Semiconductor Group 4 1998-11-01 TLE 4278 G Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max. VI II – 42 45 V – – – mA Internally limited VQ IQ –1 25 V – – – mA Internally limited VRO IRO – 0.3 25 V – –5 5 mA – VD ID – 0.3 7 V – –2 2 mA – Input Voltage VI Voltage Current Output Voltage VQ Voltage Current Reset Output RO Voltage Current Reset Delay D Voltage Current Reset Switching Threshold Adjust RADJ Voltage Current VRADJ IRADJ – 0.3 7 V – – – mA Internally limited VWI IWI – 0.3 7 V – – – mA Internally limited VWO IWO – 0.3 25 V – –5 5 mA – Watchdog Input WI Voltage Current Watchdog Output WO Voltage Current Semiconductor Group 5 1998-11-01 TLE 4278 G Absolute Maximum Ratings (cont’d) Tj = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max. VWADJ IWADJ – 0.3 7 V – – – mA Internally limited IGND – 100 50 mA – Tj Tstg – 50 150 °C – – 50 150 °C – Watchdog Adjust WADJ Voltage Current Ground GND Current Temperatures Junction temperature Storage temperature Note: ESD protection according to MIL Std. 883: ± 2 kV. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Operating Range Parameter Input voltage Junction temperature Symbol Limit Values Unit Notes min. max. VI Tj 5.5 45 V – – 40 150 °C – Rthj-a Rthj-pin – 70 K/W Measured to pin 4 – 25 K/W Measured to pin 4 Thermal Resistance Junction ambient Junction pin Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 6 1998-11-01 TLE 4278 G Electrical Characteristics VI = 13.5 V; – 40 °C ≤ Tj ≤ 125 °C (unless otherwise specified) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Output voltage VQ 4.90 5.00 5.10 V 1 mA ≤ IQ ≤ 150 mA; 6 V ≤ VI ≤ 28 V Output voltage VQ 4.8 5.0 5.2 V 1 mA ≤ IQ ≤ 50 mA; 28 V ≤ VI ≤ 45 V Output current limiting IQ Iq 200 350 – mA – 180 200 µA VQ = 4 V Tj = 25 °C; IQ = 0 mA Current consumption Iq = II – IQ Iq – 180 230 µA Current consumption Iq = II – IQ Iq – 5 12 mA IQ = 0 mA; Tj = 85 °C IQ = 150 mA Drop voltage; VDR = VI – VQ VDR – 0.25 0.5 V IQ = 150 mA1) Load regulation ∆VQ – 30 – 5 – mV Supply voltage regulation ∆VQ – 5 20 mV IQ = 5 to 150 mA; VI = 6 V VI = 6 to 28 V IQ = 5 mA Reset threshold VRT 4.5 4.65 4.8 V RADJ connected to GND Reset headroom ∆VQ,RT 180 300 – mV Reset adjust threshold VRADJTH VROL 1.28 1.35 1.45 V – 0.20 0.40 V IQ = 10 mA VQ ≥ 3.5 V Rext = 10 kΩ to VQ VQ ≥ 1 V VROH RRO Id 4.5 – – V – 20 30 45 kΩ Internal connected to VQ 2 5 8 µA VD = 1.0 V Current consumption Iq = II – IQ Reset Generator Reset low voltage Reset high voltage Reset pull-up Charging current Semiconductor Group 7 1998-11-01 TLE 4278 G Electrical Characteristics (cont’d) VI = 13.5 V; – 40 °C ≤ Tj ≤ 125 °C (unless otherwise specified) Parameter Upper timing threshold Lower reset timing threshold Delay time Reset reaction time Symbol Limit Values Unit Test Condition min. typ. max. VDU VDRL 1.5 1.9 2.3 V – 0.2 0.3 0.4 V – td tRR 12 20 28 ms 0.4 1.0 2.0 µs CD = 47 nF CD = 47 nF 1.28 1.35 1.45 V Voltage at WADJ 650 720 800 – IQ ≤ 10 mA 5 – – V/µs From 20% up to 80% VQ – 0.2 0.4 V Rext = 10 kΩ to VQ 4.5 – – V – 20 30 45 kΩ Internal connected to VQ 2 5 8 µA 0.6 1.3 2.0 µA VD = 1.0 V VD = 1.0 V 1.5 1.9 2.3 V – 0.5 0.7 0.9 V – 42 60 80 ms Watchdog VWADJ IQ/IWADJ Current ratio VWI Slew rate Watchdog low voltage VWOL Watchdog high voltage VWOH RWO Watchdog pull-up Charge current Id Idis Discharge current Upper timing threshold VDU Lower watchdog timing VDWL Activating threshold threshold Watchdog output period TWP Watchdog output low time tWR 7 13 19 ms Cd = 47 nF VQ > VRT Watchdog trigger time TWT 35 47 61 ms Cd = 47 nF 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value. Semiconductor Group 8 1998-11-01 TLE 4278 G Test Circiut ΙΙ C Ι1 1000 µF Ι WO VΙ WO VΙ WΙ VWADJ 9 VQ ΙQ C Ι2 470 nF Ι WADJ WADJ VWO 13 VW VD CQ 10 µF TLE 4278 G 1 2 8 6 D Ι dis Ιd 3-5, 10-12 GND Ι GND RO 14 7 RADJ Ι RO VO VRO VRE CD 47 nF AES02115 VDR = VΙ -VO Outside the control range Figure 3 Semiconductor Group 9 1998-11-01 TLE 4278 G Application Information Input, Output The input capacitors CI1 and CI2 are necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI1, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuit the output capacitor CQ is necessary. Stability is guaranteed at values CQ ≥ 10 µF with an ESR ≤ 5 Ω within the operating temperature range. VΙ +12 V C Ι1 CΙ2 13 9 VQ 470 nF 1 TLE 4278G 14 8 3-5, 10-12 GND 6 D WO R1 CQ 22 µF RO WΙ RADJ 7 2 WADJ µP *) Cooling Area CD 47 nF R WADJ R2 *) or short to GND for internal threshold AES02116 Figure 4 Application Circuit Semiconductor Group 10 1998-11-01 TLE 4278 G Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor Cd which can be calculated as follows: Cd = (∆td × Id)/∆V Cd = delay capacitor ∆td = delay time Id = charge current, typical 5 mA ∆V = VDU, typical 1.9 V VDU = upper delay switching threshold at Cd for reset delay time The reset reaction time trr is the time it takes the voltage regulator to set the reset out Definitions: LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs for delay capacitor of 47 nF. For other values for Cd the reaction time can be estimated using the following equation: trr ≈ 20 s/F × Cd VΙ < t RR V RT VQ dV Ι d = dt C D VDT VST VD td t RR V RO Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output AED01542 Figure 5 Reset Timing (Watchdog Disabled) Semiconductor Group 11 1998-11-01 TLE 4278 G Reset Switching Threshold The present default value is 4.65 V. When using the TLE 4278 the reset threshold can be set to 3.5 V < VRTH < 4.6 V by connecting an external voltage divider to pin RADJ. The calculation can be easily done since the reset adjust input current can be neglected. If this feature is unused, the pin can be left open or even better connected to GND. R1 = R2 × (VRTH – Vref)/Vref Definitions: VRT = Reset threshold Vref = comparator reference voltage, typical 1.35 V (Reset adjust input current ≈ 50 nA) TLE 4278 G VQ VΙ 30 kΩ RO Band-GapReference Band-GapReference 1.35 V 1.35 V >1 + - R1 RADJ GND R2 AES02553 Figure 6 The reset output pin is internally connected to the 5 V-output Q via a 30 kΩ pull-up resistor. Down to an output voltage VQ of typical 1 V the reset LOW signal at pin RO in generated. For the timing of the reset feature please refer to the data sheet, figure 5. Semiconductor Group 12 1998-11-01 TLE 4278 G Watchdog Activating The calculation of the external resistor which adjusts the watchdog switch off threshold can be done by the following equation. RWADJ = VWADJ × (IQ/IWADJ)/IQACT Definitions: VWADJ = switch off threshold, typical 1.35 V IQ/IWADJ = current ratio, typical 720 IQACT = switch off load current TLE 4278 G VΙ VQ Band-GapReference HIGH + - WADJ Watchdog active LOW Watchdog disabled R WADJ GND AES02552 Figure 7 Semiconductor Group 13 1998-11-01 TLE 4278 G Watchdog Timing The frequency of the watchdog pulses has to be higher than the minimum pulse sequence which is set by the external reset delay capacitor Cd. Calculation can be done according to the formulas given in figure 8. The watchdog output is internally connected to the output Q via a 30 kΩ pull-up resistor. To generate a watchdog created reset signal for the microcontroller the pin WO can be connected to the reset input of the microcontroller. It is also allowed to parallel the watchdog out to the reset out. VW Ι VΙ T WP VQ T WT VDU VD VDWL t WR VWO T WP = (VDU - VDWL ) (Ι d + Ι dis ) Ι d x Ι dis C D; t WR = VDUL = VDRL (VDU - VDWL ) Ιd C D; T WT = (VDU - VDWL ) Ι dis CD AED01543 Figure 8 Timing of the Watchdog Function Semiconductor Group 14 1998-11-01 TLE 4278 G Hints for Unused Pins Symbol Function Connect to RO Reset output open D Reset delay open or to output Q RADJ Reset switching threshold adjust GND WI Watchdog input GND WO Watchdog output open WADJ Watchdog adjust 1) 2) Semiconductor Group 15 to output Q via a 270 kΩ resistor: Watchdog always active to GND: Watchdog disabled 1998-11-01 TLE 4278 G Drop Voltage VDR versus Output Current IQ Current Consumption Iq versus Output Current IQ AED01544 mV Ιq V DR AED01545 mA 700 14 600 12 500 10 400 8 V Ι =13.5 V Tj = 25 C Tj = 125 C 300 6 Tj = 25 C 200 4 100 2 0 0 50 100 150 200 250 0 mA 0 50 100 150 200 250 ΙQ ΙQ Current Consumption Iq versus Input Voltage VI Output Voltage VQ versus Input Voltage VI AED01546 mA Ιq mA AED01547 mA VQ Tj = 25 C 10 10 8 8 R L= 33 Ω 6 6 R L= 33 Ω 4 4 R L= 50 Ω 2 0 2 R L= 100 Ω 0 0 10 20 30 40 V 2 4 6 8 V VΙ VΙ Semiconductor Group 0 16 1998-11-01 TLE 4278 G Charge Current Id and Discharge Current Idis versus Temperature Tj Switching Voltage VDU, VDWL and VDRL versus Temperature Tj AED01548 µA Ι VD VΙ = 13.5 V VD = 1.0 V 7 2.8 V Ι = 13.5 V 6 2.4 Ιd 5 V DU 2.0 4 1.6 3 1.2 2 Ι dis 1 0 -40 AED01549 V 0 40 80 120 0.8 V DWL 0.4 V DRL 0 -40 C 0 40 80 Tj C Tj Output Voltage VQ versus Temperature Tj Output Current Limit IQ versus Input Voltage VI AED01550 V 120 AED01551 mA ΙQ VQ Tj = 25 C 250 5.1 VΙ = 13.5 V 5.0 200 4.9 150 4.8 100 4.7 50 4.6 -40 0 0 40 80 120 V 10 20 30 40 V Vj Tj Semiconductor Group 0 17 1998-11-01 TLE 4278 G Package Outlines P-DSO-14-4 (Plastic Dual Small Outline Package) 1.27 0.1 0.35 +0.15 2) 8˚ max. 4 -0.2 1) 0.19 +0.06 1.75 max 1.45 -0.2 0.2 -0.1 0.35 x 45˚ 0.4 +0.8 0.2 14x 6 ±0.2 14 8 1 7 8.75 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 18 GPS05093 Dimensions in mm 1998-11-01