ICs for Consumer Electronics Display Processor SDA 9280 B22 Data Sheet 1998-02-01 Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. SDA 9280 B22 Revision History: Current Version: 1998-02-01 Previous Version: 1997-11-01 Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) 31 ESD protection: Except: Pin 36 (SDA) ±300V added 33 Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25°C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved. SDA 9280 B22 1 1.1 1.2 1.3 1.4 1.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.12.1 2.12.2 2.12.3 2.12.4 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrominance Interpolation (Interpolator 1) . . . . . . . . . . . . . . . . . . . . . . . . . Luminance Peaking Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Color Transient Improvement (DCTI) . . . . . . . . . . . . . . . . . . . . . . . . Picture Manipulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16:9-Operation, Signal Compander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oversampling, Interpolator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insertion Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplification, D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-Output Signal Delay Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 36 4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 5.1 5.2 5.3 5.4 5.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram Data Input Referenced to the Clock . . . . . . . . . . . . . . . . . Timing Diagram Clock Skew SCA-CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format 4:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format 4:2:2 Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format CCIR 656 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Semiconductor Group 4 11 11 12 13 14 15 15 16 17 18 19 21 22 22 22 23 24 40 40 40 41 42 42 Display Processor SDA 9280 B22 MOS 1 Overview 1.1 Features • 8-Bit amplitude resolution of each input component Input sample frequency up to 30 MHz Application in flicker reduction systems possible • Four input data formats 4:1:1 luminance and chrominance parallel P-LCC-68-1 (8 + 4 wires) 4:2:2 CCIR 656-format (8 wires) 4:2:2 luminance and chrominance parallel (2 x 8 wires) 4:4:4 all components parallel (3 x 8 wires) • Two different representations of input data Positive dual code 2’s complement code • Three D/A converters on-chip 9-Bit amplitude resolution 80 MHz maximal clock frequency • DCTI (digital color transient improvement) A digital algorithm improves the sharpness of vertical color edges avoiding the artifacts of analog CTI-circuits • Luminance peaking Separate programmable lowpass, bandpass, and highpass digital filters • High performance digital interpolation for anti-imaging Two-fold oversampling Simplification of external analog postfiltering • 16:9 compatibility Signal compression for displaying 4:3-signals on16:9-screens Signal expansion for displaying 16:9-signals on 4:3-screens Full screen display of 4:3 letter box pictures Type Ordering Code Package SDA 9280 B22 Q67101-H5039-B502-35 P-LCC-68-1 Semiconductor Group 5 1998-02-01 SDA 9280 B22 • Programmable delay for the luminance signal Phase adjustment between luminance and chrominance signals • Signal manipulations Inverted display Graphic display • Insertion of colored areas Programmable color and position • Insertion of an arbitrary pattern Control by an external signal One of 4096 colors programmable Frame insertion for multi picture display • N-Fold zoom facility for image memory systems • Programmable internal PLL for clock generation Control of compression and expansion factors • I2C-Bus control • P-LCC-68-1 package • 5 V supply voltage 1.2 General Description The Display Processor SDA 9280 is an integrated triple 9 Bit D/A converter which performs digital enhancements and manipulations of digital video component signals. Multiple input data formats are accepted. Operation with normal as well as doubled horizontal deflection frequency is supported. 4:3 or 16:9 display formats are possible. Semiconductor Group 6 1998-02-01 SDA 9280 B22 SCL RES SCA INS BLN VSS TEST HS CLL VS TEST SDA VSS VSS VDD Pin Configuration VSS VDD 1.3 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 LF VCCI GNDY YQ VCCI VCCA GNDV VQ VCCI GNDU UQ GNDA V REF R REF VCC GND VSS 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 3 4 5 6 7 8 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 VSS UV7 UV6 UV5 UV4 UV3 VDD VDD 9 V5 V6 V7 UV0 UV1 UV2 VSS VSS V0 V1 V2 V3 V4 VSS VDD VDD VSS 61 62 63 64 65 66 67 68 1 2 VDD UEP10245 Figure 1 Semiconductor Group 7 1998-02-01 SDA 9280 B22 1.4 Pin Description Pin No. Symbol Type Description 1,17,35 VSS VSS S Supply voltage (VSS) for input stages S Supply voltage (VSS) for digital parts and PLL Note: no internal connection to pins No 1,17,35 VDD S Supply voltage (VDD) for digital parts, PLL and input stages Note: internal connection to VCCI, VCCA (about 2 Ω) 64 ... 68, 2 ... 4 V0 ... 7 I/TTL Data input V (see Data Input Formats) 5,6,7,12 ... 16 UV0 ... 7 I/TTL Data input UV (see Data Input Formats) 8,9,27,34,43, 60,63 10,11,26,33, 42,61,62 18 ... 25 YUV0 ... 7 I/TTL Data input YUV (see Data Input Formats) 28 BLN I/TTL Blanking signal, high level indicates active video line 29 INS I/TTL Control signal for insertion of an arbitrary pattern (frame insertion) 30 SCA I/TTL Clock signal for data input 31 RES I/TTL Reset signal (active low) for Ι2C Bus 32 SCL I Ι2C-Bus clock line 36 SDA IQ Ι2C-Bus data line 37 TEST 38 VS I/TTL Vertical synchronization signal for synchronizing Ι2C Bus (active: HIGH) 39 CLL I/TTL System clock 40 HS I/TTL Control signal for black level insertion (line frequency) 41 TEST Connect to VSS 44 LF PLL-filter connection 45,48,52 VCCI S Analog supply voltage for DACs internally connected to VDD, VCCA (about 2 Ω) 46 GNDY S Return path for YQ 47 YQ Q/ana Analog output: luminance signal Y 49 VCCA S Analog supply voltage internally connected to VDD, VCCI (about 2 Ω) 50 GNDV S Return path for VQ Semiconductor Group Don’t connect 8 1998-02-01 SDA 9280 B22 1.4 Pin Description (cont’d) Pin No. Symbol Type Description 51 VQ Q/ana Analog output: chrominance signal -(R-Y) 53 GNDU S Return path for UQ 54 UQ Q/ana Analog output: chrominance signal -(B-Y) 55 GNDA S Analog supply voltage 56 I/ana Analog reference voltage for DACs 58 VREF RREF VCC S Analog supply voltage 59 GND S Analog supply voltage 57 S: supply, I: input, Semiconductor Group Reference resistor for DACs Q: output, TTL: digital (TTL) 9 1998-02-01 SDA 9280 B22 1.5 Block Diagram VSS VDD 10 YUV UV 8 8 MUX 8 Variable 8 Y-Delay 8 9 GND GNDA VCC 7 VCCI VCCA 3 2 Peaking 9 Filter Compander 9 Inter- 10 polator 2 Insertion 9 Compander 9 Inter- 10 polator 2 Insertion Inter- 10 polator 2 Insertion DCTI R REF V REF 9 DAC 9 Bit YQ GNDY 9 DAC 9 Bit UQ GNDU 9 DAC 9 Bit VQ GNDV Interpolator 1 V 8 9 8 9 DCTI Compander 9 Ι 2 C-Bus Receiver SCA SDA SCL RES VS INS PLL BLN HS CLL LF UEB10244 Figure 2 Semiconductor Group 10 1998-02-01 SDA 9280 B22 2 System Description 2.1 Data Input Formats CCIR 656 4:2:2 INFOR = 00 Parallel INFOR = 10 Input Data Format 4:1:1 Pin INFOR = 01 4:4:4 INFOR = 11 YUV7 Y07 Y17 Y27 Y37 Y07 Y17 U07 Y07 V07 Y17 Y07 YUV6 Y06 Y16 Y26 Y36 Y06 Y16 U06 Y06 V06 Y16 Y06 YUV5 Y05 Y15 Y25 Y35 Y05 Y15 U05 Y05 V05 Y15 Y05 YUV4 Y04 Y14 Y24 Y34 Y04 Y14 U04 Y04 V04 Y14 Y04 YUV3 Y03 Y13 Y23 Y33 Y03 Y13 U03 Y03 V03 Y13 Y03 YUV2 Y02 Y12 Y22 Y32 Y02 Y12 U02 Y02 V02 Y12 Y02 YUV1 Y01 Y11 Y21 Y31 Y01 Y11 U01 Y01 V01 Y11 Y01 YUV0 Y00 Y10 Y20 Y30 Y00 Y10 U00 Y00 V00 Y10 Y00 UV7 U07 U05 U03 U01 U07 V07 U07 UV6 U06 U04 U02 U00 U06 V06 U06 UV5 V07 V05 V03 V01 U05 V05 U05 UV4 V06 V04 V02 V00 U04 V04 U04 UV3 U03 V03 U03 UV2 U02 V02 U02 UV1 U01 V01 U01 UV0 U00 V00 U00 V7 V07 V6 V06 V5 V05 V4 V04 V3 V03 V2 V02 V1 V01 V0 V00 XAB: X: signal component A: sample number B: bit number The SDA 9280 accepts four different data input formats (Ι2C signal: INFOR). Three sample frequency relations of Y:(B-Y):(R-Y) are possible (4:1:1 or 4:2:2 or 4:4:4). Semiconductor Group 11 1998-02-01 SDA 9280 B22 The representation of the samples is programmable separately for luminance and chrominance signals as positive dual code or 2’s complement code (Ι2C signals: INCODL, INCODC) The amplitude resolution for each input is 8 Bit, the maximal clock frequency is 30 MHz. Consequently the SDA 9280 is dedicated for applications in high quality digital video systems. The data input stages and the internal data multiplexer operate with a special data input clock (SCA). For applications in the Siemens MEGAVISION® System the SCA-clock is identical with the memory output clock. A separation of the data input clock and the system clock is relevant to handle the special data format occurring at “zoom” operation mode. For other applications SCA can be connected with CLL. Note: Zoom mode causes a greater signal delay time of the whole IC. Zoom mode identification is performed automatically. 2.2 Chrominance Interpolation (Interpolator 1) UED10246 10 dB 0 Amplitude -10 -20 -30 -40 -50 0 0.1 0.2 0.3 0.4 0.5 f fS Figure 3 Frequency Response of a Filter Stage of Interpolator 1 (ƒs is the sampling frequency at the output of the interpolation filter stage) For internal processing the 4:4:4 parallel format is used. The 4:1:1 data are interpolated by two interpolation filters having the same frequency response (see figure 3) to the 4:4:4 format. Each filter performs a doubling of the sample frequency. The 4:4:4 interpolation of 4:2:2 data is done by the second filter stage. The diagram shows the frequency response of one filter stage. Semiconductor Group 12 1998-02-01 SDA 9280 B22 Interpolation filtering can be switched off for each stage separately (Ι2C signals: INT422, INT444). Then each sample is simply repeated twice. Activation of interpolation filtering is recommended because analog postfiltering of chrominance signals then can be greatly simplified (see also Interpolator 2). 2.3 Luminance Peaking Filter The luminance peaking filter improves the over all frequency response of the luminance channel. It consists of three filters working in parallel. They have low pass (LP(z)), band pass (BP(z)) and high pass (HP(z)) characteristics. Their gain factors are separately programmable (Ι2C signals: LCOF, BCOF, HCOF) according to the following equations: LCOF * LP(z) + BCOF * BP(z) + HCOF * HP(z) with: LCOF = 0 ... [1/4] ... 3/2, 2 BCOF = 0 ... [1/4] ... 3, 7/2, 4, 5 HCOF = 0 ... [1/4] ... 3, 7/2, 4, 5 LP(z) = 1/16 * (1 + z-1)4 BP(z) = -1/8 * (1 - z-2)2 HP(z) = 1/16 * (1 - z-1)4 An amplification of up to 14 dB at the half of the sample frequency is available. The high pass and band pass filters are equipped with a common coring algorithm. It is optimized to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio. Therefore no artifacts are produced. Coring can be switched off (Ι2C signal: COR). Note: The peaking filter may shift the black level of the signal. This has to be considered for black level insertion (see Insertion Facilities). A delay line for the luminance signal enables an adaption to the delay of the chrominance signals. A range of -8 to +7 clock periods of the system clock CLL is programmable (Ι2C signal: YDEL1). An additional special filtering is available for compensating a non linear phase response of the analog part of the signal path. (1 + PHACOM) * z–1 - PHACOM Three adjustments are Ι2C-Bus programmable: PHACOM = 0, 1/4, 1/8. Semiconductor Group 13 1998-02-01 SDA 9280 B22 HP(z) HCOF YIN Coring BP(z) BCOF YOUT COR LP(z) LCOF UES10247 Figure 4 Luminance Peaking 2.4 Digital Color Transient Improvement (DCTI) A new digital algorithm is implemented to improve horizontal transitions of the chrominance signals resulting in a better picture sharpness. A slow change from one color to another by reason of small chrominance bandwidth is replaced by a steep transition. The exact position of a color transition (POS) is calculated by detecting the corresponding zero transition of the second derivative of both chrominance signals. Low pass filtering (LPU, LPV, LPUV) is performed to avoid noise sensitivity. The width of a transition is derived from a threshold detector signal. It indicates an area around the detected position where the first derivatives of the chrominance signals exceed a programmable threshold (Ι2C signal: THRESH). The parameter THRESH modifies the sensitivity of the DCTI-circuit. High values cause that only significant color transitions are improved. Small color variations remain unchanged. The detected transition width can be limited by the programmable parameter TRAWID. This parameter performs an adaption to the input chrominance band width. For signals with small chrominance bandwidth (e.g. video recorders) the DCTI-performance is optimized using high values for TRAWID. Input signals with high chrominance bandwidth should be processed with small values for TRAWID. If standard 4:1:1 video signals are processed, it is recommended to choose values of the mid range for both parameters THRESH and TRAWID. Semiconductor Group 14 1998-02-01 SDA 9280 B22 UIN LPU First Derivative Threshold WIDTH Detection THRESH LPUV VIN LPV Second Derivative POS Zero Transition Width Control Insertion of Steep Transition UOUT VOUT First Derivative TRAWID UES10248 Figure 5 Digital Color Transient Improvement 2.5 Picture Manipulations A graphic display effect is realized by programmable reduction of amplitude resolution (Ι2C signals: YGR, YGRRES, CGR, CGRRES). A resolution of 1 to 4 bits is available. A special characteristic avoids a reduction of picture brightness and color saturation. The inverted display mode is attained by a programmable bit inversion for each signal component (Ι2C signals: YINV, UINV, VINV). Multiple combinations of both manipulations supply very amazing effects on the display. 2.6 16:9-Operation, Signal Compander The compander enables a display with correct geometric proportions of 4:3 signals on 16:9-screens or 16:9-signals on 4:3-screens. A full screen display of 4:3-letterbox signals on 16:9-screens is also practicable. Having a full screen display of such signals on 4:3-screens only a part of the picture can be shown. In this operation mode a horizontal shift of the picture part used for display is programmable (Ι2C signal: READD). Expansion in vertical direction must be realized by manipulation of the vertical deflection current. To satisfy all these demands a horizontal compression or expansion of the video signals is performed by raising or reducing the sample frequency. The data are written into a memory using the system clock CLL and read with a clock of higher or lower frequency. Semiconductor Group 15 1998-02-01 SDA 9280 B22 This realization does not effect the horizontal detail resolution of the picture because no filtering is executed. The highest read frequency is 4/3 of the CLL-frequency for signal compression, the lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by the internal PLL. The compander operation mode is programmable via Ι2C signals COMP and COMEX. Note: Positioning of a 4:3-signal on a 16:9-screen is realized by delaying the HS-signal. HS also controls the deflection circuit. In the Siemens MEGAVISION® System a programmable HS-delay is available in the Memory Sync Controller (MSC) circuit. 2.7 Oversampling, Interpolator 2 UED10249 10 dB 0 Amplitude -10 -20 -30 -40 -50 0 0.1 0.2 0.3 0.4 0.5 f / fS Figure 6 Frequency Response of Interpolator 2 (ƒs is the sampling frequency at the output of the interpolation filter) In general D/A conversion requires postfiltering to avoid non-harmonic distortions caused by intermodulations of the signal with its spectral images. These intermodulations may come from non-linear characteristics of subsequent amplifier stages or of the display. The spectral images are duplicates of the signal spectrum around multiples of the sampling frequency. These images, a counterpart of aliasing in the A/D conversion, become visible after D/A conversion. They are only reduced by the sinx/x characteristic of the D/A converter. Semiconductor Group 16 1998-02-01 SDA 9280 B22 An example of such non-harmonic distortions are periodic stripes with a frequency of 900 kHz appearing in a 4.8 MHz test pattern which is sampled with 13.5 MHz clock frequency (2 * 4.8 MHz – (13.5 – 4.8) MHz = 900 kHz). The ideal postfiltering comprises an ideal lowpass filter with an edge frequency at the maximum signal frequency and a stop band rejection of at least 30 or 40 dB. In practice the postfilter can be greatly simplified when a large transition band is allowed. For this purpose a digital interpolator is implemented with a steep transition at the half of the sampling frequency and an out of band rejection of more than 30 dB before D/A conversion. Combined with a two-fold oversampling the first image appears around twice the sampling frequency, thus leaving considerably more space for the transition band of an analog postfilter. There is another good reason for using a digital interpolation. Since the output frequency may vary with different compression or expansion factors an analog filter with varying edge frequencies is necessary. This requirement can only be fulfilled in the digital domain because the edge frequency is linearly controlled by the sample frequency. The amplification factor of the implemented interpolation filter is 65/64. The maximal output clock frequency is 8/3 times of the input sample frequency. The diagram (figure 6) shows the frequency response. Oversampling can be switched off (Ι2C signal: OVSAMP). Then the 4:4:4 format is directly D/A converted. With activated oversampling it is possible to switch off oversampling filtering (Ι2C signal: OVFILT). In this operation mode the input clock frequency is doubled but each sample is simply repeated twice. 2.8 Insertion Facilities Three different values are inserted into the video signal: black level, a colored background area and an arbitrary colored pattern. The blanking interval of the input signal is not processed by the compander. Therefore the black level shifting in the luminance signal, caused by the peaking filter (coefficient LCOF) and the amplification factor of the oversampling filter, has to be restored by inserting the correct value (BLACK). BLACK is programmable and must be computed according to the coding of the input data using the following formulas: BLACK = 128 + 65/128 * LCOF * (BLACKIN – 128) BLACK = 128 + 65/128 * LCOF * BLACKIN for positive dual coding for 2’s complement BLACKIN is the black level of the input signal, LCOF is the Lowpass coefficient of the Luminance Peaking Filter: 0 ... [1/4] ... 1.5, 2 Black level insertion is controlled by the external signal HS. This signal also controls the deflection circuit, consequently it has a stable phase referring to the horizontal blanking interval. The value BLACK is inserted during 80 clock periods of the clock CLL. In the Siemens MEGAVISION® System HS is supplied by the MSC-circuit. To adjust the right insertion phase a programmable delay of HS is available (Ι2C signal: HSDEL). Semiconductor Group 17 1998-02-01 SDA 9280 B22 The second insertion facility produces a colored background area on the display controlled by Ι2C Bus. Activating this insertion mode (Ι2C signal: BACKGR) parts of the display area are covered with a constant color (Ι2C signals: COLBY, COLBU, COLBV). Starting at a programmable pixel position of each line (Ι2C signal: BCKPOS) the following part is covered with the background values. The width of the insertion is also programmable (Ι2C signal: BCKWID). To realize for example two vertical background stripes at the left and right side of the display BCKPOS should be set to a high value. Then the background color is inserted over the blanking interval (except the black level phases) up to the first active pixels of the following line fixed by BCKWID. An example for application is the display of a 4:3-picture on a 16:9-screen. The free parts of the display and also the noisy start and end of the picture can be filled with background color. An opening and closing curtain can also be realized using background insertion mode. Insertion of an arbitrary pattern is controlled by the external signal INS. The color of the pattern is programmable (Ι2C signals: COLFY, COLFU, COLFV). The insertion raster corresponds to the 4:4:4 format. A fixed phase to the video signal is guaranteed by processing the INS-signal by the compander. Using this insertion mode a colored framing for multi-picture mode can be realized. The MSC of the Siemens MEGAVISION® System supplies a suited signal (FRM). A connection of the BLN2-signal supplied by the MSC to the INS-input enables a complete blanking of the horizontal and vertical inactive parts of the video signal. The polarity of the INS-signal is programmable by Ι2C Bus (INSNEG). All insertions are performed after oversampling resulting in sharp transitions without overshooting. 2.9 Amplification, D/A Conversion Before D/A conversion a fine adjustment of the phase of the luminance signal is performed (Ι2C signal: YDEL2). The delay of the luminance signal can be varied by one period of the D/A converter clock. The amplification factors of each signal component can be reduced by a factor of 0.5 (Ι2C signals: AMPY, AMPU, AMPV). This reduction of nominal amplification reserves one bit for D/A conversion of overshooting, resulting from strong peaking or interpolation filtering. The input amplitude resolution of 8 Bit is not reduced. For conversion of signals without or with only small overshooting a reduction of the amplification factor is not necessary. A digital limiter circuit prevent the D/A converters from possible overdriving by clipping. Note: Clipping causes a non-linear deformation with interferences between multiples of the signal frequency and the sample rate of the signal and should be avoided by reducing the amplification factor. A triple 9 Bit D/A converter is implemented on the SDA 9280. The DACs are short circuit protected converters with current outputs. Semiconductor Group 18 1998-02-01 SDA 9280 B22 The Full Range Output Current of the Y, U, and V channels (IOFR) is determined by the current IREF at the RREF pin by IOFR ≅ (4/3) IREF The voltage at pin RREF is generated via pin VREF by an internal operational amplifier and follows the voltage at pin VREF. Thus IREF is given by IREF ≅ VVREF/RREF where RREF is a resistor between pin RREF and analog ground. Another way to define IREF is the application of a current sink at the RREF point. For recommended values of VVREF and IREF see chapter ’Recommended Operation Conditions’. For applications with lower requirements there is still another way to define IOFR: Connect pin VREF to the positive supply and apply a resistor against ground. Since in this operation mode the internal reference amplifier goes into saturation, the exact value of IREF is not so well predictable 2.10 PLL Circuit ÷2 Divider DIVVCO Phase Discriminator Reference Clock Divider DIVREF VCO Output Clock LF UES10250 Figure 7 The internal PLL supplies the clock signals needed for compander operation, output processing and D/A conversion. The output frequency of the PLL is defined by programming the divider factors of the reference clock and of the VCO clock (Ι2C signals: DIVREF, DIVVCO). The PLL always supplies the frequency needed for oversampling. The clocks used in the other output processing parts are derived from this oversampling clock. Even if no oversampling is programmed (OVSAMP = 0) DIVREF Semiconductor Group 19 1998-02-01 SDA 9280 B22 and DIVVCO must be set according to the respective oversampling frequency. The reference clock of the PLL is the system clock CLL. The output frequency of the PLL fOUTPUT is calculated by the following equation: fOUTPUT = fREFERENCE * (2 * DIVVCO) / DIVREF Note: An arbitrary setting of the output frequency is not allowed. It has to be observed that there is resulting an integer number of clock periods per line. E.g. the input signal has 858 clock periods per line, 3:4 signal expansion results in 858 * 3/4 = 643.5 clock periods per line, which is not an integer number. Therefore this adjustment results in phase jumps of the output clock and in an unstable working condition of the PLL. The following table gives an overview of possible PLL modes referred to an input signal with 864 pixels per line and a clock frequency of 13.5 MHz. Compression-/ Resulting Clock ExpansionPeriods per Factor Line Compander Read Frequency [MHz] DIVVCO DIVREF 4:3 1152 18 4 3 5:4 1080 16.875 5 4 11:9 1056 16.5 11 9 7:6 1008 15.75 7 6 9:8 972 15.1875 9 8 10:9 960 15 10 9 13:12 936 14.625 13 12 1:1 864 13.5 4 4 15:16 810 12.65625 15 16 11:12 792 12.375 11 12 8:9 768 12 8 9 7:8 756 11.8125 7 8 5:6 720 11.25 5 6 13:16 702 10.96875 13 16 7:9 672 10.5 7 9 3:4 648 10.125 3 4 The PLL circuit can be switched inactive (Ι2C signal: PLLON). In this mode the system clock is also used for output processing and D/A conversion. Semiconductor Group 20 1998-02-01 SDA 9280 B22 To achieve an optimal PLL operation an adaption to the required frequency range can be programmed (Ι2C signal: PLLRAN). 2.11 Input-Output Signal Delay Time Due to several digital signal processing stages transients of the digital input signal at the YUV inputs appear with a certain delay at the analog YUV outputs. In the following table are defined the values for two typical circuit configurations. The configuration of the circuit is defined as the total configuration of all programmable signal processing stages on the device, the programming itself is performed via the Ι2C Bus. Name Function Time delay Internal PLL Switched OFF (Subaddress 10H, Bit D5 ... D0 = 00 0000) 120 CLL typ Compander Bypassed (Subaddress 06H, Bit D1 = 0) Oversampling No (Subaddress 07H, Bit D1 ... D0 = 00) Input data format (Subaddress 00H, Bit D5 ... D4 = 01 or 10 or 11) Zoom No (frequency of SCA and CLL is identical) Internal PLL Switched ON 126 CLL typ (Subaddress 10H, Bit D5 ... D0 = 00 0010) (Subaddress 14H, Bit D7 ... D0 = 0100 0100) Compander Active without compression or expansion (Subaddress 06H, Bit D0 = 0) (Subaddress 06H, Bit D7 ... D2 = 000001) Oversampling Yes (Subaddress 07H, Bit D1 ... D0 = 11) Input data format (Subaddress 00H, Bit D5 ... D4 = 01 or 10 or 11) Zoom No (frequency of SCA and CLL is identical) Semiconductor Group 21 1998-02-01 SDA 9280 B22 2.12 I2C-Bus Control 2.12.1 I2C-Bus Address 0 0 1 0 1 1 0 2.12.2 I2C-Bus Format write: S 0 0 1 0 1 1 0 0 A Subaddress A Data Byte A ***** Data Byte n A Data Byte (n+1) A ***** A P read: S 0 0 1 0 1 1 0 1 A NA P Reading starts at the last write address n. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not acknowledge An automatical address increment function is implemented. After switching on the IC (RES = 0), all bits are set to defined states. Except the following bits the reset state is “0”. The bits YDEL13, BCOF2, LCOF2, HCOF2, DIVREF2, DIVVCO2 are set to “1” to ensure a basic working condition. In order to avoid distortions of the picture during the active lines, the following bits are updated internally only during the HIGH-phase of VS (the programming of the Ι2C-Bus interface however is not affected by this synchronisation): Subaddress Bit Subaddress Bit 00H D1 ... D0 07H D2 ... D0 02H D4 ... D0 09H D7 ... D0 03H D7 ... D0 0AH D7 ... D0 04H D6 ... D0 0BH D6 ... D0 05H D6 ... D0 0FH D0 06H D7 ... D0 Semiconductor Group 22 1998-02-01 SDA 9280 B22 2.12.3 I2C-Bus Commands Data Byte Subadd. (Hex.) D7 D6 D5 D4 D3 D2 D1 D0 00H INSNEG 0 INFOR1 INFOR0 INCODL INCODC INT422 INT444 01H THRESH3 THRESH2 THRESH1 THRESH0 TRAWID3 TRAWID2 TRAWID1 TRAWID0 02H 0 0 CGR CGRRES1 CGRRES0 UINV VINV 03H YGR YGRRES1 YGRRES0 YINV YDEL13 YDEL12 YDEL11 YDEL10 04H 0 LCOF2 LCOF1 LCOF0 BCOF3 BCOF2 BCOF1 BCOF0 05H 0 COR PHACOM1 PHACOM0 HCOF3 HCOF2 HCOF1 HCOF0 06H READD5 READD4 READD3 READD2 READD1 READD0 COMP COMEX 07H 0 0 0 0 0 BACKGR OVFILT OVSAMP 08H 0 0 HSDEL5 HSDEL4 HSDEL3 HSDEL2 HSDEL1 HSDEL0 09H BCKPOS7 BCKPOS6 BCKPOS5 BCKPOS4 BCKPOS3 BCKPOS2 BCKPOS1 BCKPOS0 0AH BCKWID7 BCKWID6 BCKWID5 BCKWID4 BCKWID3 BCKWID2 BCKWID1 BCKWID0 0BH 0 BLACK6 BLACK5 BLACK4 BLACK3 BLACK2 BLACK1 BLACK0 0CH COLFY3 COLFY2 COLFY1 COLFY0 COLBY3 COLBY2 COLBY1 COLBY0 0DH COLFU3 COLFU2 COLFU1 COLFU0 COLBU3 COLBU2 COLBU1 COLBU0 0EH COLFV3 COLFV2 COLFV1 COLFV0 COLBV3 COLBV2 COLBV1 COLBV0 0FH 0 0 0 0 AMPY AMPU AMPV YDEL2 10H PLLRAN1 PLLRAN0 0 0 0 0 PLLON 0 11H 0 1 0 0 0 0 0 0 12H 0 0 0 0 0 0 0 0 13H 0 0 0 0 0 0 1 0 14H DIVREF3 DIVREF2 DIVREF1 DIVREF0 DIVVCO3 DIVVCO2 DIVVCO1 DIVVCO0 Semiconductor Group 0 23 1998-02-01 SDA 9280 B22 2.12.4 Detailed Description Subaddress 00H: Interpolation Mode and Input Format Bit Name Function D0 INT444 4:4:4 Interpolation filtering: 0: interpolation 4:2:2 –> 4:4:4 OFF 1: interpolation 4:2:2 –> 4:4:4 ON D1 INT422 4:2:2 Interpolation filtering: 0: interpolation 4:1:1 –> 4:2:2 OFF 1: interpolation 4:1:1 –> 4:2:2 ON D2 INCODC Coding of chrominance input data: 0: positive dual code 1: 2’s complement D3 INCODL Coding of luminance input data: 0: positive dual code 1: 2’s complement D5, D4 INFOR Input data format: 00: CCIR 656 01: 4:1:1luminance, chrominance parallel (8 + 4 wires) 10: 4:2:2luminance, chrominance parallel (2 x 8 wires) 11: 4:4:4all components parallel (3 x 8 wires) D6 D7 No function assigned. Assign binary value: 0 INSNEG Polarity of INS input signal: 0: positive polarity 1: negative polarity Subaddress 01H: Digital Color Transition Improvement Control Bit Name Function D3 ... D0 TRAWID DCTI: 0000: 0001: : 1100: D7 ... D4 THRESH DCTI: 0000: : 1111: Semiconductor Group maximal length of an improved transition: DCTI OFF 2 pixel : 24 pixel sensitivity threshold: lowest threshold (highest sensitivity) : highest threshold (lowest sensitivity) 24 1998-02-01 SDA 9280 B22 Subaddress 02H: Color Feature Control Bit Name Function D0 VINV Inversion of (R-Y)-signal: 0: inversion OFF 1: inversion ON D1 UNIV Inversion of (B-Y)-signal: 0: inversion OFF 1: inversion ON D3, D2 CGRRES Amplitude resolution of chrominance signals (CGR = 1): 00: 1 Bit 01: 2 Bit 10: 3 Bit 11: 4 Bit D4 CGR D7 ... D5 Chrominance graphic display: 0: OFF 1: ON No function assigned. Assign binary value : 000 Subaddress 03H: Luminance Feature Control Bit Name Function D3 ... D0 YDEL1 Delay adjustment of luminance signal: 0000: -8 clock periods (CLL) 0001: -7 clock periods (CLL) : : 1000: no delay : : 1111: +7 clock periods (CLL) D4 YINV Inversion of luminance signal: 0: inversion OFF 1: inversion ON D6, D5 YGRRES Amplitude resolution of luminance signal (YGR = 1): 00: 1 Bit 01: 2 Bit 10: 3 Bit 11: 4 Bit D7 YGR Semiconductor Group Luminance graphic display: 0: OFF 1: ON 25 1998-02-01 SDA 9280 B22 Subaddress 04H: Luminance Peaking Control Bit Name Function D3 ... D0 BCOF Luminance peaking, gain of band pass filter: 0000: 0 0001: 1/4 : : : [1/4] : : 1100: 12/4 1101: 14/4 1110: 16/4 1111: 20/4 D6 ... D4 LCOF Luminance peaking, gain of low pass filter: 000: 0 001: 1/4 : : : [1/4] : : 110: 6/4 111: 8/4 D7 Semiconductor Group No function assigned. Assign binary value: 0 26 1998-02-01 SDA 9280 B22 Subaddress 05H: Luminance Peaking Control Bit Name Function D3 ... D0 HCOF Luminance peaking, gain of high pass filter: 0000: 0 0001: 1/4 : : : [1/4] : : 1100: 12/4 1101: 14/4 1110: 16/4 1111: 20/4 D5, D4 PHACOM Filter coefficient for compensation of non-linear phases: 00: 0 01: 1/8 10: 2/8 D6 COR D7 Semiconductor Group Luminance peaking, coring for high- and band-pass filter: 0: OFF 1: ON No function assigned. Assign binary value: 0 27 1998-02-01 SDA 9280 B22 Subaddress 06H: Compander Control Bit Name Function D0 COMEX Compander working condition: 0: signal compression 1: signal expansion Note: For oversampling without compression or expansion COMEX = 0 is recommended in order to minimize the signal delay time. D1 COMP Compander activation: 0: bypass 1: compander active D7 ... D2 READD Compander, displayed picture part: (shifting raster: 4 pixels) 000000: not recommended 000001: left part of the picture : : 111111: right part of the picture Note: For signal compression READD = 101101 is required. For oversampling without compression or expansion READD = 000001 is required. Subaddress 07H: Oversampling Control (Interpolator 2) and Background Activation Bit Name D0 OVSAMP Oversampling control: 0: doubling of sample frequency OFF 1: doubling of sample frequency ON D1 OVFILT D2 BACKGR Activation of background insertion: 0: insertion OFF 1: insertion ON D7 ... D3 Semiconductor Group Function Oversampling control (OVSAMP = 1): 0: interpolation filtering OFF 1: interpolation filtering ON No function assigned. Assign binary value: 00000 28 1998-02-01 SDA 9280 B22 Subaddress 08H: Black Level Insertion Control Bit Name Function D5 ... D0 HSDEL Start of black level insertion, delay to HS-signal: 000000: no delay 000001: 16 clock periods (CLL) delay : : 111111: 1008 clock periods (CLL) delay Note: If HSDEL is greater than the number of samples per line there is no insertion of black level. D7 ... D6 No function assigned. Assign binary value: 00 Subaddress 09H: Background Insertion Control Bit Name Function D7 ... D0 BCKPOS Background insertion, positioning of inserted area: 00000000:starting at pixel 290 00000001:starting at pixel 292 : : 11111111:starting at pixel 800 Subaddress 0AH: Background Insertion Control Bit Name Function D7 ... D0 BCKWID Background insertion, horizontal width of inserted area: 00000000:136 pixel 00000001:140 pixel : : 11111111:1156 pixel Note: If BCKWID is greater than the number of pixels per line the whole line is filled with background color. Semiconductor Group 29 1998-02-01 SDA 9280 B22 Subaddress 0BH: Black Level Coding Bit Name Function D6 ... D0 BLACK Coding of inserted black level (Y-channel), computation see chapter ‘Insertion Facilities’: 0000000: 0 0000001: 1 : : 1111111: 127 D7 No function assigned. Assign binary value: 0 Subaddress 0CH: Background Color/Y Signal Bit Name Function D3 ... D0 COLBY Background color (luminance):4 MSBs D7 ... D4 COLFY Color of inserted pattern (luminance):4 MSBs Subaddress 0DH: Background Color/B-Y Signal Bit Name Function D3 ... D0 COLBU Background color (B-Y):4 MSBs D7 ... D4 COLFU Color of inserted pattern (B-Y):4 MSBs Subaddress 0EH: Background Color/R-Y Signal Bit Name Function D3 ... D0 COLBV Background color (R-Y):4 MSBs D7 ... D4 COLFV Color of inserted pattern (R-Y):4 MSBs Semiconductor Group 30 1998-02-01 SDA 9280 B22 Subaddress 0FH: Signal Amplification Bit Name Function D0 YDEL2 Delay fine adjustment of luminance signal: 0: no delay 1: 1 D/A converter clock period D1 AMPV Amplification of (R-Y) signal path: 0: amplification = 0.5 1: amplification = 1 D2 AMPU Amplification of (B-Y) signal path: 0: amplification = 0.5 1: amplification = 1 D3 AMPY Amplification of luminance signal path: 0: amplification = 0.5 1: amplification = 1 D7 ... D4 No function assigned. Assign binary value: 0000 Subaddress 10H: PLL Control Bit Name D0 D1 No function assigned. Assign binary value: 0 PLLON D5 ... D2 D7, D6 Function Activation of internal PLL: 0: PLL OFF 1: PLL ON No function assigned. Assign binary value: 0000 PLLRAN Frequency range of internal PLL: 00: 9 ... 13 MHz 01: 11 ... 40 MHz 10: 29 ... 60 MHz 11: 44 ... 80 MHz Subaddress 11H: Test Control Bit Name Function D7 ... D0 TEST11 Only for test conditions Semiconductor Group 31 1998-02-01 SDA 9280 B22 Subaddress 12H: Test Control Bit Name Function D7 ... D0 TEST12 Only for test conditions Subaddress 13H: Test Control Bit Name Function D7 ... D0 TEST13 Only for test conditions Subaddress 14H: PLL Control/VCO and Reference Clock Bit Name Function D3 ... D0 DIVVCO PLL-frequency programming, divider of VCO-clock: 0000: 16 0001: not allowed 0010: 2 : : 1111: 15 D7 ... D4 DIVREF PLL-frequency programming, divider of reference clock: 0000: 16 0001: not allowed 0010: 2 : : 1111: 15 Semiconductor Group 32 1998-02-01 SDA 9280 B22 3 Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. Operating temperature TA 0 70 °C Tstg Junction temperature Tj Soldering temperature TS -65 125 °C 125 °C 260 °C 10 s Storage temperature Soldering time Input voltage Output voltage Supply voltages VI VQ VDD -0.3 V VDD + 0.3 V 1 -0.3 V VDD + 0.3 V 1 Remark VCC respectively VCC respectively -0.3 6 V Supply voltage differentials -0.25 0.25 V Between any internally non-connected supply pins of the same kind, see Pin Description DAC output current -30 mA For any single output RREF output current -30 mA For any single output Total power dissipation Ptot 1.7 W ESD protection -2 2 kV MIL STD 883C method 3015.6, 100 pF, 1500 Ω Except: Pin 36 (SDA) ±300 V Latch-up protection -100 100 mA All inputs/outputs All voltages listed are referenced to ground (0 V, VSS) except where noted. Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Semiconductor Group 33 1998-02-01 SDA 9280 B22 3.1 Recommended Operating Conditions Parameter Symbol VDDxx VCCxx Ambient temperature TA Supply voltages Limit Values Unit min. nom. max. 4.75 5 5.25 V 0 25 70 °C 2.0 VDD V 0 0.8 V 30 MHz Remark All TTL Inputs H-input voltage L-input voltage VIH VIL Serial Clock TTL Input SCA SCA clock frequency fSCA SCA low time SCA high time tLOW tHIGH 0.02 27 10 ns 10 ns Rise/fall time ≥ 5 ns Line Locked Clock TTL Input CLL CLL clock frequency CLL low time CLL high time SCA-CLL skew time fCLL tLOW tHIGH tSK 6 27 30 MHz 10 ns 10 ns 0 15 ns Rise/fall time ≥ 5 ns Diagram on page 40 Digital to Analog Conversion DAC sample rate RREF output current VREF input voltage IREF VVREF 4.5 54 80 MHz -17 -14 -11 mA 1.8 2.1 2.4 V I2C Bus (All Values are Referred to min.(VIH) and max.(VIL)) VIH L-input voltage VIL SCL clock frequency fSCL Inactive time before tBUF H-input voltage 3 VDD V 0 1.5 V 0 100 kHz 4.7 µs start of transmission Set-up time start condition tSU;STA 4.7 µs Hold time start condition tHD;STA 4.0 µs SCL low time tLOW 4.7 µs Semiconductor Group 34 1998-02-01 SDA 9280 B22 3.1 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. SCL high time Set-up time DATA Hold time DATA SDA/SCL rise times SDA/SCL fall times Set-up time stop condition L-output current Semiconductor Group tHIGH tSU;DAT tHD;DAT tR tF tSU;STO nom. Unit Remark max. 4.0 µs 250 µs 0 µs 1 µs 300 ns µs 4.7 IOL 3 35 mA 1998-02-01 SDA 9280 B22 3.2 Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Limit Values Unit min. Average supply current ICC Remark max. mA All VCC and VDD pins 10 pF Not tested; max. 7 pF for SCA, CLL 10 µA 320 All Digital Inputs (Including I/O Inputs) Input capacitance CI Input leakage current II(L) -10 TTL Inputs: YUV, UV, V (Referenced to SCA); BLN, INS (Referenced To CLL) Set-up time tSU Input hold time tIH 7 6 ns See timing diagram 5.1 on page 40 ns See timing diagram 5.1 on page 40 TTL Inputs: VS, HS, RES (Asynchronous to any Clock) VS low time VS high time HS low time HS high time RES low time tLOW tHIGH tLOW tHIGH tLOW 4 µs 4 µs 12 1 CLL periods 12 1 CLL periods 100 ns For reliable reset Input/Output: SDA (Referenced to SCL; Open Drain Output) Low-level output voltage VOL 0.5 V At IOL = max 150 800 µA -800 -150 µA VLF = 2 V VLF = 2 V PLL: Pin LF (Analog) Loop filter charge Pump current Digital to Analog Conversion (9 Bit): Current Source Outputs YQ, UQ, VQ Full range output current IOFR VVREF = nom, TA = nom, IREF = nom, RL = 75 Ω VVREF = nom, TA = nom, IREF = nom, RL = 75 Ω -19.5 -16.5 mA Full range output current matching -1 1 mA Temperature dependency of IOFR -10 10 µA/°C Not tested; VVREF = nom, IREF = nom, RL = 75 Ω Semiconductor Group 36 1998-02-01 SDA 9280 B22 3.2 Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Limit Values Unit min. max. Supply voltage dependency of IOFR -0.2 0.2 Current source output resistance 20 Full range output voltage Remarky mA/V VVREF = nom, TA = nom, IREF = nom, RL = 75 Ω kΩ Not tested; VVREF = nom, TA = nom, IREF = nom 1.6 V VVREF = nom, TA = nom, IREF = nom, ||LE| ≤ max DC differential nonlinearity DLE -1 1 LSB DC integral nonlinearity ILE -2 2 LSB DAC Reference Pins: VREF, RREF (Analog) Offset voltage between VREF and RREF VREF input current Semiconductor Group VVREF VRREF -40 40 mV -10 10 µA 37 1998-02-01 SDA 9280 B22 4 Application Information 10 VDD 11 VDD 8 VSS 9 VSS 1 VSS 26 VDD 25 YUV7 24 YUV6 23 YUV5 22 YUV4 VSS VSS VDD 27 17 VSS 43 61 VDD 62 VDD 16 UV7 15 UV6 14 UV5 13 UV4 60 VSS 63 VSS 58 VCC GND SDA 9280 12 UV3 7 UV2 6 UV1 5 UV0 10 µH 5V 100 nF 10 µF 33 34 VSS 35 VSS 42 VDD 21 YUV3 20 YUV2 19 YUV1 18 YUV0 100 nF 59 100 nF 100 nF 100 nF 10 µH 100 nF 45 VCCI 48 VCCI 52 VCCI 49 VCCA 10 µH 100 nF 10 µH 13 kΩ 56 V REF 57 R REF 150 Ω 55 GNDA 54 UQ 100 nF 10 kΩ 100 nF 10 µH 10 nF - (B-Y) 100 Ω 4 3 2 68 67 66 65 64 GNDU V7 V6 V5 V4 V3 V2 V1 V0 VQ 53 10 nF 51 - (R-Y) 78 Ω GNDV YQ 50 47 nF 47 Y 39 Ω HS VS CLL SCL SDA 6.2 - 6.8 k Ω 1.5 nF 40 38 39 32 36 30 SCA 29 INS 31 RES 28 BLN 46 GNDY 44 LF UES10251 Figure 8 This application circuit is part of a Siemens MEGAVISION® application Note: The input data format must be selected via I2C Bus. Input data pins which are not used for the selected format should be connected to GND. Semiconductor Group 38 1998-02-01 SDA 9280 B22 Block Diagram of Standard Version Noise Reduction Cross Color Reduction Multipicture Decimation ADC Decimation 4 4 YI 4 3ADC SDA 9205-2 VI SYNC CSG SDA 9257 4 4:0:0 4 Picture Processor 2 SDA 9290 4:1:1 4 4:2:2 4 Display UOUT Processor SDA 9280 Chrominance SDA 9251X 4 YOUT 4 Chrominance SDA 9251X 4 4 Luminance SDA 9251X 4 4 UI SDA 9251X 4 4 Peaking CTI 16:9 Compansion Interpolation DAC Flicker Reduction Still Picture Zoom Multipicture 4:0:0 Luminance 4 4 4 4 4 SYNC MSC3 SDA 9220 VOUT SYNCOUT UEB10252 Figure 9 Semiconductor Group 39 1998-02-01 SDA 9280 B22 5 Waveforms 5.1 Timing Diagram Data Input Referenced to the Clock T t WH t WL V IH Clock Input t THL V IL t TLH V IH Input Data V IL t SU t IH UET10253 Figure 10 5.2 Timing Diagram Clock Skew SCA-CLL T t WH t WL V IH CLL t SK t THL V IL t TLH T t WH t WL V IH SCA t THL t TLH V IL UET10254 Figure 11 Semiconductor Group 40 1998-02-01 SDA 9280 B22 5.3 Input Data Format 4:1:1 144 138 Active Line: 720 BLN 50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL SCA BLN YUV7...0 Y0n Y1n Y2n Y3n Y4n Y5n Y6n Y7n Y8n Y9n Y10n Y11n Y12n Y13n UV7 U07 U05 U03 U01 U17 U15 U13 U11 U27 U25 U23 U21 U37 U35 UV6 U06 U04 U02 U00 U16 U14 U12 U10 U26 U24 U22 U20 U36 U34 UV5 V07 V05 V03 V01 V17 V15 V13 V11 V27 V25 V23 V21 V37 V35 UV4 V06 V04 V02 V00 V16 V14 V12 V10 V26 V24 V22 V20 V36 V34 UET10255 Figure 12 Semiconductor Group 41 1998-02-01 SDA 9280 B22 5.4 Input Data Format 4:2:2 Parallel 144 138 Active Line: 720 BLN 50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL SCA BLN YUV7...0 Y0n Y1n Y2n Y3n Y4n Y5n Y6n Y7n Y8n Y9n Y10n Y11n Y12n Y13n UV7...0 U0n V0n U1n V1n U2n V2n U3n V3n U4n V4n U5n V5n U6n V6n UET10256 Figure 13 5.5 Input Data Format CCIR 656 144 138 Active Line: 720 BLN 50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL SCA BLN U0n YUV7...0 Y0n V0n Y1n U1n Y2n V1n Y3n U2n Y4n V2n Y5n U3n Y6n UET10257 Figure 14 Note: XAB: X: signal component Semiconductor Group A: sample number 42 B: Bit number 1998-02-01 SDA 9280 B22 6 Package Outlines 5.08 max 1.2 x 45˚ 0.2 0.5 min 3.5 ±0.2 P-LCC-68-1 (Plastic Leaded Chip Carrier) 1.27 0.43 ±0.1 0.81 max 23.3 ±0.3 0.18 M A-B D 68x 20.32 24.21 ±0.07 1) 0.1 0.38 M A-B D 34x 25.28 -0.26 D B A 0.5 x 45˚ 3x 68 1 1.1 x 45˚ Index Marking 24.21 ±0.07 1) 25.28 -0.26 1) Does not include plastic or metal protrusions of 0.15 max per side GPL05099 Figure 15 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group Dimensions in mm 43 1998-02-01