ICs for Consumer Electronics DDC-PLUS-Deflection Controller SDA 9361 Data Sheet 1998-02-01 Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. SDA 9361 Revision History: Current Version: 1998-02-01 Previous Version: 1997-04-07 Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) 33 35 Setup time of input HSYNC (CLEXT=1) changed from 6 ns to 4 ns 35 37 Nom. average and max. stand-by current specified 35 37 Specification of charge current pump of PLL pin LF is unnecessary Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25°C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved. SDA 9361 Table of Contents Page 1 1.1 1.2 1.3 1.4 1.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 6 7 9 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Explanation of Some Control Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 12 14 15 16 16 16 17 18 24 3 3.1 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 37 4 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 5.1 5.2 5.3 5.4 5.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD- Output Voltage, 4/3-CRT and 16/9-Source . . . . . . . . . . . . . . . . . . . . . . Timing Diagram of SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On/Off Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Mode, RESN Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function of H,V Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Semiconductor Group 4 41 41 42 44 45 46 1998-02-01 DDC-PLUS-Deflection Controller SDA 9361 MOS 1 Overview 1.1 Features • • • • • • • • • • • • • • • • • • • • • Deflection - Protection - 16:9 / 4:3 No external clock needed Φ1 PLL and Φ2 PLL on chip Ι2C-Bus alignment of all deflection parameters P-MQFP-44-2 All EW-, V- and H- functions PW EHT compensation PH EHT compensation Compensation of H-phase deviation (e.g. caused by white bar) Upper/lower EW-corner correction separately adjustable V-angle correction: Vertical frequent linear modulation of H-phase V-bow correction: Vertical frequent parabolic modulation of H-phase Three reduced V-scan modes (75 %, 66 %, 50 % V-size) adjustable by only 2 Bits H-frequent PWM output signal for general purpose H- and V-blanking time adjustable Partial overscan adjustable to hide the cut off control measuring lines in the reducedscan modes Stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without annoying overscan Control signal SCAN as reference for vertical positioning of OSD, PIP etc. Vertical noise reduction with memory Standard and doubled line frequencies for NTSC and PAL, MUSE standard, ATV standard, HDTV standard Self adaptation of V-frequency/number of lines per field between 192 and 680 for each possible line frequency Protection against EHT run away (X-rays protection) Type Ordering Code Package SDA 9361 Q67107-H5167-A703 P-MQFP-44-2 Semiconductor Group 5 1998-02-01 SDA 9361 • • • • • Protection against missing V-deflection (CRT-protection) Selectable softstart of the H-output stage Clock generation on chip P-MQFP-44-2 package 5 V supply voltage 1.2 General Description The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard or doubled line and field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/ west raster correction circuit. All adjustable output parameters are Ι2C Bus controlled. Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock system which includes the Φ1 and Φ2 control loops. Pin Configuration SELFH1_2 CLEXT FH1_2 TEST HD VSYNC PWM Φ2 VREFH VREFL VSS(A2) 1.3 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 CLKI X1 X2 SDAT SCLK RESN SCAN SCP VDD(D) VSS(D) VPROT VDD(A3) HSYNC VREFC VSS(A3) VDD(D) VSS(D) SSD VSS(A4) LF VDD(A4) VOFFD VDVD+ E/W VDD(A2) VREFP VREFN VSSA(1) ABL D/A VDDA(1) HPROT UEP10278 Figure 1 Semiconductor Group 6 1998-02-01 SDA 9361 1.4 Pin Description Pin No. Symbol Type Description 1 CLKI I/TTL Input for external clock 2 X1 I Reference oscillator input, crystal 3 X2 Q Reference oscillator output, crystal 4 SDAT IQ Ι2C-Bus data 5 SCLK I Ι2C-Bus clock 6 RESN I/TTL Reset input, active low 7 SCAN Q/TTL Control signal for vertical positioning of OSD, PIP etc. 8 SCP Q Blanking signal with H- and color burst component (V-component selectable by Ι2C Bus) 9 S Digital supply 10 VDD(D) VSS(D) S Digital ground 11 VPROT I Watching external V-output stage (input is the V-sawtooth from feedback resistor) 12 HPROT I Watching EHT (input is e.g. H-flyback) 13 VDD(A1) S Analog supply 14 D/A Q Output of an Ι2C Bus controlled DC voltage 15 ABL I Input for a beam current dependent signal for stabilization of width, height and H-phase 16 S Analog ground IQ Ground for VREFP, VREFH, VREFL 18 VSS(A1) VREFN VREFP IQ Reference voltage for IBEAM ADC, DAC, HPROT / VPROT thresholds 19 VDD(A2) S Analog supply 20 E/W Q Control signal output for east/west raster correction 21 VD+ Q Control signal output for DC coupled V-output stage 22 VD- Q Like VD+ 23 S Analog ground IQ Reference voltages for E/W-DAC, V-DAC IQ Like VREFL 26 VSS(A2) VREFL VREFH Φ2 I Line flyback for H-delay compensation 27 PWM Q/TTL Control signal output 17 24 25 Semiconductor Group 7 1998-02-01 SDA 9361 1.4 Pin Description (cont’d) Pin No. Symbol Type Description 28 VSYNC I/TTL V-sync input 29 HD Q Control signal output for H driver stage 30 TEST I/TTL Switching normal operation (TEST = L) and test mode (TEST = H: pins 7, 27, 31, 32, 33, 40, 44 are additional test pins) 31 FH1_2 I/TTL Switching between 1FH mode (L) and 2FH mode (H) (Pin SELFH1_2 = 0) 32 CLEXT I/TTL Switching between internal (L) and external clock (H)1) 33 SELFH1_2 I/TTL Selection of switching between 1FH mode and 2FH mode SELFH1_2 = 0:1FH/2FH selected via pin FH1_2 SELFH1_2 = 1:1FH/2FH selected via Ι2C-Bus register 00H, Bit D5 34 VDD(A3) S Analog supply 35 HSYNC I HSYNC input (CLEXT = 1: TTL; CLEXT = 0: analog)1) 36 I Reference voltage for sync ADC S Analog ground S Digital supply 39 VREFC VSS(A3) VDD(D) VSS(D) S Digital ground 40 SSD I/TTL Disables softstart 41 VSS(A4) S Analog ground 42 LF IQ PLL loop filter 43 VDD(A4) S Analog supply 44 VOFFD I/TTL Defines default value of VOFF-Bit (Ι2C-Bus register 00H, Bit D7) 37 38 1) The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency. Semiconductor Group 8 1998-02-01 SDA 9361 1.5 Block Diagram Φ2 SCP SCAN HPROT SSD VPROT SCLK SDAT VOFFD SELFH1_2 FH1_2 TEST CLEXT VSYNC HSYNC Protection Start Up Ι2C H-Out V-Out HD VD+ VD- Control CLL EW-Corr E/W PWM PWM D/A D/A CLKI PLL LF PW/PH Corr X1 X2 VREFC VREFL VREFH VREFP VREFN ABL UEB10277 Figure 2 Semiconductor Group 9 1998-02-01 SDA 9361 2 System Description 2.1 Functional Description The main input signals are HSYNC with standard or doubled horizontal frequency and VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz. The VSYNC is processed in a noise reduction circuit to enable synchronization by worse transmission too. The output signals control the horizontal as well as the vertical deflection stages and the east/west raster correction circuit. The H-output signal HD compensates the delays of the line output stage and its phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift is about 4.5 µs (for 1FH) or 2.25 µs (for 2FH). Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of the source signal. The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and can be disabled. Suitable blanking signals are delivered by the IC. The east/west output signal E/W is a vertical frequent parabola of 4th order, enabling an additional corner correction, separately for the upper and lower part. The pulse width modulated horizontal frequent output signal PWM is for optional use. It can be modulated between 1 and 215 steps. The step width is 4*tH/864. The output D/A delivers a variable DC signal for general purpose. The picture width and picture height compensation (PW/PH Comp) processes the beam current dependent input signal ABL with effect to the outputs E/W and VD to keep width and height constant and independent of brightness. The alignment parameter Horizontal Shift Compensation enables to adjust the influence of the input signal ABL on the horizontal phase. The selectable start up circuit controls the energy supply of the H-output stage during the receiver's run up time by smooth decreasing the line output transistors switching frequency down to the normal operating value (softstart). HD starts with about double the line frequency and converges within 85 ms to its final value. The high time is kept constant.The normal operating pulse ratio H/L is 45/55. The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the V-deflection fails (refer to page 46). HPROT: Input Semiconductor Group Vi < V2 Vi > V1 V2 ≤ Vi < V1 Continuous blanking HD disabled Operating range 10 1998-02-01 SDA 9361 VPROT: Vertical saw-tooth voltage Vi < V1 in first half of V-period or Vi > V2 in second half: HD disabled The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), Hblanking HBL (VHBL) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period can be varied by Ι2C Bus. For the timing following settings are possible: : tBL = 0 : tHBL = tf (H-flyback time) : tHBL = (4 * H-blanking-time + 1) / CLL : tDBL = (H-shift + 4 * H-blanking-phase -2 * H-blanking-time + 43) / CLL : tBL = tVBL during V-blanking period : tBL is always tHBL BD = 1 BD = 0, BSE = 0 (default value) BD = 0, BSE = 1(alignment range) SSC = 0 SSC = 1 Input Signal HSYNC t DB tB t DBL VOH VOHBL VOL t BL UED10260 Figure 3 BG-pulse width tB Delay to HSYNC tDB Semiconductor Group 54 / CLL if CLEXT = L-level: (76-4 * Internal-H-sync-phase) / CLL if CLEXT = H-level: (38-4 * Internal-H-sync-phase) / CLL 11 1998-02-01 SDA 9361 2.2 Circuit Description The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to the incoming horizontal sync pulse and exactly 864 times faster then the horizontal frequency. In order to lock the internal frequency to the external sync signal positive horizontal sync pulses are required (see figure 4). tr V HSmax V HSpp V HSmin tW UED10279 Figure 4 Incoming Signal HSYNC (CLEXT = 0) Pulse width tw for Ι2C-Bus Bit ’HSWID’ = 0: 3 µs ... 6.1 µs 1.5 µs ... 3.1 µs low FH-range high FH-range Pulse width tw for Ι2C-Bus Bit ’HSWID’ = 1: 3 µs ... 8.8 µs 1.5 µs ... 4.0 µs low FH-range high FH-range Rise time tr:100 ns minimum (CLEXT = 0) The described input signal is first applied to an A/D converter. Conversion takes place with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtain defined slopes for further measurements (PAL/NTSC applications). In addition the actual high and low level of the signal as well as a threshold value is evaluated and used to calculate the phase error between internal clock and external horizontal sync Semiconductor Group 12 1998-02-01 SDA 9361 pulse. By means of digital PI filtering an increment is gained from this. The PI filter can be set by the Ι2C-Bus VCR bit so that the lock-in behavior of the PLL is optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal frequency by means of 5 Ι2C-Bus bits (INCR4..INCR0) to different horizontal frequencies. An additional bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is controlled by the INCR bits. Once an increment has been obtained, either from the PI-filter or the Ι2C Bus, it can be used to operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is proportional to the increment. The saw-tooth is converted into a sinusoidal clock signal by means of sin ROM’s and D/A converters and applied to an analog PLL which multiplies the frequency by 2 or 4 (depends on mode 1FH or 2FH; for detailed explanation see pinning and Ι2C-Bus description) and minimizes residual jitter. In this manner the required line locked clock is provided to operate the other functional parts of the circuit. If no HSYNC is applied to pin 35 the system holds its momentary frequency for 2040 lines and following resets the PLL to its nominal frequency. The status bit CON indicates the lock state of the PLL. The system also provides a stable HS-pulse for internal use. The phase between this internal pulse and the external HSYNC is adjustable via Ι2C-Bus bits HPHASE. It can be shifted over the range of one TV line. An external clock (CLKI) can be provided by pin selection (CLEXT = H). The clock frequency has to be 864 * fHSYNC.The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency. For effective noise suppression the VSYNC has to pass a window at first and is then processed in a flywheel logic. The window allows a VSYNC pulse only after a minimum number of lines from its predecessor and sets an artificial one after a maximum number of lines. The number of H-periods between two subsequent VSYNCs is stored and determines (after several checks) the following V-periods (internal synchronization). If incoincidence is detected between internal and external VSYNC, the system switches after a hysteresis of a defined number of V-periods to external synchronization and the checks are repeated. Values which influence shape and amplitude of the output signals are transmitted as reduced binary values to the SDA 9361 via Ι2C Bus. A CPU which is designed for speed reasons in a pipe line structure calculates in consideration of feedback signals (e.g.ABL) values which exactly represent the output signals. These values control after D/A conversion the external deflection and raster correction circuits. The CPU firmware is stored in an internal ROM. Semiconductor Group 13 1998-02-01 SDA 9361 2.3 Reset Modes The circuit is completely reset at power-on/off (timing diagram see figure 11) or if the pin RESN has L-level (timing diagram see figure 12). During standby operation some parts of the circuit are not affected (timing diagram see figure 12): Power-On-Reset External Reset (pin RESN = Low) Standby Mode (I2C Bit STDBY = 1) HD output Low Low Active H-protection Inactive Inactive Inactive V-protection Inactive Inactive Inactive Ι2C interface (SDA, SCL) Tristate Tristate Ready Ι2C register 01H...1CH, 1FH Set to default values Set to default values Set to default values Ι2C register 00H, 1DH, 1EH, 44H...48H Set to default values Set to default values Not affected Status Bit PONRES Set to 11) Set to 11) Not affected VREFP, VREFH. VREFL Not affected Not affected Inactive CPU Inactive Inactive Inactive 1) Can only be read after Power-On-Reset is finished Note: Power-On-Reset and RESN = Low state are deactivated after ca. 32 cycles of the X1/X2 oscillator clock and ca. 42 cycles of the CLL clock. Standby state is deactivated after ca. 42 cycles of the CLL clock. Semiconductor Group 14 1998-02-01 SDA 9361 2.4 Frequency Ranges H V nL 15.625 kHz 50 Hz 625 I 15.75 kHz 60 Hz 525 I 31.25 kHz 50 Hz 100 Hz 625 NI / 1250I 625 I 31.5 kHz 60 Hz 70 Hz 120 Hz 525 NI / 1050 I 449 NI 525 I 32.4 kHz 60 Hz 1080 I 33.75 kHz1) 60 Hz 1125 I 35 kHz1) 66.7 Hz 525 NI 1) Only with internal clock generation The allowed deviation of all input line frequencies is max. ± 4.5 %. nL: I: NI: number of lines per frame interlaced non interlaced If NSA = 0 (subaddress 01H/D5H) number of lines per field is selfadaptable between 192 and 680 for each specified H-frequency. Semiconductor Group 15 1998-02-01 SDA 9361 2.5 I2C-Bus Control 2.5.1 I2C-Bus Address 1 0 0 0 1 1 0 2.5.2 I2C-Bus Format write: S 1 0 0 0 1 1 0 0 A Subaddress A Data Byte A ***** Status byte A Data Byte n A ***** A P read: S 1 0 0 0 1 1 0 1 A NA P Reading starts at the last write address n. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not Acknowledge An automatically address increment function is implemented. After switching on the IC, all bits are set to defined states. Semiconductor Group 16 1998-02-01 SDA 9361 Control item Subaddr. 2.5.3 I2C-Bus Commands Deflection control 0 Deflection control 1 Vertical shift Vertical size Vertical linearity Vertical S-correction Vertical EHT compensation 1) Horizontal size Pin phase Pin amp Upper corner pin correction Lower corner pin correction Horizontal EHT compensation 1) Horizontal shift Vertical angle Vertical bow PWM start D/A 1) Vertical blanking time 1) Horizontal blanking time Start vertical scan 1) Horizontal blanking phase Vertical scan width 0 1) Vertical scan width 1 1) Guard band 1) Start reduced scan 1) 00H 01H 02H 03H 04H 05H 06H D7 D6 D5 D4 D3 D2 D1 D0 Allowed Effective Can be Default Range Range Disabled Value if by Bit Disabled see below – – – – see below – – – – B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..255 – – 07H 08H 09H 0AH B7 B7 B7 B7 Vertical sync control Min. No. of lines / field 1) Max. No. of lines / field 1) AFC EHT compensation1) Internal PLL control Internal H-sync phase PWM width Universal register 1 Universal register 3 Internal voltage Ref control 1) – – – – – – – – – – – – 0BH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -128..127 – – – 0CH B7 B6 B5 B4 B3 B2 B1 B0 – – – B6 B7 B7 B7 B5 X X B7 B5 B5 B6 B6 B6 B4 B6 X B6 B4 B5 B5 B5 B5 B4 B5 B5 B5 B3 B5 B5 B5 B3 B4 B4 B4 B4 B3 B4 B4 B4 B2 B4 B4 B4 B2 B3 B3 B3 B3 B2 B3 B3 B3 B1 B3 B3 B3 B1 B2 B2 B2 B2 B1 B2 B2 B2 B0 B2 B2 B2 B0 B1 B1 B1 B1 B0 B1 B1 B1 X B1 B1 B1 B0 B0 B0 B0 X B0 B0 B0 X B0 B0 B0 15H B9 B8 16H B7 B6 B5 B4 B3 B2 B1 B0 17H X X B5 B4 B3 B2 B1 B0 18H X X B5 B4 B3 B2 B1 B0 -128..127 -128..127 -128..127 -128..127 – – – – – – – -128..127 -128..127 -128..127 -128..127 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H B6 B6 B6 B6 Unit 0..255 -64..63 -128..127 -128..127 0..255 -32..31 0..127 0..63 -128..127 -32..31 0..255 -64..63 – – -128..127 – – -128..127 – – 0..215 – – -32..31 – – a) BSE = 0 b) 0..63 BSE = 0 H-flyback c) SSE = 0 9 -32..31 – – 0..+3 0..255 0..63 0..63 d) d) 0..63 0, 2..63 see below – 19H 1AH B7 B6 B5 B4 B3 B2 B1 B0 0..255 1BH B7 B6 B5 B4 B3 B2 B1 B0 0..255 1CH B5 B4 B3 B2 B1 B0 X X -32..31 – 0..255 0..255 -32..31 see below – – 1DH 1EH B7 B6 B5 B4 B3 B2 B1 B0 -128..127 -96..119 1FH B7 B6 B5 B4 B3 B2 B1 B0 0..255 0..215 45H 47H 48H see below see below see below – – – – – – 1/CLL – – 4/CLL – lines 4/CLL line 4/CLL STE = 0 STE = 0 GBE = 0 SRSE = 0 – – – – e) e) 3 2 256 lines lines half lines line – – – – – 2 lines 2 lines – – – PWM width=0 – – – – – 15 – 4/CLL 4/CLL – – – – – – see 2.5.5: Explanation of some control items Semiconductor Group 17 1998-02-01 SDA 9361 a) The effective range for Vertical Blanking Time: 16 ... 127 (absolute value) if STE = 0 0 ... 127 (offset value) if STE = 1. b) The "default value if disabled" for Vertical Blanking Time: 21 (absolute value)if STE = 0 8 (offset value)if STE = 1. c) The effective range for Start Vertical Scan: 2 ... 127 (absolute value) -128 ... 127 (offset value) if STE = 0 if STE = 1 and NSA = 1 if STE = 1 and NSA = 0. d) The effective range for Vertical Scan (total width: 10 Bit): 160 ... 684 lines. e) The "default value if disabled" for Vertical Scan equals the number of lines of the source signal reduced by the control value for Start Vertical Scan. (E.g.: input signal: 262 lines per field; Start vertical scan = 8 lines; then (if SSE = 1, STE = 0) vertical scan = 262 - 8 = 254 lines. At power on the RAM containing the control items is cleared. Therefore all data are zero by default (if not otherwise defined) before transferring individual values via Ι2C Bus. Allowed values out of the effective range are limited, e. g. Vertical blanking time = 3 is limited to 16 if STE = 0 (that means a minimum of 16 lines is blanked). There are five bits (SRSE, BSE, SSE, STE, GBE) in the deflection control byte 1 for disabling some control items. If one of these bits is "0", the value of the corresponding control item will be ignored and replaced by the value "default value if disabled" in the table above. 2.5.4 Detailed Description The Deflection Control Byte 0 includes the following bits: VOFF VOFF: STDBY 2FH BD RABL VR1 VR0 HDE Vertical off 0: normal vertical output due to control items 1: vertical saw-tooth is switched off, vertical protection is disabled Default value depends on pin 44 (VOFFD) VOFFD = Low: 0 VOFFD = High: 1 Semiconductor Group 18 1998-02-01 SDA 9361 STDBY: Stand-by mode 0: normal operation 1: stand-by mode (all internal clocks are disabled) 2FH: Setting of line frequency 0: low range of line frequency (14900 Hz ... 17650 Hz) 1: high range of line frequency (29800 Hz ... 35300 Hz) Note: this bit is don’t care if pin SELFH1_2 has L-level BD: Blanking disable 0: horizontal and vertical blanking enabled 1: horizontal and vertical blanking disabled RABL: ABL input range 0: 2 V ... 3 V 1: 0 V ... 4 V VR1 ... VR0: Reduction of the vertical size 00: 100 % V-size (16:9 source on 16:9 display) 01: 75 % V-size (16:9 source on 4:3 display) 10: 66 % V-size (two 4:3 sources on 16:9 display) 11: 50 % V-size (two 16:9 sources on 16:9 display) HDE: HD enable 0: line is switched off (HD disabled, that is L-level) 1: line is switched on (HD enabled) Default value depends on pin 40 (SSD) SSD = Low: 0 SSD = High: 1 The Deflection Control Byte 1 includes the following bits: 0 NSA: X NSA STE GBE SRSE SSE BSE No self adaptation 0: self adaptation on 1: self adaptation off Semiconductor Group 19 1998-02-01 SDA 9361 STE: Scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 are enabled GBE: Guard band enable 0: control item for guard band is disabled 1: control item for guard band is enabled SRSE: Start reduced scan enable 0: control item for start reduced scan is disabled 1: control item for start reduced scan is enabled SSE: Start scan enable 0: control item for start vertical scan is disabled 1: control item for start vertical scan is enabled BSE: Blanking select enable 0: control items for blanking times are disabled 1: control items for blanking times are enabled The Vertical Sync Control Byte includes the following bits: X X SSC NR NI NL2 SSC: Sandcastle without VBL 0: output SCP with VBL component 1: output SCP without VBL component NR: Noise reduction 0: no noise reduction of the vertical sync 1: noise reduction of the vertical sync NI: Non interlace 0: interlace depends on source 1: no interlace Semiconductor Group 20 NL1 NL0 1998-02-01 SDA 9361 NL2 ... NL0: Number of lines per field when NR = 1 and no vertical sync at the input is detected NL2 NL1 NL0 Number of Lines per Field 0 0 0 262.5 0 0 1 312.5 0 1 0 525 0 1 1 562.5 1 X X 625 The Internal PLL Control Byte includes the following bits: HSWID GENMOD VCR INCR4 INCR3 INCR2 INCR1 INCR0 HSWID: Maximum width of HSYNC 0: 6.1 µs for low FH-range 3.1 µs for high FH-range 1: 8.8 µs for low FH-range 4.0 µs for high FH-range GENMOD: Clock generator mode 0: normal PLL mode 1: generator mode (fixed frequency output, controlled by INCR..) VCR: PLL filter optimized for 0: TV mode 1: VCR mode INCR4 ... 0: Nominal PLL output frequency for low FH-range: INCR = INT((FH * 110592) / FQ - 64.625) for high FH-range: INCR = INT((FH * 55296) / FQ - 64.625) (for typical values see table below) Semiconductor Group 21 1998-02-01 SDA 9361 specified range for: GENMOD = 0: 6 GENMOD = 1: 3 (FQ = 24.576 MHz) ≤ INCR ≤ 14 ≤ INCR ≤ 18 Application FH[Hz] INCR PAL 15625 6 NTSC 15750 6 PAL (100 Hz) 31250 6 NTSC (120 Hz) 31500 6 ATV 32400 8 MUSE 33750 11 Macintosh 35000 14 Default value: INCR = 6 Warning: 1)A change of INCR or 2FH causes spontaneous changes of the generated clock frequency greater than the specified 4.5 %. Switching from PLL mode to Generator mode (GENMOD) with constant INCR values does not result in exceeding the specified frequency deviation range. 2)If pin SSD has H-level the output signal HD starts immediately after power on. In this case the starting horizontal frequency is either 15.75 kHz (if SELFH1_2 has H-level or if SELFH1_2 and FH1_2 have L-level) or 31.5 kHz (if SELFH1_2 has L-level and FH1_2 H-level). Starting with Muse or Macintosh standard requires L-level at SSD so that INCR can be changed before enabling HD with HDE = 1. 3)Using external clock at pin 1, CLKI, (pin 32, CLEXT = 1): no internal protection against missing clock pulses is provided. 4)In order to guarantee error free operation of the build in soft start circuit the input frequency has to be inside the lock range of the PLL (+/-4.5 % of standard input frequency) Semiconductor Group 22 1998-02-01 SDA 9361 The Universal Register 1 (Subaddress 45H) includes the following bit: 0 NOISYVCR: 0 NOISY VCR 0 0 0 0 0 Handling of noisy input signals in VCR mode 0: normal handling 1: improved handling Note: this bit is don’t care if bit VCR = 0 (TV mode) The Universal Register 3 (Subaddress 47H) includes the following bits: 0 0 0 KILL_ZIP TC_3RD 0 KILL_ZIP: Top flutter suppression 0: no top flutter suppression 1: top flutter suppression (phase jumps max. ± 12 µs for low FH-range rsp. max. ± 6 µs for high FH-range) TC_3RD: Third time constant 0: slow VCR time constant 1: fast VCR time constant 0 0 Note: this bit is don’t care if bit VCR = 0 (TV mode) The Internal Voltage Ref. Control Byte includes the following bits: BANDG4 BANDG3 BANDG2 BANDG1 BANDG0 BANDG BANDG4 OFF OFF BANDG4 ... BANDG0: 0 Adjustment of internal bandgap reference 10000: Reference Output voltage min : 01111: Reference Output voltage max Typical adjustment range is 0.5 V. BANDGOFF: Bandgap Off 0: VREFH, VREFL derived internally from VREFP Semiconductor Group 23 1998-02-01 SDA 9361 1: external references on VREFP, VREFH, VREFL have to be applied (in this case BANDG4OFF must be = 1) BANDG4OFF: Bandgap 4 V Off 0: internal bandgap reference is used for VREFP 1: external reference on VREFP (4 V) has to be applied The Status Byte includes the following bits: HPON VPON CON - - - - PONRES HPON: protection on 0: normal operation of the line output stage 1: high level on input HPROT has switched off the line VPON: V-protection on 0: normal operation of the vertical output stage 1: incorrect signal on input VPROT has switched off the line CON: Coincidence not 0: H-coincidence detected 1: no H-coincidence detected PONRES: Power-On-Reset 0: after bus master has read the status byte 1: after each detected reset Note: PONRES is reset after this byte has been read. 2.5.5 Explanation of Some Control Items D/A This item controls directly a 6 Bit D/A Converter at the output D/A that can be used for general purpose. Start Vertical Scan If enabled (SSE = 1) this control item defines the start of calculation of the vertical sawtooth, the east/west parabola and the vertical function required for the vertical modulated output HD. Semiconductor Group 24 1998-02-01 SDA 9361 Vertical Scan (width0 and width1) The total width of this control item is 10 Bit. Therefore two registers (width0 and width1) are necessary. If enabled (STE = 1) it defines the duration of the vertical scan. When the vertical period has more lines than the sum of Start Vertical Scan and Vertical Scan, the calculation of the vertical saw-tooth, the east/west parabola and the vertical parabola required for HD stops so that the corresponding output signals remain unchanged till the next vertical synchron pulse. Guard Band This control item is useful for optimizing self adaptation. Video signals with different number of lines in consecutive fields (e. g. VCR search mode) must not start the procedure of self adaptation. But switching between different TV standards has to change the slope of the vertical saw-tooth getting always the same amplitude (self adaptation). To avoid problems with flicker free TV systems which have alternating number of lines per field an average value of four consecutive fields is calculated. If the deviation of these average values (e.g. PAL: 312.5 lines or 625 half lines) is less or equals Guard Band, no adaptation takes place. When it exceeds Guard Band, the vertical slope will be changed. Start Reduced Scan If enabled (SRSE = 1) this item defines the start of the D/A conversion of the calculated vertical saw-tooth. From begin of the vertical flyback to the line defined by Start Reduced Scan the output signals VD+, VD- remain unchanged (flyback level). Other outputs are not affected. a) control bits VR1, VR0 # 00 (reduction of vertical size) In this case the byte is useful for e.g. displaying 16/9 source format on 4/3 picture tubes without visible RGB lines generated of the automatic cut-off control (partial overscan). It defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the vertical saw-tooth (refer page 39). When Start Reduced Scan = 0 the reduction takes place over all lines including vertical flyback. b) control bits VR1, VR0 = 00 (no reduction of vertical size) If Start Reduced Scan > Start Vertical Scan the D/A conversion of the saw-tooth starts (Start Reduced Scan - Start Vertical Scan) lines after begin of the calculation. This causes a jump of the output voltage VD+, VD- from flyback to scan level. It may be useful to hide the automatic cut-off control lines if no overscan is desired (e.g. for VGA display). If Start Reduced Scan <= Start Vertical Scan this byte has no effect. Semiconductor Group 25 1998-02-01 SDA 9361 Vertical EHT Compensation This item controls the influence of the beam current dependent input signal ABL on the outputs VD+ and VD- according to the following equation: Vertical EHT compensation 1) ∆V VDPP = ∆V ABL * ------------------------------------------------------------------------ * 0,57 512 (if RABL = 0) Vertical EHT compensation 1) ∆V VDPP = ∆V ABL * ------------------------------------------------------------------------ * 0,57 2048 (if RABL = 1) ∆VVDPP: variation of VD+ and VD- peak-to-peak voltage ∆VABL: variation of ABL input voltage 1) The factor 0.57 depends on VREFP, VREFH, VREFL If Vertical EHT Compensation = 0 the outputs VD+ and VD- are independent of the input signal ABL. Horizontal EHT Compensation This item controls the influence of the input signal ABL on the output E/W according to the following equation: Horizontal EHT compensation 1) ∆V EW = ∆V ABL * ---------------------------------------------------------------------------------- * 2,12 128 (if RABL = 0) Horizontal EHT compensation 1) ∆V EW = ∆V ABL * ---------------------------------------------------------------------------------- * 2,12 512 (if RABL = 1) ∆VEW: variation of E/W output voltage ∆VABL: variation of ABL input voltage 1) The factor 2.12 depends on VREFP, VREFH, VREFL If Horizontal EHT Compensation = 0 the output E/W is independent of the input signal ABL. AFC EHT Compensation Deviation of the horizontal phase caused by high beam current (e.g. white bar) can be eliminated by this control item. The beam current dependent input signal ABL is multiplied by AFC EHT Compensation. Semiconductor Group 26 1998-02-01 SDA 9361 Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this product influences the horizontal phase at the output HD according to the following equation: 1) AFC EHT compensation 52 ∆φ = ∆V ABL * ---------------------------------------------------------------- * ----------CLL 64 1) AFC EHT compensation 52 ∆φ = ∆V ABL * ---------------------------------------------------------------- * ----------CLL 256 ∆φ ∆VABL CLL 1) (if RABL = 0) (if RABL = 1) :variation of horizontal phase at the output HD (positive values: shift left, negatives values: shift right) :variation of ABL input voltage (units: Volt) :864 * FH The factor 52 depends on VREFP Vertical Blanking Time (VBT) VBT defines the vertical blanking pulse VBL which is part of the output signal SCP. VBL is synchronized with the leading edge of HSYNC. It always starts and stops at the beginning of line and never in the center. a) Case of STE = 0 In this case the control item Vertical blanking time defines the duration of the V-blanking pulse (VBL) exactly in number of lines. Because of IC internal limitations 16 through 127 lines can be blanked. If BSE = 0 the control item Vertical blanking time is disabled and always 21 lines (default value if disabled) are blanked. After power on the control bit BSE is 0. Therefore 21 lines will be blanked before any programming of the IC. If Vertical Blanking Time is less or equals 21 lines, VBL starts (point A in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new even field) prior to the vertical flyback. Otherwise VBL is concentric to a fictitious vertical flyback period of 21 lines, that means VBL starts (VBT - 21) / 2 lines at the end of an odd field or (VBT - 20) / 2 at the end of an even field prior to point A. Possible start points are only the beginning of line. Semiconductor Group 27 1998-02-01 SDA 9361 1 2 1 Line 14 15 16 17 18 19 20 21 22 23 24 25 ~ ~ VSYNC ~ ~ HSYNC Start of even Field Start of odd Field ~ ~ VD- ~ ~ VBL (BSE = 0) 21 Lines ~ ~ VBL (BSE = 1, VBT = 16) 2 Lines 16 Lines 2 Lines ~ ~ VBL (BSE = 1, VBT = 25) 25 Lines 3 Lines ~ ~ VBL (BSE = 1, VBT = 26) 26 Lines UED10261 A Figure 5 Vertical Blanking Pulse VBL when STE = 0 and Number of Lines per Semiconductor Group 28 1998-02-01 SDA 9361 Field = Constant b) Case of STE = 1 In this case the control item Vertical blanking time is an extension for the V-blanking pulse. - If BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always at end of scan (line B in Fig. below) and ends at start of scan (line C) defined by the control items Start Vertical Scan (if SSE = 1) and Vertical Scan. - BSE = 1 and (128 > VBT > 0) extend the V-blanking pulse according to the following relationship (If VBT > 127 this value is ignored and replaced by VBT - 128): VBL starts VBT / 2 lines (even field) respectively (VBT + 1) / 2 lines (odd field) prior to line B. VBL ends (VBT + 1) / 2 lines (even field) respectively VBT / 2 lines (odd field) after end of line C. Possible start points are only the beginning of line. - If BSE = 0 (after power on) the control item Vertical Blanking Time is disabled and VBL starts 4 lines prior to end of scan (line B) and ends 4 lines after start of scan (line C). 2 1 Line Start of odd Field C Start of even Field ~ ~ VD- 3 ~ ~ ~ ~ VSYNC 1 ~ ~ B ~ ~ HSYNC Even 4 Lines 4 Lines ~ ~ ~ ~ ~ ~ VBL (BSE = 1, VBT = 0) ~ ~ VBL (BSE = 0) 3 Lines 3 Lines ~ ~ ~ ~ VBL (BSE = 1, VBT = 7) B C UED10262 Figure 6 Vertical Blanking Pulse VBL when STE = 1 Semiconductor Group 29 1998-02-01 SDA 9361 Minimum Number of Lines per Field It defines the minimum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than defined by Minimum Number of Lines per Field no synchronisation is possible.The relationship between Minimum Number of Lines per Field and the minimum number of lines is given in the following table: Minimum Number of Lines per Field Minimum Number of Lines per Field 0 192 1 194 ... ... 127 446 128 448 ... ... 254 700 255 702 Maximum Number of Lines per Field It defines the maximum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has more lines per field than defined by Maximum Number of Lines per Field no synchronisation is possible. The relationship between Maximum Number of Lines per Field and the maximum number of lines is given in the following table: Maximum Number of Lines per Field Maximum Number of Lines per Field 0 702 1 192 2 194 ... ... 127 444 128 446 ... ... 255 700 Semiconductor Group 30 1998-02-01 SDA 9361 Mode Most Important V-Deflection Modes for 4:3 CRT Description Characteristics Notes VR1 NSA SRSE GBE STE SSE VR0 N0 Normal mode (for 4:3 source, Letterbox) with default settings Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Mode after power on 00 0 0 0 0 0 N1 Normal mode (for 4:3 source, Letterbox) with user defined values Start of scan Self adaptation adjustable scan start = Start Vertical Scan if (Start Reduced Scan>Start Vertical Scan) start of start of V-ramp = Start Reduced Scan V-ramp adjustable else guard band start of V-ramp = Start Vertical Scan adjustable scan time: depends on source signal guard band = Guard Band/2 [lines] 00 0 1 1 0 1 S0 Shrink mode 75% (for 16:9 source) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 01 0 0 0 0 0 Start of scan Self adaptation S1 Shrink adjustable scan start = Start Vertical Scan mode 75% (for 16:9 source) if (Start Reduced Scan>Start Vertical Scan) start of reduced start of reduced V-ramp = with user V-ramp Start Reduced Scan defined values adjustable else guard band start of reduced V-ramp = adjustable Start Vertical Scan scan time: depends on source signal guard band = Guard Band/2 [lines] 01 0 1 1 0 1 Semiconductor Group 31 1998-02-01 SDA 9361 Mode Most Important V-Deflection Modes for 16:9 CRT Characteristics Notes VR1 NSA SRSE GBE STE SSE VR0 N0 Normal mode (for 16:9 or 4:3 source) with default settings Self adaptation scan start = line 9 start of V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines Mode after power on 00 0 0 0 0 0 N1 Normal mode (for 16:9 or 4:3 source) with user defined values Start of scan 00 Self adaptation adjustable scan start = Start Vertical Scan if (Start Reduced Scan>Start Vertical Scan) start of start of V-ramp = Start Reduced Scan V-ramp adjustable else guard band start of V-ramp = Start Vertical Scan adjustable scan time: depends on source signal guard band = Guard Band/2 [lines] 0 1 1 0 1 00 Zoom mode scan start = Vertical (for 4:3 source, (number_of_lines - Vertical Scan)/2 + 8 scan Letterbox) scan time = Vertical Scan controls zoom factor 0 X X 1 0 Like above; 00 Start vertical scan can be additionally used for adjustment of picture phase 0 X X 1 1 00 1 X X 1 X Z Description Scan start = SC Scroll mode (number_of_lines - Vertical Scan)/2 + 8 (for 4:3 source, + Start Vertical Scan Letterbox) scan time = Vertical Scan M Manual mode Scan start = Start Vertical Scan (for 4:3 source, scan time = Vertical Scan Letterbox) Scan start and scan time are separately adjustable S2 Shrink mode 66% (for two 4:3 sources) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band =1.5 lines 10 0 0 0 0 0 S3 Shrink mode 50% (for two 16:9 sources) with default settings Self adaptation scan start = line 9 start of reduced V-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 11 0 0 0 0 0 Semiconductor Group 32 1998-02-01 SDA 9361 3 Absolute Maximum Ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages Symbol TA Tstg Tj TS VI VQ VDD Supply total voltage differentials Total power dissipation Latch-up protection 1) Limit Values Unit min. max. -20 70 °C -40 125 °C 125 °C 260 °C Remark VSS - 0.3 V VDD + 0.3 V VSS - 0.3 V VDD + 0.3 V -0.3 6 V -0.25 0.25 V 0.85 W 100 mA Ptot -100 1) All inputs/outputs Between any internally non-connected supply pin of the same kind. All VDD(D) - and VDD(A) - Pins are connected internally by about 3 Ω The VSS(D)-Pins are connected internally by about 3 Ω Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. Semiconductor Group 33 1998-02-01 SDA 9361 3.1 Recommended Operating Conditions Parameter Symbol VDD Ambient temperature TA Supply voltages Limit Values Unit min. nom. max. 4.5 5 5.5 V -20 25 70 °C Remark For analog parameters: 0°C TTL Inputs: CLKI, VSYNC, TEST, FH1_2, SELFH1_2, CLEXT, SSD, VOFFD, RESN H-input voltage L-input voltage VIH VIL 2.0 VDD V 0 0.8 V Input VPROT VREFP = 4 V VREFP = 4 V Threshold V1 1.4 1.5 1.6 V Threshold V2 0.9 1.0 1.1 V Threshold V1 3.9 4 4.1 V Threshold V2 2.1 2.4 2.7 V VREFP = 4 V VREFP = 4 V V VREFP = 4 V Input HPROT Input ABL L-input voltage VIL 2 RABL = 0 Full range input voltage 0 V 3 V VREFP = 4 V RABL = 1 VREFP = 4 V RABL = 0 4 V VREFP = 4 V RABL = 1 Reference Voltage Input Pins (Internal Voltage Ref. Control Byte Reg 48H = 00000110) VREFP input voltage VREFH input voltage VREFL input voltage VREFN input voltage VREFC input voltage Semiconductor Group VVREFP VVREFH VVREFL VVREFN VVREFC 4 V 2.5 V 1.2 V 0 V 5 V 34 Independent of register 48H, max = VDD 1998-02-01 SDA 9361 3.1 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. nom. Unit Remark max. Input Φ2 L-input voltage H-input voltage VIL VIH 0 0.7 V 2.0 VDD V VREFP = 4 V VREFP = 4 V 2 VDD V See page 12 V See page 12 Input HSYNC (CLEXT = 0) VHSpp Input voltage low level VHSmin Input voltage high level VHSmax Pulse width tw Input voltage range 0 VDD See page 12 3.0 6.1 µs Low FH-range 1.5 3.1 µs High FH-range 3.0 8.8 µs Low FH-range 1.5 4.0 µs High FH-range (HSWID = 0) Pulse width (HSWID = 1) Rise time tw tr 100 ns Input HSYNC (CLEXT = 1) 0 0.8 V 2.0 VDD V Setup time VIL VIH tSU 4 ns Referred to falling edge of CLKI Hold time tH 12 ns Referred to falling edge of CLKI L-input voltage H-input voltage Input VSYNC Pulse width high 100 100/fH ns FH1_2 = 1, NI = 0 Pulse width high 200 100/fH ns FH1_2 = 0, NI = 0 Pulse width high 1.5/fH 100/fH NI = 1 Semiconductor Group 35 1998-02-01 SDA 9361 3.1 Recommended Operating Conditions (cont’d) Parameter Symbol Limit Values min. nom. Unit Remark max. Input CLKI (External Clock Generation, CLEXT = High) Input frequency fI 12.5 13.5 15 MHz Low FH-range 25 27 30 MHz High FH-range MHz Fundamental crystal type, e.g. Saronix 9922 520 00282 Quartz Oscillator Input / Output X1, X2 Crystal frequency 24.576 Crystal resonant impedance 40 External capacitance 27 Ω pF See Application information I2C Bus (All Values are Referred to min.(VIH) and max.(VIL) High-level input voltage VIH 3 VDD V Low-level input voltage VIL 0 1.5 V 0 400 kHz SCLK clock frequency fSCLK Rise times of SCLK, SDAT tR 0.3 µs Fall times of SCLK, SDAT tF 0.3 µs Set-up time DATA tSU;DAT tHD;DAT CL Hold time DATA Load capacitance Semiconductor Group 100 ns 0 ns 400 36 fSCLK = 400 kHz pF 1998-02-01 SDA 9361 3.2 Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Limit Values min. Average supply current ICC Unit nom. max. 90 150 mA 25 mA 0.4 V Stand-by supply current Remark Output Pins: SCAN, PWM Output low level Output high level VOL VOH V IO = 1 mA IO = -1 mA 0.6 V IO = 6 mA 1 V IO = 1 mA | IO | = 100 µA V IO = -1 mA 2.8 Input / Output SDAT Output low level VOL Output SCP Output low level Output HBL level Output high level VOL VOHBL VOH 0 VDD / 2 VDD / 2 VDD / 2 -0.4 V +0.4 V 4.0 VDD DAC Output D/A DAC resolution 6 Bit DAC output low 1 V DAC output high 3.953 V Load capacitance CL 30 VREFP = 4 V VREFP = 4 V pF kΩ Output load 20 Offset error -3 % 3% Gain error -3 % 3% INL -1 1 LSB DNL -0.5 0.5 LSB VREFP = 4 V VREFP = 4 V DAC Output E/W DAC resolution 10 Bit Linear range: 100 ... 900 DAC output low 1.45 V Input data = 1001) Semiconductor Group 37 1998-02-01 SDA 9361 3.2 Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Limit Values min. DAC output high Load capacitance nom. Remark V Input data = 9001) max. 3.48 CL Unit 30 pF kΩ Output load 20 Zero error -2 % 2% DAC output voltage = 2.5 V2) Gain error -5 % 5% 2) INL -0.2 % 0.2 % 2) DNL -0.1 % 0.1 % 2) 1) VREFH = 2.5 V, VREFL = 1.2 V 2) VREFH = 2.5 V, VREFL = 1.2 V, Input range = 100 ... 900 DAC Output VD+, VDDAC resolution 14 Bit Linear range: 1500 ... 15000 DAC output low (VD-) 1.44 V Input data = 15001) DAC output high (VD-) 3.58 V Input data = 150001) DAC output low (VD-) - (VD+) -2.12 V Input data = 15001) DAC output high (VD-) - (VD+) 2.16 V Input data = 150001) Load capacitance CL 30 pF kΩ Output load 20 Zero error -1 % 1% (VD-) - (VD+) = 0 V2) Gain error -5 % 5% 2) INL -0.5 % 0.5 % 2) DNL Monotonous 1) VREFH = 2.5 V, VREFL = 1.2 V 2) VREFH = 2.5 V, VREFL = 1.2 V, Input range = 1500 ... 15000 Semiconductor Group 38 Guaranteed by design 1998-02-01 SDA 9361 3.2 Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Limit Values min. nom. Unit Remark max. Reference Output VREFP (Adjustable by Reg 48H, Bit D7 ... D3) (Reg 48H, Bit D2 = 0, Bit D1 = 0) Output voltage min 4.0 Output voltage max Output current 4.0 IQ -50 V Bit D7 ... D3 = 10000 V Bit D7 ... D3 = 01111 0 µA 2.6 V VREFP = 4 V 1.3 V VREFP = 4 V V IO = 8 mA IO = -8 mA Reference Output VREFH (Reg 48H, Bit D2 = 0) Output voltage VQ 2.4 2.5 Reference Output VREFL (Reg 48H, Bit D2 = 0) Output voltage VQ 1.1 VOL VOH 0 1 VDD VDD 1.2 Output HD Output low level Output high level -1 V Semiconductor Group 39 1998-02-01 SDA 9361 4 Application Information VB SCP SCAN VPROT HPROT φ2 EHT ABL TV Contr. Ι2C + NVM H-Coil HD 27 pF X1 24.576 MHz SDA 9361 X2 E/W 27 pF + VSYNC VD- HSYNC VD+ + Source Sel Synch Sep _ LF V-Coil ABL D/A PWM RESN VPROT UES10280 Figure 7 Semiconductor Group 40 1998-02-01 SDA 9361 5 Waveforms 5.1 VD- Output Voltage, 4/3-CRT and 16/9-Source VVDV0(max) 1 V 16/9 2 V V0(min) 2 1 V 4/3 = 1 VV 16/9 2 0.75 2 V 63 SRS 0 SRSE = 1 n z (Line No.) Start Reduced Scan (SRS) selectable (line 0, 2...63) UED10264 Figure 8 Semiconductor Group 41 1998-02-01 SDA 9361 5.2 Timing Diagram of SCAN 1 2 1 2 3 8 ~ ~ HSYNC (even field) 3 ~ ~ HSYNC (odd field) 9 8 10 9 11 10 12 11 13 12 14 13 15 14 16 15 17 16 18 17 19 18 20 19 21 20 22 21 22 ~ ~ 2 * FH (internal) d0 ~ ~ VSYNC 21 Lines ~ ~ VBL (BSE = 0) appr. 1 Line + d0 1 Line VD(SSE = 0) Start of Scan ~ ~ appr. 8.5 Lines ~ ~ SCAN (SSE = 0) appr. 0.5 Lines appr. 11.5 Lines ~ ~ SCAN (SSE = 1, start vert. scan = 12) Start of Scan ~ ~ VD(SSE = 1, start vert. scan = 12) UED10281 Figure 9 Timing Diagram of SCAN if STE = 0 Semiconductor Group 42 1998-02-01 SDA 9361 2 2 3 ~ ~ ~ ~ 2 * FH (internal) 3 ~ ~ 1 ~ ~ HSYNC (even field) 1 ~ ~ ~ ~ HSYNC (odd field) d0 1 Line ~ ~ ~ ~ VSYNC ~ ~ End of Scan VD~ ~ ~ ~ ~ ~ VBL (BSE = 0) Start of Scan appr. 1 Line + d0 4 Lines appr. 0.5 Line + d0 5.5 Lines ~ ~ ~ ~ SCAN UED10282 Figure 10 Timing Diagram of SCAN if STE = 1 Semiconductor Group 43 1998-02-01 SDA 9361 5.3 Power On/Off Diagram Supply Voltage PowerOnReset 32 Cycles 32 Cycles X1, X2 SSD = 0: ~ 250 µs1) SSD = 1: ~ 380 µs1) SSD = 0: ~ 250 µ s1) SSD = 1: ~ 380 µ s1) HD Ι 2 C Registers 01 H ...1C H , 1F H Programmable Ι 2 C Bus Tristate Ι 2 C Registers 01 H ...1C H ,1F H Programmable Ready Tristate Programmable Default Ready Tristate VREFP , VREFH, VREFL Protection Ι 2 C Reg. 00 H, 1D H, 1E H, 44 H ... 48 H Active Inactive Default Ι 2 C Reg. 01H ...1C H , 1F H Default Programmable Default Programmable Programmable Default Default CLL ~ 42 Cycles CPU Active Inactive Power On 1) ~ 42 Cycles Glitch For low FH-range this time has to be multiplied by 2 Power Off UED10283 Figure 11 Semiconductor Group 44 1998-02-01 SDA 9361 5.4 Standby Mode, RESN Diagram Standby RESN HD φ 2-Loop 32 x 1 Cycles φ 2-Loop Free Run SSD = 0: ~ 250 µ s1) SSD = 1: ~ 380 µ s1) ~ 42 CLL Cycles Free Run ~ 42 CLL Cycles Active CPU VREFP , VREFH, VREFL Protection Inactive Active Inactive Active Inactive Ι 2 C Bus Ready Ι 2 C Reg. Programmable 01H ...1C H , 1F H Default Values Ι 2 C Reg. 00 H, 1D H, 1E H 44 H ... 48 H Programmable Tristate Programmable Default Values Programmable Programmable External Reset Standby Mode 1) Default Values Ready For low FH-range this time has to be multiplied by 2 UED10284 Figure 12 Semiconductor Group 45 1998-02-01 SDA 9361 5.5 Function of H,V Protection HPON2) I2C Bus VPON2) I2C Bus Continuous blanking 0 0 H, V operation 1) 0 0 3 EHT overvoltage Continuous blanking after t2 1 after t2 0 4 Continuous H operation blanking V short after t0 if failure SSC = 0 0 0 V longer failure H off after t1 Continuous blanking after t0 if SSC = 0 0 1 after t1 EHT short overvoltage Continuous blanking after t2 1 after t2 1 after t1 HPROT 1 2 VPROT V1 V2 Start up or V1 V2 or or t 0 < t <_ t 1 5 Mode or or t <t1 or 6 SCP t <t1 t0 = 2 / fv ... 3 / fv t1 = 64 / fv ... 128 / fv t2 = 1 / fv ... 2 / fv 1) Depends on 2C-control items Ι 2) HPON or VPON = 1:HD = 0 (OFF) Semiconductor Group 46 1998-02-01 SDA 9361 6 Package Outlines H 0.8 7˚ max. 0.15 +0.08 -0.02 2.45 max. 2 +0.1 -0.05 0.25 min. P-MQFP-44-2 (Plastic Metric Quad Flat Package) 0.88 ±0.15 0.3 +0.15 C 8 13.2 10 0.1 0.2 M A-B D C 44x 0.2 A-B D 44x 1) 0.2 A-B D H 4x D A 44 1 Index Marking 1) 13.2 10 1) B 0.6 x 45˚ Does not include plastic or metal protrusions of 0.25 max per side GPM05622 Figure 13 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group Dimensions in mm 47 1998-02-01