Wireless Components 10-pin Single PLL PMB 2341 Version 1.0 Specification February 2000 DS 1 Revision History: Current Version: 02.2000 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) 4-6 4-6 Programming of multifunctional output pin (MFO) is changed, i.e. MFO (open drain) is driven to ground for MFO bit equal to 1. ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstraße 73, 81541 München © Infineon Technologies AG i. Gr. 21.02.00. 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PMB 2341 preliminary Productinfo Confidential The PMB 2341 is a monolithic, low power, Package high performance phase-locked-loop (PLL) frequency synthesizer. It is primarily designed to be used for very stable low noise LO signals in mobile communication systems such as GSM, PCN (GSM 1800), PCS and PDC. The wide range of divider rations also allows application in modern analog systems. 3.0 General Description 5.0 Productinfo Max. high:1.2 Dimens. in mm 0.2 0.5 3.0 Features B6HFC BiCMOS technology 2.7 to 4.5 V operation Low operating power consumption Programmable power down modes High input sensitivity and high input frequencies up to 2.5 GHz Reference frequencies up to 100 MHz. Programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). Dividing ratios: A, N, R counter: 0 to 63, 3 to 4095, 3 to 4095, respectively Fast phase detector with switchable polarity charge pump output with programmable current and without dead zone Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs One multi-functional port Very small Mini-TSSOP-10 Package Ordering Information Type Ordering Code Mini-TSSOP-10 PMB 2341 Wireless Components Package Product Info Specification, February 2000 1 Table of Contents 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 2.1 2.2 2.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4 4.1 4.2 4.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Register, Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Typical Power-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Typical Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 RF Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 2 Product Description Contents of this Chapter 2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 PMB 2341 preliminary Product Description Confidential 2.1 Overview The PMB 2341 is a monolithic, low power, high performance phase-locked-loop (PLL) frequency synthesizer. It is primarily designed to be used for very stable low noise LO signals in mobile communication systems such as GSM, PCN (GSM 1800), PCS and PDC. The wide range of divider rations also allows application in modern analog systems. 2.2 Features B6HFC BiCMOS technology 2.7 to 4.5 V operation Low operating power consumption Programmable power down modes High input sensitivity and high input frequencies up to 2.5 GHz Reference frequencies up to 100 MHz. Programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). Dividing ratios: A, N, R counter: 0 to 63, 3 to 4095, 3 to 4095, respectively Fast phase detector with switchable polarity charge pump output with programmable current and without dead zone Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger inputs One multi-functional port Very small Mini-TSSOP-10 Package 0.5 0.1 A A 0.22 ±0.05 0.08 M 6 max. 0.42 +0.15 -0.1 ABC 4.9 3 ±0.1 C +0.08 0.125 -0.05 3 ±0.1 H 0.09 0.15 max. 0.85 ±0.1 1.1 max. 2.3 Package outline 0.25 M ABC B Index Marking Figure 2-1 Wireless Components Mini-TSSOP-10 2-2 Specification, February 2000 3 Functional Description Contents of this Chapter 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 3.4.1 3.4.2 3.4.3 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 PMB 2341 preliminary Functional Description Confidential 3.1 Pin Configuration VDD 1 10 RI CP 2 9 EN GND 3 8 DA LO 4 7 CLK VCC 5 6 M FO PM B 2341 Pin_config.wmf Figure 3-1 IC Pin Configuration 3.2 Pin Definition and Functions Pin No. Symbol Function 1 VDD 2 CP 3 GND 4 LO 5 VCC Analog / bipolar supply and Charge pump supply Used for bipolar prescaler, input buffer and chargepump Note: VDD and VCC must be equal! 6 MFO Multi-functional output (Open-drain) 7 CLK 3-Wire bus input: Clock Clock input of the serial control interface with CMOS Schmitt-Trigger input stage 8 DA 3-Wire bus input: Data Data input of the serial control interface withCMOS Schmitt-Trigger input stage.The serial data are read into the addressed internal shift register with the positive edge of CLK 9 EN 3-Wire bus input: Enable Enable input of serial control interface with CMOS Schmitt-Trigger input stage. When EN=H the input signals CLK and DA are disabled. When EN=L the serial control interface is enabled. The received data bits are transmitted into the addressed registers with the positive edge of EN 10 RI Reference frequency input Input with highly sensitive preamplifier. With small input signals AC coupling must be set up, whereas DC coupling can be used for large input signals Wireless Components Digital CMOS supply voltage. Note: VDD and VCC must be equal! PLL charge pump output Analog / bipolar ground, Charge pump ground and Digital CMOS ground (VSS) Used for bipolar prescaler, charge pump and Digital CMOS RF frequency input AC coupling is required. 3-2 Specification, February 2000 PMB 2341 preliminary Functional Description Confidential 3.3 Block diagram 1 10 R I_ sb y PLL VDD RI 1 2 B it R -C o u n te r D a ta & S h a d o w R e g iste r VCC 9 sync load 2 P h ase D ete cto r EN buf_en M FO GND 3 M od 6 4 /6 5 3 2 /3 3 GND pll_en CP 1 2 B it N -C o u n te r 6 B it A -C o u n te r D a ta & S h a d o w R e g iste r 8 S e ria l C o n tro l L o g ic Presc_sby M o d u lu s C o n tro l p ro g m o d e DA N T_ sb y p ll_ stb m o d p re sc 4 LO 7 C o n tro l re g iste r CLK cp p w 0 ,cp p w 1 pdpol p ll_ e n b u f_ e n 5 e n a b le lo g ic P re sc_ sb y R I_ sb y N T_ sb y 6 VCC M FO M FO Block_diag.wmf Figure 3-2 Wireless Components Main block diagram 3-3 Specification, February 2000 PMB 2341 preliminary Functional Description Confidential 3.4 Functional Blocks 3.4.1 General information The PMB2341 consists of a dual band single PLL. The device is designed to work in mobile communication systems and can handle VCO input frequencies up to 2.5 GHz. 3.4.2 PLL The PLL in the PMB 2341 consists of a high frequency bipolar configurable 32/33 or 64/ 65 dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with charge pump output with programmable output current drive capability. The counter and mode settings of the synthesizer are programmed via a serial 3-wire interface. The reference frequency is applied at the RI-input and divided by the PLL’s R-counter. Its maximum value is specified to be 100 MHz. The VCO’s RF input signal is divided by the bipolar prescaler with a programmable 32/33 or 64/65 divider ratio and the following programmable A/N-counters. For a wide range of divider ratios, both N and R counter can be programmed from 3 to 4095 . The phase and frequency detectors with the charge pumps have a linear operating range without dead zone for very small phase deviations. The operating modes allow the selection of 4 different charge pump output currents, polarity setting of the phase detector, 2 standby modes and the conrol of the multifunctional output port MFO. Wireless Components 3-4 Specification, February 2000 PMB 2341 preliminary Functional Description Confidential RI fR (RI:R) LO fV CP (LO:M) P-Channel Tri-State. N-Channel positive Polarity CP P-Channel Tri-State. N-Channel negative Polarity Frequency fV < fR fV lagging Figure 3-3 Frequency fV > fR fV leading Frequency fV = fR lock state Frequency detector output waveforms Frequency setting / divider ratio calculation: The frequency of an external VCO controlled by the PMB 2341 is given below: f RI M f VCO = [ ( P ⋅ N ) + A ] ⋅ ------- = ----- ⋅ f RI R R with . fVCO: fRI: N: A: P: R: M=P*N+A: frequency of the external VCO reference frequency divide ratio of the N-counter divide ratio of the A-swallow counter divide ratio of the prescaler (33 in case of 32/33 prescaler selected) divide ratio of the R-counter total divide ratio Note: for continuous frequency steps following condition is necessary [P ⋅ N + A] ≥ P ⋅ (P – 1) Further restrictions have to be fullfilled: A<P A≤N Wireless Components 3-5 Specification, February 2000 PMB 2341 preliminary Functional Description Confidential 3.4.3 Stand-by / power down conditions The PMB 2341 device has 2 different stand-by modes to reduce the power consumption. The standby modes allow separate power up and down modes for the PLL itself and for the RI input amplifier circuitry. The selection of a desired power-down mode is done by setting two bits ‘standby1’ and ’standby2’ located in the A/N-counter control word (see table 4-1: A/N counter data format). This enables a fast wake-up of the device and programming of a VCO-frequency with only one bus cycle! The encoding of the defined modes can be obtained from table 4-5: standby mode selection bits. Wireless Components 3-6 Specification, February 2000 4 Applications Contents of this Chapter 4.1 Programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Register, Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 Special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 PMB 2341 preliminary Applications Confidential 4.1 Programing General information: Programming of the IC is done via the 3 wire serial data interface consisting of a clock line, data line and an enable line. Data are shifted into the device with every rising CLK edge and are overtaken into internal registers with the rising edge of EN according to the schematic timing diagram shown in Figure 4-1. CLK DAT EN latch data into internal register Figure 4-1 Schematic bus signal timing Depending on the desired functional units to be programmed, several serial data formats exist. A common fact is that all multibit values are ordered in little endian notation in the bitstream meaning their MSB is sent first. Every bus cycle starts with the dedicated data bits followed by at least 1 register address bit and is terminated with two device address bits. In chapter 4.2 Register, Data format the available data formats are explained. The short control data format allows a fast PD-current change. The long control data format allows the programming of 4 different PD-output current modes for the PLL, polarity setting of the PD-output signals, 2 standby modes, test mode select and the prescaler divide ratio. The A/N-counter data format contains the A/N-counter values, the multifunctional output bit and standby mode switch bits. The R-counter data format contains the R-counter values and PLL programming mode switch bit. The PLL is programmed in an asynchronous mode: The serial data is written directly to the data registers of the addressed counter with the enable pulse. As each counter is loading the new starting value after it is decremented to „zero“, the counters changes therefore their counter values asynchronously to the others. Wireless Components 4-2 Specification, February 2000 PMB 2341 preliminary Applications Confidential 4.2 Register, Data format Note MSB of all serial data is shifted first! Table 4-1 A/N counter data format PLL Bit-Nr Bit Function caddr0 caddr1 chip address 1 1 raddr0 A/N register address 3 n0 N-counter 4 n1 5 n2 6 n3 7 n4 8 n5 9 n6 10 n7 11 n8 12 n9 13 n10 14 n11 15 standby1 PLL on/off 16 standby2 Ri input amp on/off 17 a0 A-counter 18 a1 19 a2 20 a3 21 a4 22 a5 23 MSB MFO LSB 0 1 0 2 multifunc. output port 2 (MFO) Table 4-2 Wireless Components 4-3 Specification, February 2000 PMB 2341 preliminary Applications Confidential Table 4-2 R counter data format PLL Bit-Nr Wireless Components Bit Function caddr0 chip address LSB 0 0 1 1 caddr1 2 0 raddr0 3 1 raddr1 4 r0 5 r1 6 r2 7 r3 8 r4 9 r5 10 r6 11 r7 12 r8 13 r9 14 r10 15 MSB r11 4-4 R register address R-counter Specification, February 2000 PMB 2341 preliminary Applications Confidential Table 4-3 Control data formats Long control data format PLL Bit-Nr Value Bit Function caddr0 chip address LSB 0 0 1 1 caddr1 2 0 raddr0 3 0 raddr1 4 1 raddr2 cpcurr2 6 cpcurr1 7 8 0 10 Value Bit Function caddr0 chip address 0 5 9 Short control data format PLL long control word address 1 caddr1 0 raddr0 0 raddr1 0 raddr2 short control word address charge pump current setting cpcurr2 cpcurrtst charge pump current test mode cpcurrtst presc prescaler division ratio n.a. required for correct operation pdpol phase detector polarity required for correct operation 11 0 n.a. 12 1 n.a. 13 mode2 14 mode1 15 not used 16 not used 17 not used 18 not used 19 not used charge pump current setting cpcurr1 charge pump current test mode test mode selection Table 4-4 Chip address bit Bits caddr1 1 Wireless Components Description caddr0 This chip address has to be sent to access the PMB2341 0 4-5 Specification, February 2000 PMB 2341 preliminary Applications Confidential Table 4-5 Standy mode selection bits Description Bits standby 1 standby 2 1 1 1 0 0 1 0 0 Remarks ALLRUN: PLL is powered on. not used: Enabling or disabling of certain identical to ALLrun. bipolar modules is done by turning AMPRUN: on or off its bias currents. PLL is powered off, only RI input preamplifier is powered on. ALLOPP: Both PLL and RI input preamplifier are powered off. Table 4-6 Port switching bits Bit MFO VALUE Description 1 Multifunctional output MFO is driven to ground (VSS) 0 Multifunctional output MFO is driven to VDD Table 4-7 Charge pump current programming bits cpcurr 1 Bits cpcurr 2 cpcurrtst CP Current [mA] I 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1.2 mA 2.0 mA 2.8 mA 4.0 mA 1.2 mA pump 1 1.2 mA pump 2 0.8 mA pump 1 0.8 mA pump 2 Remark Table 4-8 Prescaler mode select bit Bit presc Value Description 0 32/33 1 64/65 Table 4-9 Phase detector polarity select bit Bit pdpol Wireless Components Value Description 0 negative polarity 1 positive polarity 4-6 Specification, February 2000 PMB 2341 preliminary Applications Confidential Table 4-10 Test mode installation bits Control Bits mode 1 mode 2 1 1 0 1 1 0 0 0 Mode OPERATE: Normal operation of PLL and RI Buffer in installed mode. MFO pin has programmed level. not used: identical to OPERATE Testmode RCNTOUT: Charge pump is turned off. R-counter output at multifunctional MFO pin. Testmode NCNTOUT: Charge pump is turned off. N-counter output at multifunctional MFOMFO pin. 4.3 Special programming sequences Fast wake-up programming: When the circuit is connected to the supply voltage all registers are undefined. Due to the fact that each counter is loading its new start value after it is decremented to „zero“, the start-up time of the counters with the programmed values is too long for some applications. If the device has previously been set to ALLOFF- or AMPRUN-mode (see Table 5) afterwards is turned to operating mode ALLRUN, the counters are starting immediatly with the preprogrammed start values. Therefore for fast startup after standby the following data transfer sequence is recommended: Table 4-11 Fast Wake Up Data Transfer Sequence Wireless Components Step Serial Data Transfer Sequence 1 Long Control Word: ’OPERATE’ 2 Set A-/N-Counter: AMPRUN mode 3 Set R-Counter 4 Set A-/N-Counter, AMPRUN mode 5 Set A-/N-Counter, ALLRUN mode 4-7 Specification, February 2000 PMB 2341 preliminary Applications Confidential Wireless Components 4-8 Specification, February 2000 5 Reference Contents of this Chapter 5.1 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 Typical Power-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4 Typical Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.6 Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.7 RF Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 PMB 2341 preliminary Reference Confidential 5.1 Absolute Maximum Range The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, due to permanent damage to the device. Table 5-1 Absolute Maximum Ratings # Parameter Symbol Limit Values min max Units Remarks with respect to related ground. 1 CMOS Supply Voltage VDD_lim -0.3 5 V 2 Bipolar Supply Voltage VCC_lim -0.3 5 V 3 Difference between VCC and VDD levels |0.2| V 4 Applied voltage at pins CLK, DA, EN, RI,CP VInCMOS_lim -0.3 VDD + 0.3 V 5 Input voltage (LO) VI_Bip_lim -0.3 Vcc 0.8V V 6 Output current open-drain-stage (MFO) IO_OD 1 mA 7 Total power dissipation Ptot_lim t.b.d. mW 8 Ambient temperature TA -40 85 °C 9 Storage temperature Tstg -50 125 °C 10 ESD integrity VESD t.b.d. t.b.d. V VCC and VDD are intended to have the same level 5.2 Operational Range Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed. Table 5-2 Operating Ratings # Parameter Symbol Limit Values Units min max L Remarks 1 CMOS Supply Voltage VDD 2.7 4.5 V 2 Bipolar Supply Voltage VCC 2.7 4.5 V 3 Input VCO frequency at LO ƒLO 250 2500 MHz Prescaler set to 32/33 mode 4 Input VCO frequency at LO ƒLO 250 2500 MHz Prescaler set to 64/65mode 5 Input frequency at RI fRI 1 100 MHz 6 Output current open-drainstage (MFO) | IO_PP | 0.2 mA 7 CP-output current of PLL | IO_CP | 4 mA 8 CP-output voltages VO_CP 0.5 VCC0.5 V 9 Ambient temperature TA -40 85 °C Wireless Components 5-2 VCC and VDD are intended to have the same level Specification, February 2000 PMB 2341 preliminary Reference Confidential 5.3 Typical Power-On Time Time required to turn PLL and/or LO-buffer-chain frominstalled standby-mode to mode ALLRUN. Time is measured from time point when the ENable-signal is sent on 3-wire bus after programming the apropriate data bits. Table 5-3 Previously installed standby mode (see Table 5) Turn-ONtime Units Remarks AMPRUN t.b.d µs see Note 1) ALLOFF 1 µs NOTE 1: Only the turn-on time from PLL is measured, not the required lock-in time, which strongly depends on the loopfilter, etc. 5.4 Typical Supply current Table 5-4 Standby mode (see Table 5) CMOSSupply IDD Bipolar Supply ICC Units Test item ALLRUN 1.4 5.5 mA 1.1 ALLOFF 0 0 mA 1.2 Test condition see Note 1) Note 1) : Room temperature, All supplies set to 3.2V, TA = 27 °C, fRI = 13MHz, fLO = 1.2GHz, internal fref = 200KHz, PLL locked in mode ALLRUN, charge pump output current set to 4mA. No bus programming activities. Values may vary within 10%. Wireless Components 5-3 Specification, February 2000 PMB 2341 preliminary Reference Confidential 5.5 AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VCC , VDD, , VCP = 2.7V...4.5V, Ambient temperature Tamb = -40°C to 85°C except especially mentioned other values Table 5-5 AC/DC Characteristics # Symbol Limit Values min typ Units Test Item Test Conditions max Input Signals (Schmitt-Trigger) DA, CLK, EN when configured as input 1 H-input voltage VI_ST_H 1.5V VDD V 2.1 VDD ≤=3.5V 2 H-input voltage VI_ST_H 0.5 VDD VDD V 2.2 VDD =≥ 3.5V 3 L-input voltage VI_ST_L 0.5V V 2.3 VDD =≥ 2.7V 4 Input capacity CI_ST 5 pF 5 DC High-input current IST_H 0 5 µA 2.4 6 DC Low-input current IST_L 0 5 µA 2.5 *) guaranteed by design Output Signals MFO (open drain) 7 L-output voltage VO_OD_L 0.01 0.1V V 3.1 8 H-output current IO_OD_H 0 5 µA 3.2 IO_OD_L ≤=0.2mΑ Charge Pump Output Current IO_CP 9 "1.2 mA" | IO_CP | -20% 1.2 +20% mA 4.1 VCP = 3.2V, VO_CP = VCP/2 10 "2 mA" | IO_CP | -20% 2.0 +20% mA 4.2 11 "2.8 mA" | IO_CP | -20% 2.8 +20% mA 4.3 12 "4 mA" | IO_CP | -20% 4.0 +20% mA 4.4 13 "4 mA" | IO_CP | -20% 4.6 +20% mA 4.5 VCP = 4.5V 14 "Leakage Current" | IO_CP | 0.1 1*) nA 4.6 *) guaranteed by design 5.1 VO_CP = 0.5...VCP-0.5V mVrms 6.1 VDD = 2.7V, Note 1) dBm dBm 7.1 7.2 500 - 2500 MHz 250 - 500 MHz Output Tolerance IO_CP with variing voltage at pin CP 15 ∆IO_CP / IO_CP -10% Crystal Oscillator Input Signal RI 16 Input voltage at Ri VI_RI 100 VI_LO -20 -9 Input at LO; VCC=3.6 V 17 Input voltage at LO +4 +4 Note 1: fRI=4..30 MHz, VDD=3.6 V measured with PLL in mode RCNTOUT (see Table 4-10) at pin MFO. Wireless Components 5-4 Specification, February 2000 PMB 2341 preliminary Reference Confidential 5.6 Serial Control Data Format Timing tR tF ≈ tWHCL VIH CLK VIL ≈ VIL ≈ tDS VIH DA tCLE tECL VIH VIL ≈ EN ≈ ≈ tWHEN VIH PORT VIL tDEP Figure 5-1 Serial Control Data Format Timing Table 5-6 Symbol Limit Values min Units max Parameter Wireless Components Clock frequency ƒCLK H-pulsewidth (CLK) tWHCL 30 ns Data setup tDS 20 ns Setup time Clock-Enable tCLE 20 ns Setup time Enable-Clock tECL 20 ns H-pulsewidth (Enable) tWHEN 60 ns Rise, fall time tR , tR 10 µs Propagation delay time EN-PORT tDEP 1 µs 5-5 15 MHz Specification, February 2000 PMB 2341 preliminary Reference Confidential Input Power [dBm] 5.7 RF Input Sensitivity 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 3300 3050 2800 2550 2300 2050 1800 1550 1300 1050 800 550 300 50 Input Frequency [MHz] BASELINE Figure 5-2 TOPLINE RF Input Sensitivity Measured Prescler RF Sensitivity (Vcc=2.7V, 64/65 divider) Wireless Components 5-6 Specification, February 2000