HV2705 HV2706 Supertex inc. Low Harmonic Distortion, 16-Channel, High Voltage, Analog Switches with Bleed Resistors Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► HVCMOS technology for high performance Integrated bleed resistors on the outputs 16-channel high voltage analog switch 3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation (-10µA) Low parasitic capacitance DC to 50MHz small signal frequency response -60dB typical off-isolation at 5.0MHz CMOS logic circuitry for low power Low harmonic distortion Cascadable serial data register with latches Flexible operating supply voltages Applications ►► ►► ►► ►► Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Optical MEMS modules General Description The Supertex HV2705 and HV2706 are low charge injection, 16-channel, high voltage analog switch integrated circuits (ICs) with bleed resistors. The devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage build-up on capacitive loads such as piezoelectric transducers. The HV2706 has a different pin configuration than the HV2705. Input data are shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Latches D LE CLR DIN CLK 16-Bit Shift Register Level Shifters Output Switches SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW14 D LE CLR SW15 DOUT VDD GND Doc.# DSFP-HV2705_HV2706 B051512 LE CLR VNN VPP RGND Supertex inc. www.supertex.com HV2705 HV2706 Ordering Information / Availability Pin Configuration Part Number Package Option Packing HV2705FG-G 48-Lead LQFP 250/Tray HV2705FG-G M931 48-Lead LQFP 1000/Reel HV2706FG-G 48-Lead LQFP 250/Tray HV2706FG-G M931 48-Lead LQFP 1000/Reel 1 48 -G indicates package is RoHS compliant (‘Green’). 48-Lead LQFP (FG) (top view) Product Marking Top Marking Absolute Maximum Ratings YYWW Parameter Value VDD Logic supply -0.5V to +7.0V VPP-VNN differential supply 220V VPP Positive supply -0.5V to VNN+200V VNN Negative supply +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation: 48-Lead LQFP (FG) 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance HV2 7 0 5 FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or 48-Lead LQFP (FG) Top Marking YYWW HV2 7 0 6 FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or Package θja 48-Lead LQFP 52 C/W 48-Lead LQFP (FG) O Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak TA -40V to -160V VNN+10V to VPP-10V Operating free air temperature 0°C to 70°C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be within VNN and VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Doc.# DSFP-HV2705_HV2706 B051512 2 Supertex inc. www.supertex.com HV2705 HV2706 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) Sym Parameter 0°C +25°C +70°C Units Conditions Min Max Min Typ Max Min Max - 30 - 26 38 - 48 ISIG = 5.0mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5.0mA - 22 - 16 25 - 27 ISIG = 200mA Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch on-resistance - - - 15 - - - Ω VSIG= VPP -10V, ISIG = 1.0A RINT Value of output bleed resistor - - 20 35 50 - - kΩ Output Switch to RGND IRINT = 0.5mA ISOL Switch off leakage per switch* - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V and VNN +10V DC offset switch off* - 300 - 100 300 - 300 mV DC offset switch on* - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.5 - 5.5 RONS ∆RONS VOS IPP INN Small signal switch on-resistance Average VPP supply current Average VNN supply current Ω VPP = +40V VNN = -160V ISIG = 5.0mA VPP = +100V VNN = -100V ISIG = 200mA VPP = +160V VNN = -40V No Load Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V - 4.0 - - 5.0 - 5.5 VPP = +160V VNN = -40V - 6.5 - - 7.0 - 8.0 VPP = +40V VNN = -160V - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 mA All output switches are turning ON and OFF at 50kHz with no load. VPP = +100V VNN = -100V VPP = +160V VNN= -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD-0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- * See Test Circuits on page 5 Doc.# DSFP-HV2705_HV2706 B051512 3 Supertex inc. www.supertex.com HV2705 HV2706 AC Electrical Characteristics (over recommended operating conditions, VDD= 5.0V, tR = tF ≤ 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted) Sym Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCLR Time width of CLR tSU Set up time data to clock tH Hold time data from clock fCLK Clock frequency tR,tF 0°C +25°C +70°C Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - - 56 - 56 - 12 - - 12 - 12 - 50 100 50 78 100 50 100 15 40 15 30 40 15 40 55 - 55 - - 55 - 21 - - 21 - 21 - 7.0 - - 7.0 - 7.0 - 2.0 - 2.0 - - 2.0 - - 8.0 - - 8.0 - 8.0 Units ns ns ns ns ns ns Conditions --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD= 5.0V --VDD= 3.0V VDD= 5.0V VDD= 3.0 or 5.0V VDD= 3.0V - 20 - - 20 - 20 MHz Clock rise and fall times - 50 - - 50 - 50 ns ---- TON Turn ON time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ TOFF Turn OFF time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 - - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND - 15 - 10 15 - 15 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND - 18 - 13 18 - 18 pF 0V, f = 1.0MHz - - - - 150 - - - - - - 150 - - - - - - 150 - - VPP = +160V, VNN = -40V, RLOAD = 50Ω - - - 820 - - - VPP= +40V, VNN= -160V, VSIG= 0V - - - 600 - - - - - - 350 - - - dv/dt Maximum VSIG slew rate KO Off isolation* KCR Switch crosstalk* IID +VSPK -VSPK +VSPK -VSPK Output voltage spike* +VSPK -VSPK QC Charge injection* VDD= 5.0V VPP = +40V, VNN = -160V v/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1kΩ//15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V, RLOAD = 50Ω mV pC VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP= +100V, VNN= -100V, VSIG= 0V VPP= +160V, VNN= -40V, VSIG= 0V * See Test Circuits on page 5 Doc.# DSFP-HV2705_HV2706 B051512 4 Supertex inc. www.supertex.com HV2705 HV2706 HV2705/HV2706 Test Circuits VPP -10V VPP -10V ISOL RLOAD 10kΩ VOUT VOUT Open Open RGND RGND VPP VPP VDD VNN VNN GND 5V RGND VPP VPP VDD VNN VNN GND Switch Off Leakage per Switch 5V VPP VPP VDD VNN VNN GND TON/TOFF Test Circuit DC Offset Switch ON/OFF (for HV2705 only) 5V VIN = 10VP-P @5MHz VIN = 10VP-P @5MHz VSIG IID VOUT VNN RLOAD 50Ω RGND RGND VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND VOUT KCR = 20Log VIN 50Ω RGND VPP Output Switch Isolation Diode Current OFF Isolation 5V VOUT VIN Switch Crosstalk +VSPK ΔVOUT VOUT –VSPK 1000pF VOUT RLOAD VSIG RGND 50Ω RGND 1kΩ VPP VPP VDD VNN VNN GND 5V Q = 1000pF x ΔVOUT Charge Injection Doc.# DSFP-HV2705_HV2706 B051512 NC VPP VPP VDD VNN VNN GND 5V Output Voltage Spike 5 Supertex inc. www.supertex.com HV2705 HV2706 Logic Function Table D0 D1 L ... D7 D8 - - H - - L - D15 LE CLR SW0 SW1 SW7 SW8 - - L L OFF - - - - - - - L L - - - L L ON - - - - - OFF - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L L - - - - - - - L - - L L - - OFF - - - - H - - L L - - ON - - - - L - L L - - - OFF - - - H - L L - - - ON - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF ... ... ... ... ... ... ... SW15 - Notes: 1. The 16 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the shift register 15 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN - 1 DN DN + 1 DATA IN DIN 5 0% LE 50% 50% 50% tWLE tSD 50% CLOCK 50% th tSU tDO DATA OUT DOUT VOUT 50% tON tOFF OFF 90% (typ) 1 0% ON CLR Doc.# DSFP-HV2705_HV2706 B051512 5 0% 5 0% tWCL 6 Supertex inc. www.supertex.com HV2705 HV2706 HV2705 Pin Description 48-Lead LQFP (FG) Pin # Function Pin # Function Pin # Function Pin # Function 1 NC 13 VNN 25 SW15B 37 SW10B 2 NC 14 NC 26 SW15A 38 SW10A 3 SW4B 15 VPP 27 SW14B 39 SW9B 4 SW4A 16 NC 28 SW14A 40 SW9A 5 SW3B 17 GND 29 SW13B 41 SW8B 6 SW3A 18 VDD 30 SW13A 42 SW8A 7 SW2B 19 DIN 31 SW12B 43 SW7B 8 SW2A 20 CLK 32 SW12A 44 SW7A 9 SW1B 21 LE 33 SW11B 45 SW6B 10 SW1A 22 CLR 34 SW11A 46 SW6A 11 SW0B 23 DOUT 35 NC 47 SW5B 12 SW0A 24 RGND 36 NC 48 SW5A HV2706 Pin Description 48-Lead LQFP (FG) Pin # Function Pin # Function Pin # Function Pin # Function 1 NC 13 VNN 25 SW15B 37 SW10B 2 NC 14 NC 26 SW15A 38 SW10A 3 SW4B 15 VPP 27 SW14B 39 SW9B 4 SW4A 16 NC 28 SW14A 40 SW9A 5 SW3B 17 GND, RGND 29 SW13B 41 SW8B 6 SW3A 18 VDD 30 SW13A 42 SW8A 7 SW2B 19 DIN 31 SW12B 43 SW7B 8 SW2A 20 CLK 32 SW12A 44 SW7A 9 SW1B 21 LE 33 SW11B 45 SW6B 10 SW1A 22 CLR 34 SW11A 46 SW6A 11 SW0B 23 DOUT 35 NC 47 SW5B 12 SW0A 24 NC 36 NC 48 SW5A Doc.# DSFP-HV2705_HV2706 B051512 7 Supertex inc. www.supertex.com HV2705 HV2706 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View L2 View B A A2 L Seating Plane Side View A1 θ L1 Gauge Plane Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC θ 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV2705_HV2706 B051512 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com