HV2761 DATA SHEET (06/22/2014) DOWNLOAD

Supertex inc.
HV2761
Low Charge Injection, 24-Channel,
High Voltage Analog Switch with Bleed Resistors
Features
General Description
Applications
Input data is shifted into a 24-bit shift register that can then be
retained in a 24-bit latch. To reduce any possible clock feed through
noise, the latch enable (LE) should be left high until all bits are
clocked in. Data are clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
►►
24-channel high voltage analog switch
Integrated bleed resistors on the outputs
3.3 or 5.0V CMOS input logic level
3:1 MUX-deMUX with 8 states
20MHz data shift clock frequency
HVCMOS technology for high performance
Very low quiescent power dissipation,10µA
Low parasitic capacitance
DC to 50MHz analog signal frequency
-60dB typical OFF-isolation at 5.0MHz
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
Medical ultrasound imaging
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
The Supertex HV2761 is a low charge injection, 24-channel,
high voltage analog switch integrated circuit (IC) intended for
use in applications requiring high voltage switching controlled by
low voltage control signals, such as medical ultrasound imaging,
piezoelectric transducer drivers, and printers. The bleed resistors
eliminate voltage built up on capacitive loads such as piezoelectric
transducers.
The device is suitable for various combinations of high voltage
supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V.
Block Diagram
Latches
D
LE
CLR
CLK
DIN
24-Bit
Shift
Register
DOUT
VDD GND
Doc.# DSFP-HV2761
NR010913
LE CLR
Level
Shifters
Output
Switches
SW0
D
LE
CLR
SW1
D
LE
CLR
SW2
D
LE
CLR
SW3
D
LE
CLR
SW4
D
LE
CLR
SW5
D
LE
CLR
SW21
D
LE
CLR
SW22
D
LE
CLR
SW23
Y0
Y1
Y7
VNN VPP
RGND
Supertex inc.
www.supertex.com
HV2761
Pin Configuration
Ordering Information
Part Number
Package
Packing
HV2761FG-G
48-Lead LQFP
250/Tray
HV2761FG-G M931 48-Lead LQFP
1
48
1000/Reel
-G indicates package is RoHS compliant (‘Green’)
48-Lead LQFP
Absolute Maximum Ratings
(top view)
Parameter
Value
VDD logic supply
-0.5V to +6.5V
VPP - VNN differential supply
VPP positive supply
220V
Product Marking
Top Marking
YYWW
-0.5V to VNN + 200V
VNN negative supply
+0.5V to - 200V
Logic input voltage
-0.5V to VDD + 0.3V
Analog signal range
VNN to VPP
Peak analog signal current/channel
Storage temperature
3.0A
-65°C to 150°C
Power dissipation
H V 2761FG
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
*May be part of top marking
Package may or may not include the following marks: Si or
48-Lead LQFP
1.0W
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
Typical Thermal Resistance
Package
θja
48-Lead LQFP
52OC/W
Recommended Operating Conditions
Sym
Parameter
Value
VDD
Logic power supply voltage
3.0V to 5.5V
VPP
Positive high voltage supply
+40V to VNN + 200V
VNN
Negative high voltage supply
-40V to - 160V
VIH
High level input voltage
0.9VDD to VDD
VIL
Low level input voltage
0V to 0.1VDD
VSIG
Analog signal voltage peak-to-peak
VNN +10V to VPP - 10V
Operating free air temperature
0OC to 70OC
TA
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition.
3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
Doc.# DSFP-HV2761
NR010913
2
Supertex inc.
www.supertex.com
HV2761
DC Electrical Characteristics (Over recommended operating conditions unless otherwise specified )
Sym
Parameter
0OC
+25OC
+70OC
Unit Conditions
Min
Max
Min
Typ
Max
Min
Max
-
-
-
26
-
-
-
-
-
-
22
-
-
-
-
-
-
22
-
-
-
-
-
-
18
-
-
-
-
-
-
20
-
-
-
-
-
-
16
-
-
-
Small signal switch
ON-resistance matching
-
20
-
5.0
20
-
20
%
RONL
Large signal switch
ON-resistance
ISIG = 5.0mA,
VPP = +100V, VNN = -100V
-
-
-
30
-
-
-
Ω
VSIG = VPP - 10V, ISIG = 1.0A
RINT
Output switch shunt resistance
-
-
20
35
50
-
-
KΩ
Output switch to RGND
IRINT = 0.5mA
ISOL
Switch OFF-leakage per switch
-
5.0
-
1.0
10
-
15
μA
VSIG = VPP - 10V, VNN +10V
DC offset switch OFF
-
300
-
100
300
-
300
DC offset switch ON
-
500
-
100
500
-
500
mV
No load
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
μA
All switches OFF
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
μA
All switches ON,
ISW = 5.0mA
ISW
Switch output peak current
-
-
-
2.0
1.3
-
-
A
VSIG duty cycle < 0.1%
fSW
Output switching frequency
-
-
-
-
50
-
-
kHz
Duty cycle = 50%
-
4.0
-
-
4.5
-
5.0
-
4.0
-
-
4.5
-
5.0
mA
-
4.0
-
-
4.5
-
5.0
VPP= +40V, All output
VNN = -160V switches are
VPP= +100V, turning ON
VNN = -100V and OFF at
VPP= +160V, 50kHz with
no load
V = -40V
mA
VPP = +40V, All output
VNN = -160V switches are
VPP= +100V, turning ON
VNN = -100V and OFF at
VPP= +160V, 50kHz with
no load
V = -40V
RONS
ΔRONS
VOS
IPP
Small signal switch
ON-resistance
Average VPP supply current
ISIG = 5.0mA
VPP = +40V,
ISIG = 200mA VNN = -160V
Ω
ISIG = 5.0mA
VPP = +100V,
ISIG = 200mA VNN = -100V
ISIG = 5.0mA
VPP = +160V,
ISIG = 200mA VNN = -40V
NN
INN
Average VNN supply current
-
4.0
-
-
4.5
-
5.0
-
4.0
-
-
4.5
-
5.0
-
4.0
-
-
4.5
-
5.0
NN
IDD
Average VDD supply current
-
8.0
-
-
8.0
-
8.0
mA
fCLK = 5.0MHz, VDD = 5.0V
IDDQ
Quiescent VDD supply current
-
10
-
-
10
-
10
μA
All logic inputs are static
ISOR
Data out source current
0.45
-
0.45 0.70
-
0.40
mA
VOUT = VDD - 0.7V
ISINK
Data out sink current
0.45
-
0.45 0.70
-
0.40
mA
VOUT = 0.7V
CIN
Logic input capacitance
-
10
10
-
pF
---
-
-
10
* See Test Circuits on page 5
Doc.# DSFP-HV2761
NR010913
3
Supertex inc.
www.supertex.com
HV2761
AC Electrical Characteristics (Over recommended operating conditions unless otherwise specified)
Sym
Parameter
tSD
Set up time before LE rises
tWLE
Time width of LE
tDO
Clock delay time to data out
tWCLR
Time width of CLR
tSU
Set up time data to clock
tH
Hold time data from clock
0OC
+25OC
+70OC
Min
Max
Min
Typ
Max
Min
Max
25
-
25
-
-
25
-
56
-
-
56
-
56
-
12
-
-
12
-
12
-
25
100
25
78
100
25
100
15
40
15
30
40
15
40
55
-
55
-
-
55
-
21
-
21
-
-
21
-
7.0
-
7.0
-
-
7.0
-
5.0
-
5.0
-
-
5.0
-
7.0
-
7.0
-
-
7.0
-
-
8
-
-
8
-
8
-
20
-
-
20
-
20
Unit
ns
ns
ns
ns
ns
ns
Conditions
--VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
--VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
fCLK
Clock frequency
tR, tF
Clock rise and fall times
-
50
-
-
50
-
50
tON
Turn ON time
-
5.0
-
-
5.0
-
5.0
tOFF
Turn OFF time
-
5.0
-
-
5.0
-
5.0
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-30
-
-30
-33
-
-30
-
-58
-
-58
-60
-
-58
-
-60
-
-60
-70
-
-60
-
dB
f = 5.0MHz, 50Ω load
Output switch isolation diode
current
-
300
-
-
300
-
300
mA
300ns pulse width,
2.0% duty cycle
OFF capacitance SW to GND
-
14
-
9.0
14
-
14
OFF capacitance Y to GND
-
35
-
27
35
-
35
pF
VSIG = 0V, f = 1.0MHz
all SW OFF
ON capacitance SW to GND
-
39
-
30
39
-
39
ON capacitance Y to GND
-
39
-
30
39
-
39
pF
VSIG = 0V, f = 1.0MHz
one SW ON, two SW OFF
+VSPK
-
-
-
-
150
-
-
-VSPK
-
-
-
-
150
-
-
-
-
-
-
150
-
-
-
-
-
-
150
-
-
+VSPK
-
-
-
-
150
-
-
-VSPK
-
-
-
-
150
-
-
dv/dt
Maximum VSIG slew rate
KO
OFF isolation
KCR
Switch crosstalk
IID
CSG(OFF)
CSG(ON)
+VSPK
-VSPK
Output voltage spike
(per switch)
MHz
VDD = 5.0V
ns
---
μs
VSIG = VPP - 10V,
RLOAD = 10kΩ
VPP = +40V, VNN = -160V
V/ns
VPP = +100V, VNN = -100V
VPP = +160V, VNN = -40V
dB
f = 5.0MHz,
1.0kΩ//15pF load
f = 5.0MHz, 50Ω load
VPP = +40V, VNN = -160V
RLOAD = 50Ω
mV
VPP = +100V, VNN = -100V
RLOAD = 50Ω
VPP = +160V, VNN = -40V
RLOAD = 50Ω
* See Test Circuits on page 5
Doc.# DSFP-HV2761
NR010913
4
Supertex inc.
www.supertex.com
HV2761
AC Electrical Characteristics (cont.) (Over recommended operating conditions unless otherwise specified)
Sym
QC
0OC
Parameter
Charge injection
(per switch)
+25OC
+70OC
Min
Max
Min
Typ
Max
Min
Max
-
-
-
820
-
-
-
-
-
-
600
-
-
-
-
-
-
350
-
-
-
Unit
Conditions
VPP = +40V, VNN = -160V
pC
VPP = +100V, VNN = -100V
VPP = +160V, VNN = -40V
Test Circuits
ISOL
VPP -10V
NC
SW0
SW1
Y0
SW2
NC
VOUT
NC
RGND
NC
VPP
VDD
VNN
VNN
GND
5.0V
Y0
SW2
VPP -10V
SW0
RLOAD
10kΩ
VOUT
NC
NC
SW0
SW1
Y0
SW2
VSIG
VPP
VDD
VNN
VNN
GND
NC
SW0
IID
50Ω
NC
5.0V
RGND
VPP
VPP
VDD
VNN
VNN
GND
SW1
NC
NC
50Ω
SW2
VOUT
VNN
VPP
VNN
KO = 20Log
VDD
VPP
5.0V
1000pF
Y0
VPP
VNN
GND
VDD
VNN
5.0V
Y0
SW2
SW3
SW4
SW5
Y1
GND
VPP
VPP
VDD
VNN
VNN
GND
KCR = 20Log
VIN
SW1
SW2
NC
VOUT
NC
VPP
VPP
VDD
VNN
GND
+VSPK
Y0
RL
1kΩ
5.0V
SW0
NC
-VSPK 50Ω
RGND
VNN
SW1
SW0
VIN = 10VP-P
@5.0MHz
NC
NC
NC
SW2
NC
RGND
VPP
VPP
VDD
VNN
VNN
GND
5.0V
VOUT
VIN
Crosstalk
Isolation Diode Current
+VSPK
5.0V
RGND
VOUT
ΔVOUT
VOUT
SW1
NC
OFF Isolation
SW0
SW0
50Ω
NC
RGND
VPP
NC
TON/TOFF Test Circuit
VNN
Y0
NC
SW2
Y0
DC Offset ON/OFF
NC
SW1
RGND
VPP
Switch OFF Leakage
VOUT
SW1
RGND
VPP
VIN = 10VP-P
@5.0MHz
SW0
5.0V
-VSPK
RL
1kΩ
VOUT
Y0
50Ω
SW1
SW2
NC
NC
RGND
VPP
VPP
VDD
VNN
VNN
GND
5.0V
Q = 1000pF • ∆VOUT
Charge Injection
Doc.# DSFP-HV2761
NR010913
Output Voltage Spike SW
5
Output Voltage Spike Y
Supertex inc.
www.supertex.com
HV2761
Truth Table
D0
D1
L
...
D15
D16
-
-
H
-
-
D23
LE
CLR
SW0
SW1
SW15
SW16
-
-
L
L
OFF
-
-
-
-
-
-
-
L
L
ON
-
-
-
-
L
-
-
-
L
L
-
OFF
-
-
-
-
H
-
-
-
L
L
-
ON
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
-
-
L
L
-
-
-
-
-
-
-
L
L
-
-
OFF
-
-
-
-
H
-
-
L
L
-
-
ON
-
-
-
-
L
-
L
L
-
-
-
OFF
-
-
-
H
-
L
L
-
-
-
ON
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
-
L
L
-
-
-
-
-
-
-
-
-
L
L
L
-
-
-
-
OFF
-
-
-
-
H
L
L
-
-
-
-
ON
...
...
...
...
...
X
X
X
X
X
X
X
H
L
HOLD PREVIOUS STATE
X
X
X
X
X
X
X
X
H
ALL SWITCHES OFF
...
...
SW23
-
Notes:
1. The 24 switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch.
4. DOUT is high when data in the register 23 is high.
5. Shift registers clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN + 1
DN
DATA IN
DIN
5 0%
LE
50%
DN - 1
50%
50%
tWLE
tSD
50%
CLOCK
tSU
DATA OUT
DOUT
VOUT
(typ)
th
tDO
50%
tON
tOFF
OFF
90%
1 0%
ON
CLR
Doc.# DSFP-HV2761
NR010913
50%
5 0%
tWCL
5 0%
6
Supertex inc.
www.supertex.com
HV2761
Pin Function
Pin
Function
Pin
Function
Pin
Function
Pin
Function
1
VPP
13
SW0
25
VPP
37
SW15
2
NC
14
Y0
26
RGND
38
SW16
3
GND
15
SW1
27
SW9
39
Y5
4
CLR
16
SW2
28
Y3
40
SW17
5
LE
17
SW3
29
SW10
41
SW18
6
CLK
18
Y1
30
SW11
42
SW19
7
VDD
19
SW4
31
SW12
43
Y6
8
GND
20
SW5
32
SW13
44
SW20
9
DIN
21
SW6
33
Y4
45
SW21
10
DOUT
22
Y2
34
SW14
46
SW22
11
NC
23
SW7
35
RGND
47
Y7
12
VNN
24
SW8
36
VNN
48
SW23
Doc.# DSFP-HV2761
NR010913
7
Supertex inc.
www.supertex.com
HV2761
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
D
D1
E1 E
Note 1
(Index Area
D1/4 x E1/4)
48
1
e
b
Top View
View B
A A2
L2
Seating
Plane
L
L1
A1
θ
Gauge
Plane
Seating
Plane
View B
Side View
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
A1
A2
b
D
D1
E
E1
MIN
Dimension
NOM
(mm)
MAX
1.40*
0.05
1.35
0.17
8.80*
6.80*
8.80*
6.80*
-
-
1.40
0.22
9.00
7.00
9.00
7.00
1.60
0.15
1.45
0.27
9.20*
7.20*
9.20*
7.20*
e
L
0.50
BSC
0.45
0.60
0.75
L1
L2
1.00
REF
0.25
BSC
θ
0O
3.5O
7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV2761
NR010913
8
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com