Quad HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics Digitizer and 3D Comb Filter Decoder ADV7844 Data Sheet Vertical peaking and horizontal peaking filters Robust synchronization extraction for poor video source Advanced VBI data slicer General Highly flexible 36-bit pixel output interface Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function support Any-to-any, 3 × 3 color space conversion (CSC) matrix 2 programmable interrupt request output pins Simultaneous analog processing and HDMI monitoring APPLICATIONS Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP® rear projection HDTVs LCoS™ HDTVs AVR video receivers HDTV STBs with PVR Projectors FUNCTIONAL BLOCK DIAGRAM SDRAM ADC SD/PS YPbPr ADC ADC CVBS SCART G SCART B SCART R HS/VS SDP CVBS 3D YC S-VIDEO SCART FIELD/DE CLK DATA HS/VS CP YPbPr 525p/625p Pb/B 720p/1080i 1080p/ Pb/R UXGA RGB Y/G HD YpbPr GRAPHICS RGB HDMI 1 TMDS DDC HDMI 2 TMDS DDC HDMI 3 TMDS DDC HDMI 4 TMDS DDC S/PDIF ARC_1± ARC_2± ARC FIELD/DE HS/VS FIELD/DE CLK 36-BIT YCbCr/RGB CLK DATA 36 4 I 2S S/PDIF DEEP COLOR HDMI Rx DSD HBR MCLK FAST SWITCH HDCP KEYS SCLK ADV7844 AUDIO OUTPUT 5 MCLK SCLK TO AUDIO PROCESSOR 08850-001 ADC CVBS YC 48 CVBS SCART RGB + CVBS OUTPUT MUX SCART CVBS OUTPUT MUX Quad HDMI® 1.4 fast switching receiver HDMI support Audio return channel (ARC) 3D TV support Content type bits CEC 1.4-compatible Extended colorimetry HDMI 225 MHz receiver Xpressview fast switching of HDMI ports 2 ARC interfaces for ARC support SPDIF interface for ARC support 3D video format support, including frame packing 1080p 24 Hz, 720p 50 Hz, 720p 60 Hz Full colorimetry support including sYCC601, Adobe RGB, Adobe YCC 601 36-/30-bit Deep Color and 24-bit color support HDCP 1.4 support with internal HDCP keys 5 V detect and hot plug assert for each HDMI port Adaptive HDMI equalizer Integrated CEC controller HDMI repeater support HDMI audio support including HBR and DSD Advanced audio mute feature Flexible digital audio output interfaces Supports up to 5 S/PDIF outputs Supports up to 4 I2S outputs Video and graphics digitizer Four 170 MHz, 12-bit ADCs 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Low refresh rates (24/25/30 Hz) support for 720p/1080p Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA) SCART fast blank support 3D video decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i IF compensation filters INPUT MUX FEATURES Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. ADV7844 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up Sequence ................................................................... 23 Applications....................................................................................... 1 Power-Down Sequence.............................................................. 23 Functional Block Diagram .............................................................. 1 Functional Overview...................................................................... 24 Revision History ............................................................................... 2 HDMI Receiver........................................................................... 24 General Description ......................................................................... 3 Analog Front End....................................................................... 24 Detailed Functional Block Diagram .............................................. 4 Standard Definition Processor ................................................. 25 Specifications..................................................................................... 5 Component Processor ............................................................... 25 Electrical Characteristics............................................................. 5 Other Features ............................................................................ 26 Power Specifications .................................................................... 6 External Memory Requirements .................................................. 27 Analog Specifications................................................................... 8 Single Data Rate (SDR).............................................................. 27 Video Specifications..................................................................... 9 Double Data Rate (DDR) .......................................................... 27 Timing Characteristics .............................................................. 10 Pixel Input/Output Formatting .................................................... 28 Timing Diagrams........................................................................ 11 Pixel Data Output Modes Features .......................................... 28 Absolute Maximum Ratings.......................................................... 12 Register Map Architecture ............................................................ 29 Package Thermal Performance................................................. 12 Outline Dimensions ....................................................................... 30 ESD Caution................................................................................ 12 Ordering Guide .......................................................................... 30 Pin Configuration and Function Descriptions........................... 13 Power Supply Sequencing.............................................................. 23 REVISION HISTORY 4/12—Rev. B: Initial Version Rev. B | Page 2 of 32 Data Sheet ADV7844 GENERAL DESCRIPTION The multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of a composite or an S-Video input signal into a digital ITU-R BT.656 format. SCART and overlay functionality are enabled by the ability of the ADV7844 to process CVBS and standard definition RGB signals simultaneously. The ADV7844 is a high quality, single-chip, 4:1 multiplexed HDMI receiver and graphics digitizer with an integrated multiformat video decoder. The ADV7844 incorporates a quad input HDMI-compatible receiver that supports all HDTV formats up to 1080p and display resolutions up to UXGA (1600 × 1200 at 60 Hz). The ADV7844 incorporates Xpressview™ fast switching on all input HDMI ports. Using the Analog Devices, Inc., hardwarebased HDCP engine that minimizes software overhead, Xpressview™ technology allows fast switching between any HDMI input ports in less than 1 second. The ADV7844 supports all mandatory HDMI 3D TV formats in addition to all HDTV formats up to 1080p 36-bit Deep Color. The ADV7844 also integrates an HDMI CEC controller that supports the capability discovery and control (CDC) feature. The ADV7844 offers a flexible audio output port for the audio data decoded from the HDMI stream. HDMI audio formats, including super audio CD (SACD) via DSD and HBR are supported. The ADV7844 also features the audio return channel (ARC) feature. ARC simplifies cabling by combining upstream audio capability in a conventional HDMI cable. Each HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output. The ADV7844 contains one main component processor (CP), which processes YPbPr and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7844 can operate in quad HDMI and analog input mode, thus allowing for fast switching between the ADCs and HDMI. The ADV7844 supports the decoding of a component RGB/ YPbPr video signal into a digital YCbCr or RGB pixel output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other SMPTE and HD standards. The ADV7844 supports graphics digitization. The ADV7844 is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into a digital RGB or YCbCr pixel output stream. Internal EDID is available for one graphic port. Fabricated in an advanced CMOS process, the ADV7844 is provided in a 19 mm × 19 mm, 425-ball, CSP BGA, surfacemount, RoHS-compliant package, and is specified over the 0°C to 70°C temperature range. Rev. B | Page 3 of 32 Figure 2. Detailed Functional Block Diagram Rev. B | Page 4 of 32 EQUALIZER EQUALIZER RXB_0± RXB_1± RXB_2± RXC_0± RXC_1± RXC_2± SAMPLER SAMPLER SAMPLER SAMPLER HDCP BLOCK HDCP EEPROM AUDIO RETURN CHANNEL EQUALIZER EQUALIZER RXA_0± RXA_1± RXA_2± RXD_0± RXD_1± RXD_2± ARC_1± ARC_2± SPDIF_IN PLL EDID/ REPEATER CONTROLLER 5V DETECT AND HPD CONTROLLER CEC CONTROLLER AVLINK CONTROLLER I2C CONTROL INTERFACE TRI-LEVEL SLICER RXA_C± RXB_C± DDCA_SDA/DDCA_SC L DDCB_SDA/DDCB_SC L DDCC_SDA/DDCC_SC L DDCD_SDA/DDCD_SC L RXA_5V/HPA_A RXB_5V/HPA_B RXC_5V/HPA_C RXD_5V/HPA_D CEC AVLINK SCL SDA TRI1 TO TRI4 SYNC PROCESSING AND CLOCK GENERATION LLC GENERATION SYNC1 SYNC2 SYNC3 SYNC4 HS_IN1/TRI5 VS_IN1/TRI6 HS_IN2/TRI7 VS_IN2/TRI8 CLAMP CLAMP CLAMP 12-CHANNE L INPUT MATRIX RGB YPrPb SCART RGB YC CVBS CONTROL HS/CS, VS/FIELD 12 12 12 12 PACKET PROCESSOR FILTER 4:2:2 TO 4:4:4 CONVERSION DEEP COLOR CONVERSION CONTROL AND DATA ADC3 ADC2 ADC1 ADC0 FAST SWITCHING BLOCK + HDMI DECODE + MUX CLAMP MUX PACKET/ INFOFRAME MEMORY (A) (B) (C) (D) (C) (B) (A) ANCILLARY DATA FORMATTER AV CODE INSERTION FAST I2C INTERFACE AUDIO PROCESSOR INTERRUPT CONTROLLER ACTIVE PEAK AND HSYNC DEPTH OFFSET ADDER CP CSC AND DECIMATION FILTERS GAIN CONTROL NOISE AND CALIBRATION DIGITAL FINE CLAMP STANDARD IDENTIFICATION SYNC EXTRACT (ESDP) VIDEO DATA PROCESSOR READBACK I2C VBI DECODER PROGRAMMABLE DELAY MACROVISION AND CGMS DETECTION SYNC SOURCE AND POLARITY DETECT COMPONENT PROCESSOR FASTBLANK OVERLAY CONTROL COLOR SPACE CONVERSION DIGITAL PROCESSING BLOCK CTI AND LTI INTERLACE TO PROGRESSIVE CONVERSION MACROVISION DETECTION DECIMATION FILTERS DDR/SDR-SDRAM INTERFACE STANDARD AUTODECTION 3D COMB HORIZONTAL PEAKING VERTICAL PEAKING 2D COMB TBC STANDARD DEFINITION PROCESSOR (SDP) VIDEO OUTPUT FORMATTER AUDIO OUTPUT FORMATTER ANALOG FRONT END 12 12 12 MCLK SCLK AP2 AP3 AP4 AP5 AP0 AP1 INT1 INT2 TTX_SDA/TTX_SCL VS/FIELD FIELD/DE SYNC_OUT LLC HS/CS P24 TO P35 P12 TO P23 P0 TO P11 08850-002 AOUT ADV7844 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM Data Sheet ADV7844 SPECIFICATIONS AVDD = 1.8 V ± 5%, CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, PVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, TVDD = 3.3 V ± 5%, VDD_SDRAM = 3.2 V to 3.4 V (SDR), VDD_SDRAM = 2.35 V to 2.65 V (DDR). TMIN to TMAX = 0°C to 70°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL INPUTS (5 V TOLERANT) 1 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance 1 Symbol N INL DNL VIH VIL VIH VIL IIN Test Conditions/Comments Min 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 74.25 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 75 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) XTALN and XTALP pins XTALN and XTALP pins Other digital inputs Other digital inputs Reset pin EP_MISO pin SPDIF_IN pin TEST4 pin TEST6 pin Other digital inputs Typ Max Unit 12 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB −3.0 to +8.0 −3.0 to +8.0 −4.0 to +7.0 −3.5 to +8.0 −0.7 to +1.5 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.6 to +0.5 1.2 0.8 ±60 ±60 ±60 ±60 ±60 ±10 10 V V V V μA μA μA μA μA μA pF 0.8 +82 V V μA 0.4 2 CIN VIH VIL IIN 2.6 VOH VOL ILEAK COUT 2.4 −82 0.4 10 20 V V μA pF The following pins are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, RXA_5V, RXB_5V, RXC_5V, RXD_5V, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, and DDCD_SDA. Rev. B | Page 5 of 32 ADV7844 Data Sheet POWER SPECIFICATIONS Table 2. Parameter POWER REQUIREMENTS Digital Core Power Supply Digital I/O Power Supply SDRAM Power Supply PLL Power Supply Analog Power Supply Terminator Power Supply Comparator Power Supply CURRENT CONSUMPTION 1, 2, 3 Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Symbol Min Typ Max Unit VDD DVDDIO VDD_SDRAM 1.75 3.14 1.8 3.3 1.85 3.46 V V 3.2 2.35 1.71 1.71 3.14 1.71 3.3 2.5 1.8 1.8 3.3 1.8 3.4 2.65 1.89 1.89 3.46 1.89 V V V V V V SDR memory DDR memory 155 149 365 220 205 445 mA mA mA 148 298 210 385 mA mA 440 475 mA 480 525 mA 55 40 37 120 122 120 mA mA mA 15 14 175 175 mA mA 9 11 mA 9 10 mA 27 25 24 30 29 28 mA mA mA 34 35 37 38 mA mA 33 36 mA 33 38 mA Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with all background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color with all background ports enabled SD core 576i processing in simultaneous mode with all background ports enabled SCART processing in simultaneous mode with all background ports enabled Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with all background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color with all background ports enabled SD core 576i processing in simultaneous mode with all background ports enabled SCART processing in simultaneous mode with all background ports enabled Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with all background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color with all background ports enabled SD core 576i processing in simultaneous mode with all background ports enabled SCART processing in simultaneous mode with all background ports enabled PVDD AVDD TVDD CVDD IVDD IDVDDIO IPVDD Rev. B | Page 6 of 32 Test Conditions/Comments Data Sheet Parameter Analog Supply Current ADV7844 Symbol IAVDD Terminator Supply Current 4 ITVDD Comparator Supply Current ICVDD Memory Interface Supply Current Power-Down Currents 5 IVDD_SDRAM Power-Up Time IDVDDIO IVDD_SDRAM IVDD IAVDD ICVDD ITVDD IPVDD tPWRUP Min Typ 210 215 214 Max 235 240 235 Unit mA mA mA 0 0 0.1 0.1 mA mA 80 90 mA 260 285 mA 85 260 105 420 95 280 120 440 mA mA mA mA 28 35 mA 0.1 2.6 10 0.1 0.5 2.2 1.7 mA mA mA mA mA mA mA ms 25 1 Test Conditions/Comments Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with all background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color with all background ports enabled SD core 576i processing in simultaneous mode with all background ports enabled SCART processing in simultaneous mode with all background ports enabled One port connected Four ports connected HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with all background ports enabled CVBS input sampling at 54 MHz All maximum current values are guaranteed by characterization to assist in power supply design. Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature. Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature. 4 Termination power supply includes TVDD current consumed off chip. 5 Power-down mode entered by setting Bit POWER_DOWN high. 2 3 Rev. B | Page 7 of 32 ADV7844 Data Sheet ANALOG SPECIFICATIONS Table 3. Parameter CLAMP CIRCUITRY 1 Input Impedance Analog (AIN1 – AIN12) ADC Midscale (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 Test Conditions/Comments Min Typ Max Unit Clamps switched off 10 MΩ Component input, Y signal Component input, Pr signal Component input, Pb signal PC RGB input (R, G, B signals) CVBS input SCART RGB input (R, G, B signals) S-Video input (Y Signal) S-Video input (C Signal) SDP only SDP only SDP only SDP only 0.91 CML + 0.55 CML − 0.55 1.1 CML − 0.12 CML CML CML − 0.12 CML − 0.205 CML − 0.205 CML − 0.205 CML 0.3 0.4 9 8 V V V V V V V V V V V V mA mA μA μA Specified for external clamp capacitor of 100 nF. Rev. B | Page 8 of 32 Data Sheet ADV7844 VIDEO SPECIFICATIONS Table 4. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS (SDP) Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range Color Lock-In Time Sync Depth Range1 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS (SDP) Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation Symbol Test Conditions/Comments DP DG LNL CVBS input (modulated five-step) CVBS input (modulated five-step) CVBS input (modulated five-step) Measured at 27 MHz LLC Luma ramp Luma flat field Min Typ Max 0.6 0.8 0.9 Degrees % % 63 64 60 dB dB dB ±5 300 100 % Hz kHz Lines % % ms Lines 0.9 0.3 0.3 % Degrees % 40 fSC 70 ±0.8 60 20 1 Rev. B | Page 9 of 32 Unit 200 200 ADV7844 Data Sheet TIMING CHARACTERISTICS Data and I2C Timing Characteristics Table 5. Parameter 1 CLOCK AND CRYSTAL Crystal Frequency, XTAL Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORTS SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time TTX I2C PORTS SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio Symbol Test Conditions/Comments Min Typ Max Unit ±50 110 170 MHz ppm kHz MHz 28.63636 10 12.825 400 t1 t2 t3 t4 t5 t6 t7 t8 600 1.3 600 600 100 t1 t2 t3 t4 t5 t6 t7 t8 60 160 160 160 10 10 10 160 1000 300 0.6 3.4 80 80 5 t9:t10 kHz ns μs ns ns ns ns ns μs MHz ns ns ns ns ns ns ns ns ms 45:55 55:45 % duty cycle 4.6 0.6 2.2 0.3 ns ns ns ns 55:45 10 10 5 5 % duty cycle ns ns ns ns DATA AND CONTROL OUTPUTS 2 Data Output Transition Time SDR (SDP) Data Output Transition Time SDR (SDP) Data Output Transition Time SDR (CP) Data Output Transition Time SDR (CP) I2S PORT, MASTER MODE SCLK Mark-Space Ratio LRCLK Data Transition Time LRCLK Data Transition Time I2Sx Data Transition Time I2Sx Data Transition Time 1 2 t11 t12 t13 t14 End of valid data to negative clock edge Negative clock edge to start of valid data End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 2.9 0.2 1.5 0.1 45:55 Guaranteed by characterization. With the DLL block on output clock bypassed. Rev. B | Page 10 of 32 Data Sheet ADV7844 TIMING DIAGRAMS t3 t5 t3 SDA t6 t1 t2 t7 t4 08850-003 SCL t8 Figure 3. I2C Timing t9 t10 LLC t11 08850-004 t12 P0 TO P35, HS/CS, VS/FIELD, FIELD/DE Figure 4. Pixel Port and Control SDR Output Timing (SDP) t9 t10 LLC t13 08850-005 t14 P0 TO P35, HS/CS, VS/FIELD, FIELD/DE Figure 5. Pixel Port and Control SDR Output Timing (CP) t15 SCLK t16 t17 LRCLK t18 t19 MSB MSB – 1 t20 I2Sx I2S MODE I2Sx RIGHT-JUSTIFIED MODE t19 MSB MSB – 1 t20 t19 MSB NOTES 1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES. 2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN. 3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS. Figure 6. I2S Timing Rev. B | Page 11 of 32 LSB t20 08850-006 I2Sx LEFT-JUSTIFIED MODE ADV7844 Data Sheet ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 6. Parameter AVDD to GND VDD to GND PVDD to GND DVDDIO to GND VDD_SDRAM to GND CVDD to GND TVDD to GND AVDD to PVDD AVDD to VDD TVDD to CVDD DVDDIO to VDD_SDRAM VDD_SDRAM to AVDD VDD_SDRAM to VDD Digital Inputs Voltage to GND Digital Outputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Analog Inputs to GND XTALN and XTALP to GND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 2.2 V 4.0 V 4.0 V 2.2 V 4.0 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +2.2 V −0.3 V to +3.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to DVDDIO + 0.3 V −0.3 V to DVDDIO + 0.3 V 5.5 V −0.3 V to AVDD + 0.3 V −0.3 V to PVDD + 0.3 V 125°C −65°C to +150°C 260°C The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, and DDCD_SDA. To reduce power consumption when using the ADV7844, the user is advised to turn off unused sections of the part. Due to PCB metal variation, and therefore variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): ( T J = TS + Ψ JT × WTOTAL ) where: TS is the package surface temperature (°C). ΨJT = 0.7°C/W for the 425-ball CSP_BGA. WTOTAL = (PVDD × IPVDD) + (0.4 × TVDD × ITVDD) + (CVDD × ICVDD) + (AVDD × IAVDD) + (VDD × IVDD) + (A × DVDDIO × IDVDDIO) + (VDD_SDRAM × IVDD_SDRAM) where 0.4 reflects the 40% of TVDD power that is dissipated on the part itself. A = 0.5 when the output pixel clock is >74 MHz. A = 0.75 when the output pixel clock is ≤74 MHz. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 12 of 32 Data Sheet ADV7844 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 GND VS/FIELD TEST6 TEST7 TVDD RXD_2– RXD_1– RXD_0– RXD_C– ARC_2– TVDD RXC_2– RXC_1– RXC_0– RXC_C– NC TVDD RXB_2– RXB_1– RXB_0– RXB_C– ARC_1– GND A FIELD/DE TEST8 TEST9 TVDD RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_2+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ NC TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_1+ GND B B HS/CS 5 6 7 8 9 10 11 C P0 P1 TEST10 TEST11 TVDD PWRDN1 TEST14 HPA_D RXD_5V RXC_5V TVDD D P2 P3 TEST12 TEST13 TVDD E DVDDIO DVDDIO GND SYNC_OUT 12 GND 13 GND 14 GND 15 GND 16 GND 17 GND 18 19 20 21 22 23 TVDD TVDD TVDD TVDD TVDD TVDD C CEC HPA_C RXB_5V HPA_B TVDD RXA_5V HPA_A DDCD_SDADDCD_SCLDDCC_SDADDCC_SCLRTERM DDCB_SDADDCB_SCL TVDD RXA_2+ RXA_2– D GND DDCA_SDA CVDD RXA_1+ RXA_1– E EP_MOSI DDCA_SCL CVDD RXA_0+ RXA_0– F F P5 P4 EP_MISO G P7 P6 EP_CS EP_SCK GND GND GND GND H P9 P8 TTX_SDA TTX_SCL GND GND GND GND GND GND J P11 P10 MCLK AP0 GND GND GND GND GND K P13 P12 AP5 SCLK VDD GND GND GND L DVDDIO DVDDIO GND GND VDD GND GND TEST1 TEST2 GND GND CVDD CVDD CVDD VGA_SCL CVDD RXA_C+ RXA_C– G GND GND CVDD CVDD CVDD VGA_SDA CVDD GND GND GND GND GND GND PVDD TEST3 GND GND GND GND GND GND GND GND PVDD GND XTALN XTALP K GND GND GND GND GND GND GND GND GND GND GND GND GND REFN REFP M NC NC H GND J GND L M P15 P14 AP4 AP3 VDD GND GND GND GND GND GND GND GND GND GND N P17 P16 AP2 AP1 VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AVDD AVDD N P P18 P19 SCL SDA VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AIN11 AIN12 P R P20 P21 TEST4 INT1 VDD GND GND GND GND GND GND GND GND GND GND HS_IN2/TRI7 VS_IN2/TRI8 T P22 P23 TEST5 INT2 VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND T VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND TRI4 TRI3 AIN9 AIN8 U TRI1 TRI2 SYNC3 AIN7 V U DVDDIO DVDDIO DVDDIO DVDDIO V LLC P24 W P25 P26 NC SPDIF_IN Y P27 P28 GND GND GND VDD_SDRAM SDRAM_A11 SDRAM_A6 SDRAM_A2 AA P29 P30 GND GND GND VDD_SDRAM SDRAM_A9 SDRAM_A5 SDRAM_A1 SDRAM_RAS SDRAM_DQ7 AB P31 P32 P34 NC GND DVDDIO SDRAM_A8 SDRAM_A4 AC GND P33 P35 NC GND DVDDIO SDRAM_A7 1 2 3 4 7 RESET AVLINK SYNC4 AIN10 R AVDD AVDD AVDD AVDD W 5 6 GND SDRAM_DQ6 SDRAM_DQ2 SDRAM_DQ15 SDRAM_DQ11 SDRAM_CKE VDD_SDRAM GND AOUT NC GND SDRAM_DQ5 SDRAM_DQ1 SDRAM_DQ12 SDRAM_DQ8 SDRAM_CK VDD_SDRAM GND NC NC SDRAM_A0 SDRAM_BA1 SDRAM_CAS VDD_SDRAM SDRAM_DQ4 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9 SDRAM_CK VDD_SDRAM GND SYNC1 SDRAM_A3 SDRAM_A10 SDRAM_BA0 SDRAM_WE 8 9 10 11 SDRAM_CS SDRAM_LDQS VDD_SDRAM SDRAM_DQ3 SDRAM_VREF SDRAM_DQ14 SDRAM_DQ10 SDRAM_UDQS VDD_SDRAM 12 13 14 Figure 7. Pin Configuration Rev. B | Page 13 of 32 15 16 17 18 AIN5 AIN6 Y SYNC2 AIN4 AA HS_IN1/TRI5 VS_IN1/TRI6 GND AB AC GND AIN1 AIN2 AIN3 GND 19 20 21 22 23 08850-007 A ADV7844 Data Sheet Table 7. Pin Function Descriptions Pin No. A1 A2 Mnemonic GND VS/FIELD Type Ground Digital video output A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 TEST6 TEST7 TVDD RXD_2− RXD_1− RXD_0− RXD_C− ARC_2− TVDD RXC_2− RXC_1− RXC_0− RXC_C− NC TVDD RXB_2− RXB_1− RXB_0− RXB_C− ARC_1− GND HS/CS Test pin Test pin Power HDMI input HDMI input HDMI input HDMI input HDMI input/output Power HDMI input HDMI input HDMI input HDMI input No connect Power HDMI input HDMI input HDMI input HDMI input HDMI input/output Ground Digital video output B2 FIELD/DE Miscellaneous digital B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 TEST8 TEST9 TVDD RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_2+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ NC TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_1+ GND Test pin Test pin Power HDMI input HDMI input HDMI input HDMI input HDMI input/output Power HDMI input HDMI input HDMI input HDMI input No Connect Power HDMI input HDMI input HDMI input HDMI input HDMI input/output Ground Description Ground. Vertical Synchronization Output Signal (VS). Field Synchronization Output Signal in All Interlaced Video Modes (FIELD). VS or FIELD can be configured for this pin. Float this pin. Float this pin. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port D in the HDMI Interface. Digital Input Channel 1 Complement of Port D in the HDMI Interface. Digital Input Channel 0 Complement of Port D in the HDMI Interface. Digital Input Clock Complement of Port D in the HDMI Interface. Audio Return Channel (ARC) Complement in ARC Interface 2. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port C in the HDMI Interface. Digital Input Channel 1 Complement of Port C in the HDMI Interface. Digital Input Channel 0 Complement of Port C in the HDMI Interface. Digital Input Clock Complement of Port C in the HDMI Interface. No Connect. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Clock Complement of Port B in the HDMI Interface. Audio Return Channel (ARC) Complement in ARC Interface 1. Ground. Horizontal Synchronization Output Signal (HS). Composite Synchronization Signal (CS). CS is a single signal containing both horizontal and vertical synchronization pulses. HS or CS can be configured for this pin. Field Synchronization Output Signal in All Interlaced Video Modes (FIELD). Data Enable (DE). DE is a signal that indicates active pixel data. DE or FIELD can be configured for this pin. Float this pin. Float this pin. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 True of Port D in the HDMI Interface. Digital Input Channel 1 True of Port D in the HDMI Interface. Digital Input Channel 0 True of Port D in the HDMI Interface. Digital Input Clock True of Port D in the HDMI Interface. Audio Return Channel (ARC) True in ARC Interface 2. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 True Of Port C in the HDMI Interface. Digital Input Channel 1 True Of Port C in the HDMI Interface. Digital Input Channel 0 True Of Port C in the HDMI Interface. Digital Input Clock True Of Port C in the HDMI Interface. No Connect. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 True of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Audio Return Channel (ARC) True in ARC Interface 1. Ground. Rev. B | Page 14 of 32 Data Sheet ADV7844 Pin No. C1 C2 C3 C4 C5 C6 Mnemonic P0 P1 TEST10 TEST11 TVDD PWRDN1 Type Digital video output Digital video output Test pin Test pin Power Miscellaneous digital C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 TEST14 HPA_D RXD_5V RXC_5V TVDD GND GND GND GND GND GND TVDD TVDD TVDD TVDD TVDD TVDD P2 P3 TEST12 TEST13 TVDD SYNC_OUT CEC HPA_C RXB_5V HPA_B TVDD RXA_5V HPA_A DDCD_SDA DDCD_SCL DDCC_SDA DDCC_SCL RTERM Test pin Miscellaneous digital HDMI input HDMI input Power Ground Ground Ground Ground Ground Ground Power Power Power Power Power Power Digital video output Digital video output Test pin Test pin Power Miscellaneous digital Digital input/output Miscellaneous digital HDMI input Miscellaneous digital Power HDMI input Miscellaneous digital Digital input/output Digital input Digital input/output Digital input Miscellaneous analog D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 DDCB_SDA DDCB_SCL TVDD RXA_2+ RXA_2− DVDDIO DVDDIO GND GND DDCA_SDA CVDD Digital input/output Digital input Power HDMI input HDMI input Power Power Ground Ground Digital input/output Power Description Video Pixel Output Port. Video Pixel Output Port. Float this pin. Float this pin. Terminator Supply Voltage (3.3 V). Controls the Power-Up of the ADV7844. Should be connected to a digital 3.3 V I/O supply to power up the ADV7844. Tie this pin to ground via a 4.7 kΩ resistor. Hot Plug Assert Signal Output for HDMI Port D. 5 V Detect Pin for Port D in the HDMI Interface. 5 V Detect Pin for Port C in the HDMI Interface. Terminator Supply Voltage (3.3 V). Ground. Ground. Ground. Ground. Ground. Ground. Terminator Supply Voltage (3.3 V). Terminator Supply Voltage (3.3 V). Terminator Supply Voltage (3.3 V). Terminator Supply Voltage (3.3 V). Terminator Supply Voltage (3.3 V). Terminator Supply Voltage (3.3 V). Video Pixel Output Port. Video Pixel Output Port. Float this pin. Float this pin. Terminator Supply Voltage (3.3 V). Sliced synchronization output. Consumer Electronic Control Channel. Hot Plug Assert Signal Output for HDMI Port C. 5 V Detect Pin for Port B in the HDMI Interface. Hot Plug Assert Signal Output for HDMI Port B. Terminator Supply Voltage (3.3 V). 5 V Detect Pin for Port A in the HDMI Interface. Hot Plug Assert Signal Output for HDMI Port A. HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant. Sets Internal Termination Resistance. A 500 Ω resistor between this pin and GND should be used. HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital I/O Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Ground. Ground. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. Comparator Supply Voltage (1.8 V). Rev. B | Page 15 of 32 ADV7844 Pin No. E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G20 G21 G22 G23 H1 H2 H3 H4 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H20 H21 H22 H23 J1 J2 J3 J4 J7 Mnemonic RXA_1+ RXA_1− P5 P4 EP_MISO EP_MOSI DDCA_SCL CVDD RXA_0+ RXA_0− P7 P6 EP_CS EP_SCK GND GND GND GND TEST1 TEST2 GND GND CVDD CVDD CVDD VGA_SCL CVDD RXA_C+ RXA_C− P9 P8 TTX_SDA TTX_SCL GND GND GND GND GND GND GND GND CVDD CVDD CVDD VGA_SDA CVDD NC NC P11 P10 MCLK AP0 GND Data Sheet Type HDMI input HDMI input Digital video output Digital video output Digital output Digital input Digital input Power HDMI input HDMI input Digital video output Digital video output Digital output Digital output Ground Ground Ground Ground Test Test Ground Ground Power Power Power Miscellaneous digital Power HDMI input HDMI input Digital video output Digital video output Miscellaneous digital Miscellaneous digital Ground Ground Ground Ground Ground Ground Ground Ground Power Power Power Miscellaneous digital Power No Connect No Connect Digital video output Digital video output Miscellaneous Miscellaneous Ground Description Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Video Pixel Output Port. Video Pixel Output Port. SPI Master In/Slave Out for External EDID Interface. SPI Master Out/Slave In for External EDID Interface. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. Comparator Supply Voltage (1.8 V). Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Video Pixel Output Port. Video Pixel Output Port. SPI Chip Select for External EDID Interface. SPI Clock for External EDID Interface. Ground. Ground. Ground. Ground. Do Not Connect. Do Not Connect. Ground. Ground. Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). DDC Port Serial Clock Input for VGA. Comparator Supply Voltage (1.8 V). Digital Input Clock True of Port A in the HDMI Interface. Digital Input Clock Complement of Port A in the HDMI Interface. Video Pixel Output Port. Video Pixel Output Port. I2C Port Serial Data Input/Output. SDA is the data line for the teletext port. I2C Port Serial Clock Input. SCL is the clock line for the teletext port. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). DDC Port Serial Data Input/Output for VGA. Comparator Supply Voltage (1.8 V). No Connect. No Connect. Video Pixel Output Port. Video Pixel Output Port. Audio Master Clock Output. Audio Output. Ground. Rev. B | Page 16 of 32 Data Sheet ADV7844 Pin No. J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J20 J21 J22 J23 K1 K2 K3 K4 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K20 K21 K22 K23 Mnemonic GND GND GND GND GND GND GND GND GND GND PVDD TEST3 GND GND P13 P12 AP5 SCLK VDD GND GND GND GND GND GND GND GND GND GND PVDD GND XTALN XTALP Type Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Power Test Ground Ground Digital video output Digital video output Miscellaneous Miscellaneous digital Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Power Ground Miscellaneous analog Miscellaneous analog L1 L2 L3 L4 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L20 L21 L22 L23 DVDDIO DVDDIO GND GND VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND Power Power Ground Ground Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Description Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. PLL Supply Voltage (1.8 V). Do Not Connect. Ground. Ground. Video Pixel Output Port. Video Pixel Output Port. Audio Output. Audio Serial Clock Output. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. PLL Supply Voltage (1.8 V). Ground. Input Pin for 28.63636 MHz Crystal. Input pin for 28.63636 MHz Crystal or an external 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7844. Digital I/O Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Ground. Ground. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Rev. B | Page 17 of 32 ADV7844 Pin No. M1 M2 M3 M4 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M20 M21 M22 M23 N1 N2 N3 N4 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N20 N21 N22 N23 P1 P2 P3 P4 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 Mnemonic P15 P14 AP4 AP3 VDD GND GND GND GND GND GND GND GND GND GND GND GND REFN REFP P17 P16 AP2 AP1 VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AVDD AVDD P18 P19 SCL SDA VDD GND GND GND GND GND GND GND GND GND GND Data Sheet Type Digital video output Digital video output Miscellaneous Miscellaneous Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Miscellaneous analog Miscellaneous analog Digital video output Digital video output Miscellaneous Miscellaneous Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Power Power Power Power Digital video output Digital video output Miscellaneous digital Miscellaneous digital Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Description Video Pixel Output Port. Video Pixel Output Port. Audio Output. Audio Output. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Internal Voltage Reference Output. Internal Voltage Reference Output. Video Pixel Output Port. Video Pixel Output Port. Audio Output. Audio Output. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Video Pixel Output Port. Video Pixel Output Port. I2C Port Serial Clock Input. SCL is the clock line for the control port. I2C Port Serial Data Input/Output. SDA is the data line for the control port. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Rev. B | Page 18 of 32 Data Sheet ADV7844 Pin No. P20 P21 P22 P23 R1 R2 R3 R4 Mnemonic AVDD AVDD AIN11 AIN12 P20 P21 TEST4 INT1 Type Power Power Analog video input Analog video input Digital video output Digital video output Test Miscellaneous digital R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R20 VDD GND GND GND GND GND GND GND GND GND GND HS_IN2/TRI7 Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Miscellaneous analog R21 VS_IN2/TRI8 Miscellaneous analog R22 SYNC4 Miscellaneous analog R23 T1 T2 T3 T4 AIN10 P22 P23 TEST5 INT2 Analog video input Digital video output Digital video output Test Miscellaneous digital T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T20 T21 T22 T23 U1 U2 U3 U4 U7 VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND DVDDIO DVDDIO DVDDIO DVDDIO VDD Power Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Power Power Power Power Power Description Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Analog Video Input Channel. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. This pin should be tied to ground. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. HS on Graphics Port 2 (HS_IN2). The HS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI7). (Selection available via the I2C.) VS on Graphics Port 2 (VS_IN2). The VS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI8). (Selection available via the I2C.) This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. Do Not Connect. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Digital I/O Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Rev. B | Page 19 of 32 ADV7844 Data Sheet Pin No. U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U20 Mnemonic VDD VDD VDD VDD VDD VDD VDD GND GND GND TRI4 Type Power Power Power Power Power Power Power Ground Ground Ground Miscellaneous analog U21 TRI3 Miscellaneous analog U22 U23 V1 V2 V3 AIN9 AIN8 LLC P24 RESET Analog video input Analog video input Digital video output Digital video output Miscellaneous digital V4 V20 AVLINK TRI1 Digital input/output Miscellaneous analog V21 TRI2 Miscellaneous analog V22 SYNC3 Miscellaneous analog V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 AIN7 P25 P26 NC SPDIF_IN AVDD AVDD AVDD AVDD P27 P28 GND GND GND VDD_SDRAM SDRAM_A11 SDRAM_A6 SDRAM_A2 SDRAM_CS Analog video input Digital video output Digital video output No connect Miscellaneous digital Power Power Power Power Digital video output Digital video output Ground Ground Ground Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface Y11 SDRAM_LDQS SDRAM interface Y12 Y13 Y14 GND SDRAM_DQ6 SDRAM_DQ2 Ground SDRAM interface SDRAM interface Description Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) Analog Video Input Channel. Analog Video Input Channel. Line-Locked Output Clock for the Pixel Data. Video Pixel Output Port. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7844 circuitry. Digital SCART Control Channel. Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. No Connect. S/PDIF Stream Input. Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Video Pixel Output Port. Video Pixel Output Port. Ground. Ground. Ground. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Chip Select. SDRAM_CS enables and disables the command decoder on the RAM. One of four command signals to the external SDRAM. Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input when reading data from external memory and output when writing data to external memory. It is edge-aligned when reading from external memory and centered with data when reading to external memory. SDRAM_ LDQS corresponds to the data on SDRAM_DQ7 to SDRAM_DQ0. Ground. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Rev. B | Page 20 of 32 Data Sheet ADV7844 Pin No. Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 Mnemonic SDRAM_DQ15 SDRAM_DQ11 SDRAM_CKE VDD_SDRAM GND AOUT NC AIN5 AIN6 P29 P30 GND GND GND VDD_SDRAM SDRAM_A9 SDRAM_A5 SDRAM_A1 SDRAM_RAS Type SDRAM interface SDRAM interface SDRAM interface Power Ground Analog monitor output No connect Analog video input Analog video input Digital video output Digital video output Ground Ground Ground Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface AA11 AA12 AA13 AA14 AA15 AA16 AA17 SDRAM_DQ7 GND SDRAM_DQ5 SDRAM_DQ1 SDRAM_DQ12 SDRAM_DQ8 SDRAM_CK SDRAM interface Ground SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface AA18 AA19 AA20 AA21 AA22 VDD_SDRAM GND NC NC SYNC2 Power Ground No connect No connect Miscellaneous analog AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AIN4 P31 P32 P34 NC GND DVDDIO SDRAM_A8 SDRAM_A4 SDRAM_A0 SDRAM_BA1 SDRAM_CAS Analog video input Digital video output Digital video output Digital video output No connect Ground Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface AB12 AB13 AB14 AB15 AB16 VDD_SDRAM SDRAM_DQ4 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9 Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface Description Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Clock Enable. This pin acts as an enable to the clock signals of the external RAM. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Ground. Analog Monitor Output. No Connect. Analog Video Input Channel. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. Ground. Ground. Ground. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Row Address Select Command Signal. One of four command signals to the external SDRAM. Data Bus. Interface to external RAM 16-bit data bus. Ground. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Differential Clock Output. All address and control output signals to the RAM should be sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Ground. No Connect. No Connect. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. No Connect. Ground. Digital I/O Supply Voltage (3.3 V). Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Bank Address Output. Interface to external RAM bank address lines. Column Address Select Command Signal. One of four command signals to the external SDRAM. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Rev. B | Page 21 of 32 ADV7844 Data Sheet Pin No. AB17 Mnemonic SDRAM_CK Type SDRAM interface AB18 AB19 AB20 VDD_SDRAM GND SYNC1 Power Ground Miscellaneous analog AB21 HS_IN1/TRI5 Miscellaneous analog AB22 VS_IN1/TRI6 Miscellaneous analog AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 GND GND P33 P35 NC GND DVDDIO SDRAM_A7 SDRAM_A3 SDRAM_A10 SDRAM_BA0 SDRAM_WE Ground Ground Digital video output Digital video output No connect Ground Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface AC12 AC13 AC14 AC15 AC16 AC17 VDD_SDRAM SDRAM_DQ3 SDRAM_VREF SDRAM_DQ14 SDRAM_DQ10 SDRAM_UDQS Power SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface AC18 AC19 AC20 AC21 AC22 AC23 VDD_SDRAM GND AIN1 AIN2 AIN3 GND Power Ground Analog video input Analog video input Analog video input Ground Description Differential Clock Output. All address and control output signals to the RAM should be sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Ground. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. HS on Graphics Port 1 (HS_IN1). The HS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI5). (Selection available via the I2C.) VS on Graphics Port 1 (VS_IN2). The VS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI6). (Selection available via the I2C.) Ground. Ground. Video Pixel Output Port. Video Pixel Output Port. No Connect. Ground. Digital I/O Supply Voltage (3.3 V). Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Bank Address Output. Interface to external RAM bank address lines. Write Enable Output Command Signal. One of four command signals to the external SDRAM. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Data Bus. Interface to external RAM 16-bit data bus. 1.25 V Reference for DDR SDRAM Interface or 1.65 V for SDR. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Upper Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input when reading data from external memory and an output when writing data to external memory. It is edge-aligned with data when reading from external memory and centered with data when writing to external memory. SDRAM_UDQS corresponds to the data on SDRAM_DQ15 to SDRAM_DQ8. External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Ground. Analog Video Input Channel. Analog Video Input Channel. Analog Video Input Channel. Ground. Rev. B | Page 22 of 32 Data Sheet ADV7844 POWER SUPPLY SEQUENCING POWER-UP SEQUENCE Notes The recommended power-up sequence of the ADV7844 is as follows: Reset should be held low while the supplies are being powered up. 3.3 V supplies 2.5 V supply (applies only if using DDR memory) 1.8 V supplies 3.3V POWER SUPPLY (V) 2.5V • • • 3.3 V supplies should be powered up first. 2.5 V supply should be powered after the 3.3 V supplies are established but before the 1.8 V supplies. 1.8 V supplies should be powered up last. 3.3V SUPPLIES The ADV7844 can alternatively be powered up by asserting all supplies simultaneously. 2.5V SUPPLIES (IF ANY) In this case, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level, as the supplies are being established. 1.8V SUPPLIES 1.8V POWER-DOWN SEQUENCE The ADV7844 supplies can be deasserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3.3V SUPPLIES POWER-UP 2.5V SUPPLIES 1.8V SUPPLIES POWER-UP POWER-UP 08850-009 1. 2. 3. Figure 8. Recommended Power-Up Sequence Rev. B | Page 23 of 32 ADV7844 Data Sheet FUNCTIONAL OVERVIEW HDMI RECEIVER The ADV7844 front end incorporates a 4:1 multiplexed HDMI receiver with Xpressview fast switching technology and support for HDMI features including ARC and 3D TV. Building on the feature set of Analog Devices existing HDMI devices, the ADV7844 also offers support for all HD TV formats up to 12bit, 1080p Deep Color and all display resolutions up to UXGA (1600 × 1200 at 60 Hz). Xpressview fast switching technology, using Analog Devices hardware-based HDCP engine that minimizes software overhead, allows switching between any two input ports in less than 1 second. With the inclusion of HDCP 1.4, the ADV7844 can receive encrypted video content. The HDMI interface of the ADV7844 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewal of that authentication during transmission, as specified by the HDCP 1.4 protocol. Repeater support is also offered by the ADV7844. The ADV7844 supports the audio return channel feature. There is a dedicated S/PDIF input on which audio can be received for retransmission on the HDMI input. A wide range of 3D video formats is supported, including frame packing 1080p 24 Hz, 720p 50 Hz, and 720p 60 Hz. The HDMI receiver incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest HDMI data rates. The HDMI receiver offers advanced audio functionality. It supports multichannel I2S audio for up to eight channels. It also supports a 6-DSD channel interface with each channel carrying an oversampled 1-bit representation of the audio signal as delivered on SACD. The ADV7844 can also receive HBR audio packet streams and outputs them through the HBR interface in an S/PDIF format conforming to the IEC60958 standard. The receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be ramped to mute to prevent audio clicks or pops. • • • • ANALOG FRONT END The ADV7844 analog front end comprises four 170 MHz, 12-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP) or component processor (CP). The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7844 without the requirement of an external mux. Current and voltage clamp control loops ensure that any dc offsets are removed from the video signal. The clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. The ADCs are configured to run up to 8× oversampling mode when decoding composite or S-Video inputs. For component 525i, 625i, 525p, and 625p sources, 4× oversampling is performed. All other video standards are 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR). Optional internal antialiasing filters with programmable bandwidth are positioned in front of each ADC. These filters can be used to band limit video signals, removing spurious, outof-band noise. The ADV7844 can support the simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed with the output under the control of I2C registers. Analog front-end features include: • • HDMI receiver features include: • • • • • • • • 4:1 multiplexed HDMI receiver HDMI, ARC, and 3D format support, DVI 1.0 225 MHz HDMI receiver Integrated equalizer High-bandwidth Digital Content Protection (HDCP 1.4) on background ports Internal HDCP keys 36-/30-bit Deep Color support PCM, HBR, and DSD audio packet support Repeater support Internal E-EDID RAM Hot plug assert output pin for each HDMI port CEC controller • • • • Rev. B | Page 24 of 32 Four 170 MHz, NSV, 12-bit ADCs that enable true 12-bit video decoding 12-channel analog input mux that enables multiple source connections without the requirement of an external mux Four current and voltage clamp control loops that ensure any dc offsets are removed from the video signal SCART functionality and SD RGB overlay on CVBS controlled by fast blank input SCART source switching detection through the TRI1 to TRI8 inputs Four programmable antialiasing filters Data Sheet ADV7844 STANDARD DEFINITION PROCESSOR The SDP is capable of decoding a large selection of baseband video signals in composite and S-Video formats. The video standards supported by the SDP include PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The ADV7844 can automatically detect the video standard and process it accordingly. The SDP has a 3D temporal comb filter and a five-line adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter controls for brightness, contrast, saturation, and hue. The ADV7844 implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7844 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs, VCR players, and camcorders). Frame TBC ensures stable clock synchronization between the decoder and the downstream devices. The SDP also contains both a luma transient improvement (LTI) block and a chroma transient improvement (CTI) block. These increase the edge rate on the luma and chroma transitions, resulting in a sharper video image. The SDP has a Macrovision® detection circuit that allows Type I, Type II, and Type III Macrovision protection levels. The decoder is also fully robust to all Macrovision signal inputs. • • • • COMPONENT PROCESSOR The CP section of the ADV7844 is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The any-to-any, 3 × 3 CSC matrix is placed between the analog front end and the CP section. This enables YPbPr to RGB and RGB to YCbCr conversions. Many other standards of color space can be implemented using the color space converter. The CP section contains circuitry to enable the detection of Macrovision encoded YPbPr signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI extraction of CGMS data is performed by the CP section of the ADV7844 for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. CP features include: • • • SDP features include: • • • • • • • • • • • Advanced adaptive 3D comb (using either external DDR or SDR SDRAM memory) Adaptive 2D five-line comb filters for NTSC and PAL that give superior chrominance and luminance separation for composite video Full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM) Automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners IF filter block that compensates for high frequency luma attenuation due to tuner SAW filter LTI and CTI Vertical and horizontal programmable luma peaking filters 8× oversampling (108 MHz) for CVBS, and S-Video modes Line-locked clock (LLC) output Free-run output mode that provides stable timing when no video input is present or video lock is lost Internal color bar test pattern Advanced TBC with frame synchronization, which ensures nominal clock and data for nonstandard input Interlace-to-progressive conversion for 525i and 625i formats, enabling direct drive of HDMI Tx devices Color controls that include hue, brightness, saturation, and contrast • • • • • • • • • Rev. B | Page 25 of 32 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats are supported Supports 720p 24 Hz/25 Hz formats Manual adjustments including gain (contrast), offset (brightness), hue, and saturation Support for analog component YPbPr and RGB video formats with embedded synchronization, composite synchronization or separate HS and VS Any-to-any, 3 × 3 CSC matrix that supports YCbCr-toRGB and RGB-to- YCbCr, fully programmable or preprogrammable configurations Synchronization source polarity detector (SSPD) that determines the source and polarity of the synchronization signals that accompany the input video Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) Free-run output mode that provides stable timing when no video input is present or video lock is lost Arbitrary pixel sampling support for nonstandard video sources 170 MHz conversion rate, which supports RGB input resolutions up to 1600 × 1200 at 60 Hz Automatic or manual clamp-and-gain controls for graphics modes Contrast, brightness, hue, and saturation controls ADV7844 • • • • • Data Sheet 32-phase ADC DLL that allows optimum pixel clock sampling Automatic detection of synchronization source and polarity by SSPD block Standard identification enabled by STDI block RGB that can be color space converted to YCbCr and decimated to a 4:2:2 format for video-centric back-end IC interfacing Data enable (DE) output signal supplied for direct connection to HDMI/DVI Tx IC OTHER FEATURES The ADV7844 has HS, VS, FIELD, and DE output signals with programmable position, polarity, and width, and two I2C host port interfaces (control and VBI). The ADV7844 has two programmable interrupt request output pins, INT1 and INT2. It also features a number of low power modes and a full power-down mode. The ADV7844 is provided in a 19 mm × 19 mm, RoHS-compliant CSP_BGA package, and is specified over the 0°C to +70°C temperature range. For more detailed product information about the ADV7844, contact your local Analog Devices sales office. Rev. B | Page 26 of 32 Data Sheet ADV7844 EXTERNAL MEMORY REQUIREMENTS The ADV7844 uses external SD RAM for 3D comb and frame synchronizer. The ADV7844 supports either SDR or DDR SD RAM. SINGLE DATA RATE (SDR) The ADV7844 can use SDR external memory to provide 3D comb or frame synchronizer operation nonconcurrently. There is a 64 Mb SDR SDRAM minimum memory requirement. The required memory architecture is four banks of 1 Mb × 16 (4M16) with a speed grade of 133 MHz at CAS latency (CL) 3. Using 22 Ω series termination resistors is recommended for this configuration. Recommended SDR memory that is compatible with the ADV7844 includes Winbond W9864G6PH-7. DOUBLE DATA RATE (DDR) The ADV7844 can use DDR external memory to simultaneously provide 3D comb and frame synchronizer operation. There is a 128 Mb DDR SDRAM minimum memory requirement. The required memory architecture is four banks of 2 Mb × 16 (8M16) with a speed grade of 133 MHz at CL 2.5. Using 22 Ω series termination resistors is recommended for this configuration Recommended DDR memory that is compatible with the ADV7844 includes the K4H561638J-LCB3 from Samsung, the MT46V16M16P-6T from Micron Technology, Inc., and the H5DU1262GTR-E3C from Hynix, Inc. Rev. B | Page 27 of 32 ADV7844 Data Sheet PIXEL INPUT/OUTPUT FORMATTING The output section of the ADV7844 is highly flexible. The pixel output bus can support up to 36-bit 4:4:4. The pixel data supports both single and double data rates modes. In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In DDR mode, the pixel output port can be configured in 8-/10-/12-bit 4:2:2 modes or 24-/30-/36-bit 4:4:4 modes. Bus rotation and bus inversion are also supported. All output modes are controlled via I2C controls. PIXEL DATA OUTPUT MODES FEATURES The output pixel port features include the following: • • • • 8-/10-/12-bit ITU-R BT.656 4:2:2 with embedded time codes and/or HS, VS, and FIELD output signals SDR 16-/20-/24-/30-/36 bit with embedded time codes and/or HS and VS/FIELD pin timing DDR 8-/10-/12-bit 4:2:2 with embedded time codes and/or HS, VS, and FIELD output signals DDR 24-/30-/36 bit 4:4:4 with embedded time codes and/or HS, VS, and FIELD output signals Note that DDR modes are supported up to 54 MHz by characterization. Rev. B | Page 28 of 32 Data Sheet ADV7844 REGISTER MAP ARCHITECTURE programmed; this ensures no addressing clashes on the system. Figure 9 shows the register map architecture. The registers of the ADV7844 are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7844 has 12 maps. The IO map has a static I2C address. All other map addresses must be Table 8. Register Map Name IO Map CP Map SDP Map SDP_IO Map VDP Map AVLINK Map CEC Map HDMI Map EDID Map Repeater Map AFE, DPLL Map InfoFrame Map Default Address 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Programmable Address Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Location at Which Address Can Be Programmed Not applicable IO map, Register 0xFD IO map, Register 0xF1 IO map, Register 0xF2 IO map, Register 0xFE IO map, Register 0xF3 IO map, Register 0xF4 IO map, Register 0xFB IO map, Register 0xFA IO map, Register 0xF9 IO map, Register 0xF8 IO map, Register 0xF5 IO MAP CP MAP SDP MAP SDP_IO MAP VDP MAP AVLINK MAP CEC MAP SLAVE ADDRESS: 0x40 SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SCL SDA SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE HDMI MAP EDID MAP REPEATER MAP AFE, DPLL MAP INFOFRAME MAP 08850-008 SLAVE ADDRESS: PROGRAMMABLE Figure 9. Register Map Architecture Rev. B | Page 29 of 32 ADV7844 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 19.20 19.00 SQ 18.80 A1 BALL CORNER 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 A C E G 17.60 BSC SQ J L N 0.80 BSC R U W B D F H K M P T V Y AA AB AC TOP VIEW 1.50 1.36 1.21 BOTTOM VIEW DETAIL A 0.65 NOM DETAIL A 1.11 1.01 0.91 0.35 NOM 0.30 MIN SEATING PLANE 0.50 COPLANARITY 0.12 0.45 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2. 11-22-2011-A 0.35 NOM Figure 10. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-425-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV7844KBCZ-5 EVAL-ADV7844EB1Z Notes 2, 3 3, 4, 5 Temperature Range 0°C to +70°C 0°C to +70°C Package Description 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Front-End Evaluation Board 1 Package Option BC-425-1 Z = RoHS-Compliant Part. Speed grade: 5 = 170 MHz. 3 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to purchase any components with internal HDCP keys. 4 An ATV motherboard is also required to process the ADV7844 digital outputs and achieve video output. An ATV video output board is optional to evaluate performance through an HDMI transmitter and video encoder. 5 Front-end board for the ATV video evaluation platform, fitted with ADV7844KBCZ-5 decoder. 2 Rev. B | Page 30 of 32 Data Sheet ADV7844 NOTES Rev. B | Page 31 of 32 ADV7844 Data Sheet NOTES I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08850-0-4/12(B) Rev. B | Page 32 of 32