Complete AV Front End ADV7850 Data Sheet Audio codec 24-bit, 48 kHz stereo codec 5-channel stereo analog input mux with a stereo output General Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function support for dual input detection Simultaneous analog processing and HDMI monitoring for fast input switching APPLICATIONS HDTVs, set-top boxes, AV receivers, projectors, video matrix switchers FUNCTIONAL BLOCK DIAGRAM DDR2 SDRAM CVBS × 2/YC CVBS YC YPbPr GRAPHICS RGB AUDIO L/R 5 AUDIO L/R AUDIO L/R CVBS ADC ADC ADC ADC SDP CVBS 3D COMB SCART B YC SCART SCART R HS/VS/DE SCART G CLK DATA HDMI Tx SCART RGB + CVBS VIDEO INPUT MUX CP YPbPr 525p/625p Pb/B 720p/1080i 1080p/ UXGA Pb/R RGB Y/G HDMI HS/VS/DE CLK DATA ADC I2S INTERFACE DAC HP L/R TMDS DDC HDMI 2 TMDS DDC HDMI 3 HDMI 4 ARC 4 5V HDMI + VGA 5 TMDS DDC TMDS DDC 36 4 I2S S/PDIF DEEP COLOR HDMI Rx DSD/DST HBR MCLK FAST SWITCH HDCP KEYS SCLK 5 MCLK SCLK S/PDIF ARC 5V EDID REG AUDIO OUTPUT SPI INTERFACE EDID EPROM ADV7850 07758-001 HDMI 1 OUTPUT MUX Main features 4-port HDMI Xpressview receiver 170 MHz video and graphics digitizer Complete 3D comb video decoder Stereo audio codec High speed serial output (TMDS) HDMI support 3D TV support Audio return channel (ARC) Extended colorimetry, including sYCC601, Adobe RGB, Adobe YCC 601, and xvYCC extended gamut color 4:1 HDMI 297 MHz receiver Fast switching of HDMI ports (Xpressview) 3D TV video format support HDCP 1.4 support with internal HDCP keys Adaptive HDMI equalizer Full HDCP repeater support S/PDIF interface for 4 single-mode ARC outputs Up to 36-bit Deep Color support Complete HDMI audio support Audio extraction available Support for up to 16 VSIs (including THX Media Director™) High speed serial output (TMDS 297 MHz) Full transmitter support including encryption Can operate in a transceiver configuration Audio insertion available Video and graphics digitizer Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA) SD, ED, and HD TV support up to 1080p at 60 Hz Low refresh rates (24 Hz/25 Hz/30 Hz) support for 720p/1080p 13-channel analog video input channels with 2 outputs 3D comb video decoder Full NTSC/PAL/SECAM color standards support Adaptive 3D comb filter video decoder Advanced time-base correction (TBC) with frame synchronization for SD formats Complete SCART support Advanced VBI data slicer IF compensation filters AUDIO IN MUX FEATURES Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. ADV7850 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up Sequence ................................................................... 24 Applications ....................................................................................... 1 Power-Down Sequence.............................................................. 24 Functional Block Diagram .............................................................. 1 Power Supply requirements ...................................................... 24 Revision History ............................................................................... 2 Functional Overview...................................................................... 25 General Description ......................................................................... 3 HDMI Receiver........................................................................... 25 Detailed Functional Block Diagram .............................................. 4 Analog Front End ....................................................................... 25 Specifications..................................................................................... 5 Standard Definition Processor ................................................. 26 Electrical Characteristics ............................................................. 5 Component Processor ............................................................... 26 Power Specifications .................................................................... 6 VBI Data Processor (VDP) ....................................................... 27 Analog Specifications ................................................................... 7 TMDS Output ............................................................................. 27 Video Specifications ..................................................................... 9 External Memory Requirements .............................................. 27 Timing Characteristics .............................................................. 10 Other Features ............................................................................ 27 Timing Diagrams........................................................................ 11 Audio Overview.............................................................................. 28 Absolute Maximum Ratings .......................................................... 13 Analog Audio MUX Functionality .......................................... 28 Package Thermal Performance ................................................. 13 Audio Codec Functionality ....................................................... 28 ESD Caution ................................................................................ 13 Register Map Architecture ............................................................ 29 Pin Configuration and Function Descriptions ........................... 14 Outline Dimensions ....................................................................... 30 Power Supply Sequencing .............................................................. 24 Ordering Guide .......................................................................... 30 REVISION HISTORY 5/12—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet ADV7850 GENERAL DESCRIPTION The ADV7850 is a high quality, single chip, multiformat video decoder graphics digitizer with an integrated 4:1 multiplexed HDMI® receiver. This multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of a composite or an S-Video input signal into a HDMI output stream. SCART and overlay functionality are enabled by the ability of the ADV7850 to process CVBS and standard definition RGB signals simultaneously. The ADV7850 contains one main component processor (CP) that processes YPrPb and RGB component formats, including RGB graphics. The ADV7850 can operate in quad HDMI and analog input mode, thus allowing for fast switching between the analog video inputs and HDMI. The ADV7850 supports the decoding of a component RGB/ YPrPb video signal into a HDMI output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other SMPTE and HD standards. The ADV7850 supports graphics digitization. The ADV7850 is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into an HDMI output stream. Internal EDID RAM is available for one graphics port. The ADV7850 incorporates a quad input HDMI-compatible receiver that supports all HDTV formats up to 3D 1080p 60 Hz and 2160P 24 Hz. The ADV7850 supports full HDCP decryption with internal key storage. The ADV7850 features HDCP authentication on all ports simultaneously. The feature allows fast switching between HDMI ports. Sync measurements and status monitoring are also available for all HDMI ports. Each HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, such as a mute flag, that prevents audible extraneous noise in the audio output. In addition, the HDMI receiver incorporates internal EDID support, which can be made available in full power, powerdown, and power-off modes. An internal regulator supplies external EDID memory from the HDMI 5 V signal in poweroff mode. The ADV7850 incorporates Xpressview™ fast switching on all HDMI input ports. Using the Analog Devices, Inc., hardwarebased HDCP engine that minimizes software overhead, Xpressview technology allows fast switching between any two HDMI input ports in less than 1 second. The ADV7850 offers a flexible audio output port for the audio data decoded from the HDMI stream. HDMI audio formats, including super audio CD (SACD) via DSD, DST, and HBR are supported. The ADV7850 also features the single mode audio return channel (ARC) feature. ARC simplifies cabling by combining upstream audio capability in a conventional HDMI cable. The stereo audio ADC converts analog audio inputs and provides the data to the back end via the HDMI interface. The stereo audio DAC receives I2S data from the back end and converts it to analog audio output. The audio output is available as both high impedance and a driven output, which is suitable for driving headphones directly. Fabricated in an advanced CMOS process, the ADV7850 is provided in a 19 mm × 19 mm, 425-ball, CSP_BGA, surfacemount, RoHS-compliant package, and is specified over the −20°C to +70°C temperature range. Rev. 0 | Page 3 of 32 Rev. 0 | Page 4 of 32 CLAMP CLAMP CLAMP SPI INTERFACE SERIALIZER TMDS DRIVERS Figure 2. Detailed Functional Block Diagram HP_L/R_OUT DAC ADC AC_MCLK AUDIO_L/R_OUT DAC_L/R_OUT 5-CHANNEL STEREO INPUT MATRIX AUDIO_L/R_1 AUDIO_L/R_2 AUDIO_L/R_3 AUDIO_L/R_4 AUDIO_L/R_5 AC_SCLK AC_LRCLK AC_SDI HA_MCLK HA_SCLK HA_P2 HA_P3 HA_P4 HA_P5 SPDIF_IN SAMPLER SAMPLER AUDIO RETURN CHANNEL (SINGLE MODE ONLY) HA_P0 HA_P1 TTX_SPI HPD DDC_SDA DDC_SCL TX_C± TX_0± TX_1± TX_2± ARC_A ARC_B ARC_C ARC_D AUDIO PROCESSOR HDCP EEPROM HDCP BLOCK HDMI ENCODER HDMI TX PLL INT1 INT2 INT3 EQUALIZER AUDIO PLL VBI DATA FORMATTER ACTIVE PEAK AND HSYNC DEPTH OFFSET ADDER COLOR SPACE CONVERSION GAIN CONTRO L NOISE AND CALIBR ATION DIGITAL FINE CLAM P I2C READBACK VIDEO DATA PROCESSOR VBI DECODER PROGRAMMABLE DELAY STANDARD IDENTIFICATION FASTBLANK OVERLAY CONTROL INTERRUPT CONTROLLER RXD_0± RXD_1± RXD_2± I2S PACKET/ INFOFRAME MEMORY (A) (B) (C) MACROVISION AND CGMS DETECTION SYNC SOURCE AND POLARITY DETECT COMPONENT PROCESSOR (CP) DDR2 SDRAM INTERFACE COLOR CONTROL 2D COMB EQUALIZER PACKET PROCESSOR PARAMETER EXTRACTION HDMI PROCESSOR (D) (C) (B) (A) (D) CTI AND LTI MACROVISION DETECTION HORIZONTAL PEAKING (C) (B) 3D COMB STANDARD AUTODECTION TBC VERTICAL PEAKING (A) STANDARD DEFINITION PROCESSOR (SDP) RXC_0± RXC_1± RXC_2± SAMPLER SAMPLER HDCP BLOCK HDCP EEPROM HS/CS, VS/FIELD 12 12 12 CONTROL AND DATA ADC3 ADC2 ADC1 12 PROGRAMMABLE DECIMATION FILTERS EQUALIZER EQUALIZER PLL EDID/ REPEATER CONTROLLER 5V DETECT, HPA CONTROLLER AND 5V REGULATOR I2C CONTROL INTERFACE TRI-LEVEL SLICER SYNC PROCESSING AND CLOCK GENERATION 13-CHANNEL INPUT MATRIX ADC0 VIDEO OUTPUT FORM ATTER RXB_0± RXB_1± RXB_2± RXA_C± RXB_C± RXC_C± RXD_C± RXA_0± RXA_1± RXA_2± VGA_SDA/VGA_SCL DDCA_SDA/DDCA_SCL DDCB_SDA/DDCB_SCL DDCC_SDA/DDCC_SCL DDCD_SDA/DDCD_SCL +3.3V_EPROM SPI_EPROM RXA_5V/HPAA RXB_5V/HPAB RXC_5V/HPAC RXD_5V/HPAD SCL SDA TRI1 TO TRI8 SYNC1 SYNC2 SYNC3 HS_IN VS_IN RGB YPrPb SCART RGB YC CVBS CLAMP FAST SWITCHING BLOCK + HDMI DECODE + MUX ANALOG FRONT END AUDIO OUTPUT FORM ATTER VIDEO_OUT_1 VIDEO_OUT_2 ADV7850 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM 07758-A002 Data Sheet ADV7850 SPECIFICATIONS AVDD = 1.8 V ± 5%, VDD to GND = 1.8 V ± 5%, PVDD = 1.8 V ± 5%, TX_AVDD = 1.8 V ± 5%, TX_PVDD = 1.8 V ± 5%, SAVDD = 1.8 V ± 5%, SDVDD = 1.8 V ± 5%, CVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, TX_VDD33 = 3.3 V ± 5%, TVDD = 3.3 V ± 5%, AC_AVDD = 3.3 V ± 5%. TMIN to TMAX = −20°C to +70°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Capacitance HDMI TMDS Differential Pin Capacitance DIGITAL INPUTS (5 V TOLERANT) 1 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Symbol N INL DNL VIH VIL VIH VIL CIN 1 Min 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 74.25 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 75 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) XTALN and XTALP pins XTALN and XTALP pins Other digital inputs Other digital inputs Typ Max Unit 12 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB −3.0 to +8.0 −3.0 to +8.0 −4.0 to +7.0 −3.5 to +8.0 −0.7 to +1.8 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.6 to +0.5 1.2 0.4 2 0.8 10 0.3 VIH VIL IIN 3.0 VOH VOL ILEAK 2.4 ILEAK Output Capacitance Test Conditions/Comments ILEAK COUT pF 0.8 +82 −82 V V µA 30 V V µA 20 µA 0.4 DDC_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, VGA_SCL, VGA_SDA, SPDIF_IN, SHARED_EDID RXA_5V, RXB_5V, RXC_5V, RXD_5V and VGA_5V All other digital pins V V V V pF 10 20 µA pF The following pins are 5 V tolerant: HS_IN1/TRI7, HS_IN2/TRI5, VS_IN1/TRI8, VS_IN2/TRI6, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, VGA_SCL, VGA_SDA, TX_DDC_SCL, TX_DDC_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V, and VGA_5V. Rev. 0 | Page 5 of 32 ADV7850 Data Sheet POWER SPECIFICATIONS Table 2. Parameter POWER REQUIREMENTS Digital Core Power Supply Digital I/O Power Supply Memory Interface Analog Power Supply Memory Interface Digital Power Supply DPLL Power Supply Video Analog Power Supply Terminator Power Supply Comparator Power Supply Audio Block Supply HDMI Tx Analog Power Supply HDMI Tx Digital Power Supply HDMI Tx PLL Regulator Power Supply CURRENT CONSUMPTION 1, 2, 3 Digital Core Supply Current Digital I/O Supply Current DPLL Supply Current Video Analog Supply Current Memory Interface Analog Power Supply Memory Interface Digital Power Supply Comparator Supply Current Audio Block Supply Current HDMI Tx Analog Supply Current HDMI Tx Digital Supply Current HDMI Tx PLL Regulator Supply Current Terminator Supply Current 4 Power-Down Currents 5 Power-Up Time Symbol Min Typ Max Unit VDD DVDDIO SAVDD SDVDD PVDD AVDD TVDD CVDD AC_AVDD TX_AVDD TX_PVDD TX_VDD33 1.75 3.14 1.71 1.71 1.71 1.71 3.14 1.71 3.14 1.71 1.71 3.14 1.8 3.3 1.8 1.8 1.8 1.8 3.3 1.8 3.3 1.8 1.8 3.3 1.85 3.46 1.89 1.89 1.89 1.89 3.46 1.89 3.46 1.89 1.89 3.46 V V V V V V V V V V V V 400 3 36 270 4 15 300 80 20 43 2 80 280 1 1.5 0.5 0.5 0.5 0.5 0.5 0.5 1 2.5 0.5 0.5 25 440 4 45 290 5 18 350 84 25 50 5 85 290 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ms IVDD IDVDDIO IPVDD IAVDD ISAVDD ISDVDD ICVDD IAC_AVDD ITX_AVDD ITX_PVDD ITX_VDD33 ITVDD IVDD IDVDDIO IPVDD IAVDD ISAVDD ISDVDD ITVDD ICVDD IAC_AVDD ITX_AVDD ITX_PVDD ITX_VDD33 tPWRUP 1 Test Conditions/Comments One port connected Four ports connected All maximum current values are guaranteed by characterization to assist in power supply design. Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature. Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature. 4 Termination power supply includes TVDD current consumed off chip. 5 Power-down mode entered by setting the I2C Bit POWER_DOWN high. 2 3 Rev. 0 | Page 6 of 32 Data Sheet ADV7850 ANALOG SPECIFICATIONS Table 3. Parameter CLAMP CIRCUITRY 1 Input Impedance Analog (AIN1 to AIN12) ADC Midscale (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current AUDIO ADC SECTION 2 Number of Channels Full-Scale Input Level Resolution Dynamic Range (Stereo Channel) A-Weighted Total Harmonic Distortion + Noise (Stereo Channel) Gain Mismatch Crosstalk (Left to Right, Right to Left) Gain Error Power Supply Rejection AUDIO ADC DIGITAL DECIMATOR FILTER CHARACTERISTICS2 Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay AUDIO DAC SECTION2 Number of Auxiliary Output Channels Resolution Full-Scale Analog Output Dynamic Range A-Weighted Total Harmonic Distortion + Noise Test Conditions/Comments Min Typ Max Unit Clamps switched off 10 MΩ Component input, Y signal Component input, Pr signal Component input, Pb signal PC RGB input (R, G, B signals) CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) SDP only SDP only SDP only SDP only 0.91 CML + 0.55 CML − 0.55 1.1 CML − 0.12 CML CML CML − 0.12 CML − 0.205 CML − 0.205 CML − 0.205 CML 0.3 0.4 9 8 V V V V V V V V V V V V mA mA μA μA Stereo pair 1 50 24 Channel µA rms Bits −60 dBFS with respect to full-scale analog input −3 dBFS with respect to full-scale analog input Left- and right-channel gain mismatch 90 dB −85 dB 0.2 dB −90 −1.1 −89 dB dB dB 22.5 ±0.0002 26.5 100 1040 kHz dB kHz dB µs Stereo pair 1 24 1.0 Channel Bits V rms −60 dBFS with respect to fullscale code input −3 dBFS with respect to full-scale code input 93 dB −89 dB Input signal = 2.8 V rms 1 kHz, 300 mV p-p signal at AVDD At 48 kHz, guaranteed by design Rev. 0 | Page 7 of 32 ADV7850 Parameter Crosstalk (Left to Right, Right to Left) Interchannel Gain Mismatch Gain Error Power Supply Rejection AUDIO DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS2 Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay HEADPHONE AMPLIFIER2 Number of Channels Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Power Supply Rejection ANALOG AUDIO MUX2 Number of Input Channels Number of Output Channels Gain Mismatch Between Left and Right Channels REFERENCE SECTION Absolute Voltage VREF 1 2 Data Sheet Test Conditions/Comments Left- and right-channel gain mismatch 1 V rms output 1 kHz, 300 mV p-p signal at AVDD At 48 kHz, guaranteed by design Measured at headphone output with 32 Ω load Stereo pair −60 dBFS with respect to fullscale code input −3 dBFS with respect to full-scale code input 1 kHz, 300 mV p-p signal at AVDD Stereo pair Stereo pair Specified for external clamp capacitor of 100 nF. Guaranteed by lab characterization. Rev. 0 | Page 8 of 32 Min Typ −104 0.1 Max Unit dB dB 0.525 −101 dB dB 21.769 ±0.01 23.95 26.122 75 580 kHz dB kHz kHz dB µs 1 Channel 92 dB −86 dB 0.1 −82 dB dB 5 1 ±5 Channel Channel % 1.5 V Data Sheet ADV7850 VIDEO SPECIFICATIONS Table 4. Parameter NONLINEAR SPECIFICATIONS 1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS1 SNR Unweighted SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS (SDP) 2 Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range Color Lock-In Time Sync Depth Range Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS (SDP)1 Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation 1 2 Symbol Test Conditions/Comments DP DG LNL CVBS input (modulated five-step) CVBS input (modulated five-step) CVBS input (modulated five-step) Measured at 27 MHz LLC Luma ramp Luma flat field Min Typ Max 0.5 0.6 0.9 Degrees % % 59 60 60 dB dB dB ±5 300 100 % Hz kHz Lines % % ms Lines 0.9 0.3 0.6 % Degrees % 40 fSC 70 ±0.8 60 20 1 Guaranteed by lab characterization. Guaranteed by design. Rev. 0 | Page 9 of 32 Unit 200 200 ADV7850 Data Sheet TIMING CHARACTERISTICS Data, SPI, and I2C Timing Characteristics Table 5. Parameter CLOCK AND CRYSTAL Crystal Frequency Crystal Frequency Stability 2 I C PORT1 SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time RESET FEATURE Reset Pulse Width HDMI AUDIO I2S PORT, MASTER MODE HA_SCLK Mark-Space Ratio LRCLK2 Data Transition Time 2 3 Test Conditions/Comments Min Typ Max Unit ±50 MHz ppm 27 See Figure 3 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 kHz ns μs ns ns ns ns ns μs 5 ms 600 1.3 600 600 100 1000 300 See Figure 4 t15:t16 t17 LRCLK2 Data Transition Time t18 I2Sx3 Data Transition Time t19 I2Sx3 Data Transition Time t20 AUDIO CODEC MASTER CLOCK AC_MCLK Frequency Range AC_MCLK Frequency SPI READ AND WRITE OPERATIONS1 SCLK Frequency Master Mode TTX_SCLK Falling Edge to CS/TTX_MOSI Valid TTX_MISO Setup Time TTX_MISO Hold Time Slave Mode CS Falling Edge to TTX_SCLK Rising Edge TTX_SCLK Falling Edge to CS Rising Edge TTX_MOSI Setup Time TTX_MOSI Hold Time TTX_SCLK Falling Edge to CS/MOSI Valid 1 Symbol 45:55 End of valid data to negative HA_SCLK edge Negative HA_SCLK edge to start of valid data End of valid data to negative HA_SCLK edge Negative HA_SCLK edge to start of valid data fMCLK fMCLK 4.096 128 × fS 45:55 2 % duty cycle ns 2 ns 2 ns 2 ns 24.576 MHz Hz See Figure 5, Figure 7, and Figure 8 13.5 t21, t22 3.0 t23 t24 MHz 4.1 15.3 2.1 ns ns ns t25, t26 4.0 ns t27, t28 4.0 ns t29 t30 t31, t32 1.8 2.7 7.3 Guaranteed by design. LRCLK is a signal accessible via HA_AP5. I2Sx are signals accessible via Ball HA_AP1 to Ball HA_AP4. Rev. 0 | Page 10 of 32 15.5 ns ns ns Data Sheet ADV7850 TIMING DIAGRAMS t3 t5 t3 SDA t6 t1 t2 t7 t4 07758-003 SCL t8 2 Figure 3. I C Timing t15 HA_SCLK t16 t17 LRCLK t18 t19 I2Sx LEFT-JUSTIFIED MODE MSB MSB – 1 t20 I2Sx I2S MODE t19 MSB MSB – 1 t20 I2Sx RIGHT-JUSTIFIED MODE t19 MSB LSB t20 07758-004 NOTES 1. THE SUFFIX x REFERS TO THE I2S OUTPUT 0, 1, 2, 3. 2. LRCLK IS A SIGNAL ACCESSIBLE VIA HA_AP5 BALL. 3. I2Sx ARE SIGNALS ACCESSIBLE VIA HA_AP1 TO HA_AP4 BALL. Figure 4. HDMI Audio I2S Timing t21 t22 t23 t24 TTX_SCLK TTX_MOSI 07758-007 TTX_CS TTX_MISO Figure 5. SPI Master Mode Timing Rev. 0 | Page 11 of 32 ADV7850 Data Sheet TTX_CS TTX_SCLK 24-BIT ADDRESS TTX_MOSI 23 22 21 ... 3 2 DUMMY BYTE 1 0 7 6 5 4 3 2 1 0 DATA OUT 1 TTX_MISO 7 6 5 4 3 2 DATA OUT 2 1 0 7 6 5 4 3 2 1 0 07758-008 INSTRUCTION (0x0B) Figure 6. SPI Master Mode Overview t29 t31 t30 t32 TTX_SCLK TTX_MOSI 07758-009 TTX_CS TTX_MISO Figure 7. SPI Slave Mode Timing t27 t25 t28 t26 0 0 TTX_SCLK 0 1 TTX_SCLK 1 0 TTX_SCLK 1 1 TTX_SCLK W/R DEVICE ADDRESS TTX_MOSI 7 6 5 4 3 2 1 0 DUMMY BYTE TTX_MISO DATA OUT 0 7 6 5 4 3 2 Figure 8. SPI Slave Mode Overview Rev. 0 | Page 12 of 32 1 0 07758-010 CPCL CPHA CS Data Sheet ADV7850 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 6. Parameter AVDD to GND VDD to GND PVDD to GND TX_AVDD to GND TX_PVDD to GND SAVDD to GND SDVDD to GND CVDD to GND DVDDIO to GND TVDD to GND AC_AVDD to GND Maximum Difference Across All 1.8 V Supplies Maximum Difference Across All 3.3 V Supplies Maximum Difference Between 3.3 V Domain Supplies and 1.8 V Domain Supplies Digital Inputs Voltage to GND Digital Outputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Analog Inputs to GND XTALN and XTALP to GND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 To reduce power consumption when using the ADV7850, the user is advised to turn off unused sections of the part. Rating 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 4.0 V 4.0 V 4.0 V −0.3 V to +0.3 V Due to PCB metal variation, and, therefore, variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): ( TJ = TS + Ψ JT × WTOTAL −0.3 V to +0.3 V ) where: TS is the package surface temperature (°C). ΨJT = 0.7°C/W for the 425-ball CSP_BGA. −0.3 V to +2.2 V −0.3 V to DVDDIO + 0.3 V −0.3 V to DVDDIO + 0.3 V 5.5 V −0.3V to AVDD + 0.3 V−0.3V to AC_AVDD + 0.3 V −0.3 V to PVDD + 0.3 V 125°C −65°C to +150°C 260°C WTOTAL = (PVDD × IPVDD) + (0.4 × TVDD × ITVDD) + (CVDD × ICVDD) + (AVDD × IAVDD) + (VDD × IVDD) + (DVDDIO × IDVDDIO) + (TX_AVDD × ITX_AVDD) + (TX_PVDD × ITX_PVDD) + (SAVDD × ISAVDD) + (SDVDD × ISDVDD) + (TX_VDD33 × ITX_VDD33) + (AC_AVDD × IAC_AVDD) where 0.4 reflects the 40% of TVDD power that is dissipated on the part itself. ESD CAUTION The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI7, HS_IN2/TRI5, VS_IN1/TRI8, VS_IN2/TRI6, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, VGA_SCL, VGA_SDA, TX_DDC_SCL, TX_DDC_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V and VGA_5V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 13 of 32 ADV7850 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A GND GND GND RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_B TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ ARC_C GND RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_D GND GND GND B ARC_A HPA_A GND RXB_2– RXB_1– RXB_0– RXB_C– HPA_B TVDD RXC_2– RXC_1– RXC_0– RXC_C– HPA_C GND RXD_2– RXD_1– RXD_0– RXD_C– HPA_D GND ACMUXO ACMUXO UT_R UT_L B GND ACMUXIN ACMUXIN _1R _1L C AC_AVDD AC_AVDD AC_AVDD ACMUXIN ACMUXIN _2R _2L D C RXA_C+ RXA_C– CVDD GND GND GND GND VDD_EEP ROM D RXA_0+ RXA_0– CVDD RXD_5V VGA_5V DDCA_ SCL DDCA_ SDA DDCB_ SCL E RXA_1+ RXA_1– CVDD RXC_5V GND GND ACMUXIN ACMUXIN _3R _3L E F RXA_2+ RXA_2– CVDD RXB_5V PLL_LF GND ACMUXIN ACMUXIN _4R _4L F G TVDD TVDD TVDD TVDD AC_AVDD GND ACMUXIN ACMUXIN _5R _5L G H J H J K GND EP_MISO EP_MOSI SPDIF_IN RXA_5V EP_CS GND EP_SCK GND SHARED_ RESET EDID TEST1 TVDD TVDD TVDD TVDD TVDD TVDD GND DDCB_ SDA DDCC_ SCL DDCC_ SDA DDCD_ SCL DDCD_ SDA VREG GND CVDD CVDD CVDD CVDD CVDD CVDD CVDD TVDD TVDD VGA_SCL VGA_SDA GND TVDD TVDD TVDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FILTA VREF_AU DIO GND GND GND GND GND GND GND GND GND GND GND AC_AVDD GND ISET FILTD K L DVDDIO DVDDIO VDD GND GND GND GND GND GND GND GND GND GND AC_ AC_ AC_AVDD AC_AVDD DACOUT_ DACOUT_ R L INT1 SDA VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD AC_AVDD HPOUT_R HPOUT_L INT2 SCL VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD GND GND GND M L HA_AP5 HA_SCLK M HA_AP4 HA_AP3/ INT3 N HA_AP2 AC_ HA_AP1 AC_MCLK LRCLK VDD GND GND GND GND GND GND GND GND GND GND PVDD PVDD XTALN XTALP N P HA_AP0 HA_MCLK AC_SDI AC_SCLK OUT VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND P R TTX_ SCLK TTX_ MOSI TTX_ MISO TTX_CS VDD GND GND GND GND GND GND GND GND GND GND GND GND REFN REFP R T DVDDIO DVDDIO GND GND VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AVDD AVDD T GND TX_DDC_ SCL VDD VDD VDD VDD VDD VDD VDD TEST2 GND GND GND AVIN13 AVIN12 AVIN11 AVIN10 U U TX_AVDD TX_AVDD V TX_2+ TX_2– GND TX_DDC_ SDA AVDD AVDD AVDD AVDD V W TX_1+ TX_1– GND TX_HPD GND AVOUT2 AVIN9 AVIN8 W Y TX_0+ TX_0– GND GND GND AVOUT1 SYNC3 AVIN7 Y VS_IN2/ TRI6 AA A7 A3 A10 BA0 CKE GND DQ6 DQ7 DQ0 DQ8 UDQS SDVDD SAVDD TRI1 TRI2 VS_IN1/ TRI8 GND TRI3 HS_IN2/ TRI5 TX_ AVDD GND A9 A5 A1 BA1 WE GND DQ4 DQ5 DQ2 DQ11 UDQSN SDVDD GND HS_IN1/ TRI7 TX_ PVDD TX_ PLVDD SDVDD A11 A6 A2 CAS RAS VREF SDVDD LDQSN DQ3 DQ10 DQ12 DQ14 GND SYNC1 AVIN3 GND SYNC2 AVIN6 TRI4 AB GND TX_ RTERM TX_ VDD33 SDVDD A8 A4 A0 CS CKN CK SDVDD LDQS DQ1 DQ9 DQ15 DQ13 GND AVIN1 AVIN2 GND AVIN4 AVIN5 GND AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AA TX_C+ AB GND AC TX_C– Figure 9. Pin Configuration Rev. 0 | Page 14 of 32 07758-011 A Data Sheet ADV7850 Table 7. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 Mnemonic GND GND GND RXB_2+ RXB_1+ RXB_0+ RXB_C+ ARC_B TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ ARC_C GND RXD_2+ RXD_1+ RXD_0+ RXD_C+ ARC_D GND GND GND ARC_A HPA_A GND RXB_2− RXB_1− RXB_0− RXB_C− HPA_B TVDD RXC_2− RXC_1− RXC_0− RXC_C− HPA_C GND RXD_2− RXD_1− RXD_0− RXD_C− HPA_D GND ACMUXOUT_R ACMUXOUT_L RXA_C+ RXA_C− CVDD GND GND GND Description Ground. Ground. Ground. Digital Input Channel 2 True of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI interface. Single-Ended Audio Return Channel of Port B in the HDMI Interface. HDMI Termination Supply (3.3 V). Digital Input Channel 2 True of Port C in the HDMI Interface. Digital Input Channel 1 True of Port C in the HDMI Interface. Digital Input Channel 0 True of Port C in the HDMI Interface. Digital Input Clock True of Port C in the HDMI Interface. Single-Ended Audio Return Channel of Port C in the HDMI Interface. Ground. Digital Input Channel 2 True of Port D in the HDMI Interface. Digital Input Channel 1 True of Port D in the HDMI Interface. Digital Input Channel 0 True of Port D in the HDMI Interface. Digital Input Clock True of Port D in the HDMI Interface. Single-Ended Audio Return Channel of Port D in the HDMI Interface. Ground. Ground. Ground. Single-Ended Audio Return Channel of Port A in the HDMI Interface. Hot Plug Assert for Port A. Ground. Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Clock Complement of Port B in the HDMI Interface. Hot Plug Assert for Port B. HDMI Termination Supply (3.3 V). Digital Input Channel 2 Complement of Port C in the HDMI Interface. Digital Input Channel 1 Complement of Port C in the HDMI Interface. Digital Input Channel 0 Complement of Port C in the HDMI Interface. Digital Input Clock Complement of Port C in the HDMI Interface. Hot Plug Assert for Port C. Ground. Digital Input Channel 2 Complement of Port D in the HDMI Interface. Digital Input Channel 1 Complement of Port D in the HDMI Interface. Digital Input Channel 0 Complement of Port D in the HDMI Interface. Digital Input Clock Complement of Port D in the HDMI Interface. Hot Plug Assert for Port D. Ground. Audio Codec Mux Output Right Channel. Audio Codec Mux Output Left Channel. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Clock Complement of Port A in the HDMI Interface. HDMI Comparator Supply (1.8 V). Ground. Ground. Ground. Rev. 0 | Page 15 of 32 ADV7850 Pin No. C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 Mnemonic GND VDD_EEPROM TVDD TVDD TVDD TVDD TVDD TVDD GND TVDD TVDD TVDD TVDD GND GND ACMUXIN_1R ACMUXIN_1L RXA_0+ RXA_0− CVDD RXD_5V VGA_5V DDCA_SCL DDCA_SDA DDCB_SCL DDCB_SDA DDCC_SCL DDCC_SDA DDCD_SCL DDCD_SDA VREG GND VGA_SCL VGA_SDA TVDD AC_AVDD AC_AVDD AC_AVDD ACMUXIN_2R ACMUXIN_2L RXA_1+ RXA_1− CVDD RXC_5V GND GND ACMUXIN_3R ACMUXIN_3L RXA_2+ RXA_2− CVDD RXB_5V PLL_LF Data Sheet Description Ground. External EDID EEPROM Power Supply. HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). Ground. HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). Ground. Ground. Audio Codec Mux Input 1 Right Channel. Audio Codec Mux Input 1 Left Channel. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. HDMI Comparator Supply (1.8 V). 5 V Detect Pin for Port D in the HDMI Interface. 5 V Detect I/O for VGA Connector. Serial Clock for DDC Bus of Port A. DDCA_SCL is 5 V tolerant. Serial Data for DDC Bus of Port A. DDCA_SDA is 5 V tolerant. Serial Clock Port for DDC Bus of Port B. DDCB_SCL is 5 V tolerant. Serial Data Port for DDC Bus of Port B. DDCB_SDA is 5 V tolerant. Serial Clock Port for DDC Bus of Port C. DDCC_SCL is 5 V tolerant. Serial Data Port for DDC Bus of Port C. DDCC_SDA is 5 V tolerant. Serial Clock Port for DDC Bus of Port D. DDCD_SCL is 5 V tolerant. Serial Data Port for DDC Bus of Port D. DDCD_SDA is 5 V tolerant. Voltage Regulator Output. Must be decoupled to GND via 1 µF capacitor. Ground. Serial Clock for VGA Interface. VGA_SCL is 5 V tolerant. Serial Data for VGA Interface. VGA_SDA is 5 V tolerant. HDMI Termination Supply (3.3 V). Audio Block Supply (3.3 V). Audio Block Supply (3.3 V). Audio Block Supply (3.3 V). Audio Codec Mux Input 2 Right Channel. Audio Codec Mux Input 2 Left Channel. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. HDMI Comparator Supply (1.8 V). 5 V Detect Pin for Port C in the HDMI Interface. Ground. Ground. Audio Codec Mux Input 3 Right Channel. Audio Codec Mux Input 3 Left Channel. Digital Input Channel 2 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. HDMI Comparator Supply (1.8 V). 5 V Detect Pin for Port B in the HDMI Interface. Loop Filter Ball for Audio Codec PLL. Rev. 0 | Page 16 of 32 Data Sheet Pin No. F21 F22 F23 G1 G2 G3 G4 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G20 G21 G22 G23 H1 H2 H3 H4 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H20 H21 H22 H23 J1 J2 J3 J4 J7 J8 J9 J10 J11 J12 J13 J14 Mnemonic GND ACMUXIN_4R ACMUXIN_4L TVDD TVDD TVDD TVDD GND TEST1 CVDD CVDD CVDD CVDD CVDD CVDD CVDD GND GND AC_AVDD GND ACMUXIN_5R ACMUXIN_5L EP_MISO EP_MOSI SPDIF_IN RXA_5V GND GND GND GND GND GND GND GND GND GND GND GND GND FILTA VREF_AUDIO EP_CS EP_SCK SHARED_EDID RESET GND GND GND GND GND GND GND GND ADV7850 Description Ground. Audio Codec Mux Input 4 Right Channel. Audio Codec Mux Input 4 Left Channel. HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). HDMI Termination Supply (3.3 V). Ground. Test Pin. Do not connect. HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). HDMI Comparator Supply (1.8 V). Ground. Ground. Audio Block Supply (3.3 V). Ground. Audio Codec Mux Input 5 Right Channel. Audio Codec Mux Input 5 Left Channel. External EDID EEPROM Interface. External EDID EEPROM Interface. S/PDIF Digital Audio Input for Audio Return Channel (ARC). 5 V Detect Pin for Port A in the HDMI Interface. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Audio Codec ADC Filter Capacitor. Audio Codec Block Reference Voltage Capacitor. External EDID EEPROM Interface. External EDID EEPROM Interface. EDID Selection Signal for HDMI Port D. Chip Reset. Active low. Minimum low time guarantee reset is 5 ms. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Rev. 0 | Page 17 of 32 ADV7850 Pin No. J15 J16 J17 J20 J21 J22 J23 K1 K2 K3 K4 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K20 K21 K22 K23 L1 L2 L3 L4 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L20 L21 L22 L23 M1 M2 Mnemonic GND GND GND AC_AVDD GND ISET FILTD GND GND DVDDIO DVDDIO VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD AC_AVDD AC_DACOUT_R AC_DACOUT_L HA_AP5 HA_SCLK INT1 SDA VDD GND GND GND GND GND GND GND GND GND GND AC_AVDD AC_AVDD HPOUT_R HPOUT_L HA_AP4 HA_AP3/INT3 M3 M4 M7 M8 M9 INT2 SCL VDD GND GND Data Sheet Description Ground. Ground. Ground. Audio Block Supply (3.3 V). Ground. Audio Codec ADC Current Settings. Audio Codec DAC Filter Capacitor. Ground. Ground. I/O Supply (3.3 V). I/O Supply (3.3 V). Video Digital Supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Audio Block Supply (3.3 V). Audio Block Supply (3.3 V). Audio Codec DAC Output Right Channel. Audio Codec DAC Output Left Channel HDMI Audio Port Output. HDMI Audio Port Serial Clock Output. External Interrupt 1. I2C Port Serial Data Input/Output. Video Digital Supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Audio Block Supply (3.3 V). Audio Block Supply (3.3 V). Headphone Output Right Channel. Headphone Output Left Channel. HDMI Audio Port Output. HDMI Audio Port Output/External Interrupt 3. This pin can be configured as a TTL output interrupt pin for the VDP SPI interface. External Interrupt 2. I2C Port Serial Clock Input. Video Digital Supply (1.8 V). Ground. Ground. Rev. 0 | Page 18 of 32 Data Sheet Pin No. M10 M11 M12 M13 M14 M15 M16 M17 M20 M21 M22 M23 N1 N2 N3 N4 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N20 N21 N22 N23 P1 P2 P3 P4 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 R1 R2 R3 Mnemonic GND GND GND GND GND GND GND GND AC_AVDD GND GND GND HA_AP2 HA_AP1 AC_MCLK AC_LRCLK VDD GND GND GND GND GND GND GND GND GND GND PVDD PVDD XTALN XTALP HA_AP0 HA_MCLKOUT AC_SDI AC_SCLK VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND TTX_SCLK TTX_MOSI TTX_MISO ADV7850 Description Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Audio Block Supply (3.3 V). Ground. Ground. Ground. HDMI Audio Port Output. HDMI Audio Port Output. Audio Codec/DAC Clock Input. Audio DAC Left/Right Clock Input. Video Digital supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. DPLL Supply (1.8 V). DPLL Supply (1.8 V). Crystal Output. Crystal Input or External Clock Input. HDMI Audio Port Output. HDMI Audio Master Clock Output. Audio DAC Data Input. Audio DAC SCLK Input. Video Digital Supply (1.8 V). Ground. Ground. Ground. Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground VBI Data Interface. VBI Data Interface. VBI Data Interface. Rev. 0 | Page 19 of 32 ADV7850 Pin No. R4 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T20 T21 T22 T23 U1 U2 U3 U4 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U20 U21 U22 Mnemonic TTX_CS VDD GND GND GND GND GND GND GND GND GND GND GND GND REFN REFP DVDDIO DVDDIO GND GND VDD GND GND GND GND GND GND GND GND GND GND AVDD AVDD AVDD AVDD TX_AVDD TX_AVDD GND TX_DDC_SCL VDD VDD VDD VDD VDD VDD VDD TEST2 GND GND GND AVIN13 AVIN12 AVIN11 Data Sheet Description VBI Data Interface. Video Digital Supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Negative Analog Video Reference Output. Positive Analog Video Reference Output. I/O Supply (3.3 V). I/O Supply (3.3 V). Ground. Ground. Video Digital Supply (1.8 V). Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Ground. Video Analog Supply Voltage (1.8 V). Video Analog Supply Voltage (1.8 V). Video Analog Supply Voltage (1.8 V). Video Analog Supply Voltage (1.8 V). HDMI Tx Analog Supply (1.8 V). HDMI Tx Analog Supply (1.8 V). Ground. Serial Clock for DDC Bus of HDMI Tx. TX_DDCA_SCL is 5 V tolerant. Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Video Digital Supply (1.8 V). Test Pin. Do not connect. Ground. Ground. Ground. Analog Video Mux Input Channel. Analog Video Mux Input Channel. Analog Video Mux Input Channel. Rev. 0 | Page 20 of 32 Data Sheet ADV7850 Pin No. U23 V1 V2 V3 V4 V20 V21 Mnemonic AVIN10 TX_2+ TX_2− GND TX_DDC_SDA AVDD AVDD Description Analog Video Mux Input Channel. Digital Output Channel 2 True of the HDMI Tx. Digital Output Channel 2 Complement of the HDMI Tx. Ground. Serial Data for DDC Bus of HDMI Tx. TX_DDCA_SDA is 5 V tolerant. Video Analog Supply Voltage (1.8 V). Video Analog Supply Voltage (1.8 V). V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AVDD AVDD TX_1+ TX_1− GND TX_HPD GND AVOUT2 AVIN9 AVIN8 TX_0+ TX_0− GND GND A7 A3 A10 BA0 CKE GND DQ6 DQ7 DQ0 DQ8 UDQS SDVDD SAVDD TRI1 TRI2 GND AVOUT1 SYNC3 AVIN7 TX_C+ TX_C− TX_AVDD GND A9 A5 A1 BA1 WE GND DQ4 DQ5 DQ2 Video Analog Supply Voltage (1.8 V). Video Analog Supply Voltage (1.8 V). Digital Output Channel 1 True of the HDMI Tx. Digital Output Channel 1 Complement of the HDMI Tx. Ground. Hot Plug Detect Signal of the HDMI Tx. Ground. Analog Video Mux Output 2. Analog Video Mux Input Channel. Analog Video Mux Input Channel. Digital Output Channel 0 True of the HDMI Tx. Digital Output Channel 0 Complement of the HDMI Tx. Ground. Ground. SDRAM Address Line. SDRAM Address Line. SDRAM Address Line. SDRAM Block Address Signal. SDRAM Clock Enable. Ground. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. SDRAM Upper Data Strobe True Signal. Memory Interface Supply. SDRAM Interface Supply. Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. Ground. Analog Video Mux Output 1. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. Analog Video Mux Input Channel. Digital Output Clock True of the HDMI Tx. Digital Output Clock Complement of the HDMI Tx. HDMI Tx Analog Supply (1.8 V). Ground. SDRAM Address Line. SDRAM Address Line. SDRAM Address Line. SDRAM Block Address Signal. SDRAM Write Enable Signal. Ground. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. Rev. 0 | Page 21 of 32 ADV7850 Pin No. AA14 AA15 AA16 AA17 AA18 Mnemonic DQ11 UDQSN SDVDD GND HS_IN1/TRI7 AA19 VS_IN1/TRI8 AA20 AA21 AA22 GND TRI3 HS_IN2/TRI5 AA23 VS_IN2/TRI6 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 GND TX_PVDD TX_PLVDD SDVDD A11 A6 A2 CAS AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 RAS VREF SDVDD LDQSN DQ3 DQ10 DQ12 DQ14 GND SYNC1 AVIN3 GND SYNC2 AVIN6 TRI4 GND TX_RTERM TX_VDD33 SDVDD A8 A4 A0 CS AC9 CKN AC10 CK Data Sheet Description SDRAM Data Line. SDRAM Upper Data Strobe Complement Signal. Memory Interface Supply. Ground. HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or D-connector. VS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or D-connector. Ground. Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or D-connector. HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or D-connector. Ground. HDMI Tx Digital Supply (1.8 V). HDMI Tx PLL Digital Supply (1.8 V). It is important to ensure that this supply pin has a clean voltage input. Memory Interface Supply. SDRAM Address Line. SDRAM Address Line. SDRAM Address Line. SDRAM Interface Column Address Select Command Signal. One of four command signals to the external SDRAM. SDRAM Interface Row Address Select Command Signal. One of four command signals to the external SDRAM. Termination Reference Voltage for Memory Interface. Memory Interface Supply. SDRAM Lower Data Strobe Complement Signal. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. Ground. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. Analog Video Mux Input Channel. Ground. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. Analog Video Mux Input Channel. Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. Ground. This signal sets the internal termination resistance. A 500 Ωresistor between this ball and GND should be used. HDMI Tx PLL Regulator Supply Input (3.3V). This pin is an internal voltage regulator input. Memory Interface Supply. SDRAM Address Line. SDRAM Address Line. SDRAM Address Line. SDRAM Interface Chip Select. SDRAM CS enables and disables the command decoder on the RAM. One of four command signals to the external SDRAM. SDRAM Interface Differential Clock Compliment Output. All address and control output signals to the RAM should be sampled on the positive edge of CK and on the negative edge of CKN. SDRAM Interface Differential Clock Right Output. All address and control output signals to the RAM should be sampled on the positive edge of CK and on the negative edge of CKN. Rev. 0 | Page 22 of 32 Data Sheet Pin No. AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Mnemonic SDVDD LDQS DQ1 DQ9 DQ15 DQ13 GND AVIN1 AVIN2 GND AVIN4 AVIN5 GND ADV7850 Description Memory Interface Supply. SDRAM Lower Data Strobe True Signal. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. SDRAM Data Line. Ground. Analog Video Mux Input Channel. Analog Video Mux Input Channel. Ground. Analog Video Mux Input Channel. Analog Video Mux Input Channel. Ground. Rev. 0 | Page 23 of 32 ADV7850 Data Sheet POWER SUPPLY SEQUENCING POWER-UP SEQUENCE The recommended power-up sequence of the ADV7850 is as follows: 1. 2. 3.3 V supplies 1.8 V supplies 3.3V In this case, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level as the supplies are being established. POWER-DOWN SEQUENCE The ADV7850 supplies can be powered down simultaneously as long as the 3.3 V supply domain does not go below the 1.8 V supply domain. 3.3V SUPPLIES 1.8V Table 8 shows the current rating recommendations for power supply design. These values should be used when designing a power supply section to ensure that an adequate current can be supplied to the ADV7850. 1.8V SUPPLIES Table 8. Current Rating Recommendation for Power Supply Design 3.3V SUPPLIES POWER-UP 1.8V SUPPLIES POWER-UP 07758-012 POWER SUPPLY (V) POWER SUPPLY REQUIREMENTS Figure 10. Recommended Power-Up Sequence Notes RESET should be held low while the supplies are being powered up. 3.3 V supplies should be powered up first. 1.8 V supplies should be powered up last. The ADV7850 can alternatively be powered up by asserting all supplies simultaneously. Parameter IDVDD ICVDD ITVDD IAVDD IAC_AVDD ITX_PVDD IPVDD ITX_VDD33 ISDVDD ITX_AVDD IDVDDIO ISAVDD Rev. 0 | Page 24 of 32 Rating 600 mA 450 mA 400 mA 350 mA 150 mA 100 mA 60 mA 50 mA 50 mA 50 mA 20 mA 20 mA Data Sheet ADV7850 FUNCTIONAL OVERVIEW HDMI RECEIVER The ADV7850 front end incorporates a 4:1 multiplexed HDMI receiver with Xpressview fast switching technology and support for HDMI features including ARC and 3D TV. Building on the feature set of Analog Devices existing HDMI devices, the ADV7850 also offers support for all HDTV formats up to 3D 1080p at 60 Hz and 2160p at 24 Hz. Xpressview fast switching technology, using the Analog Devices hardware-based HDCP engine that minimizes software overhead, allows switching between any two input ports in less than 1 second. With the inclusion of HDCP 1.4, the ADV7850 can receive encrypted video content. The HDMI interface of the ADV7850 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewal of that authentication during transmission, as specified by the HDCP 1.4 protocol. Repeater support is also offered by the ADV7850. The ADV7850 supports the audio return channel feature. There is a dedicated S/PDIF input on which audio can be received for retransmission on the HDMI input. Wide ranges of 3D video formats are supported, including frame packing up to 3D 1080p at 60 Hz and 2160p at 24 Hz. The HDMI receiver incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest HDMI data rates. The HDMI receiver offers advanced audio functionality. It supports multichannel I2S audio for up to eight channels. It also supports a six-DSD channel interface with each channel carrying an oversampled 1-bit representation of the audio signal as delivered on SACD. The ADV7850 can also receive HBR audio packet streams and outputs them through the HBR interface in an S/PDIF format conforming to the IEC 60958 standard. • • ANALOG FRONT END The ADV7850 analog front end comprises four 170 MHz, 12-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP) or component processor (CP). The front end also includes a 13-channel input mux that enables multiple video signals to be applied to the ADV7850 without the requirement of an external mux. Current and voltage clamp control loops ensure that any dc offsets are set properly for the video signal. The clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. The ADCs are configured to run up to 4× oversampling mode when decoding composite, S-Video, or SCART inputs. For component 525i, 625i, 525p, and 625p sources, 4× oversampling is performed. Higher frequency video standards can be 2× or 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal-to-noise ratio (SNR). Optional internal antialiasing filters with programmable bandwidth are positioned in front of each ADC. These filters can be used to band-limit video signals, removing spurious outof-band noise. The ADV7850 can support the simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed with the output under the control of I2C registers. Analog front-end features include: • The receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be muted to prevent audio clicks or pops. • HDMI receiver features include: • • • • • • • • • • 4:1 multiplexed HDMI receiver HDMI, ARC, and 3D format support, DVI 1.0 297 MHz HDMI receiver Integrated equalizer High-bandwidth Digital Content Protection (HDCP 1.4) on background ports Internal HDCP keys 36-/30-bit Deep Color support PCM, HBR, DSD, and DST audio packet support Repeater support Internal E-EDID RAM Hot plug assert output pin for each HDMI port • • • Rev. 0 | Page 25 of 32 Four 170 MHz, 12-bit NSV ADCs that enable 10-bit (SD)/ 12-bit (CP) video decoding 13-channel analog input mux that enables multiple source connections without the requirement of an external mux Four current and voltage clamp control loops that ensure any dc offsets are set properly for the video signal SCART functionality and SD RGB overlay on CVBS controlled by fastblank input SCART source switching detection through the TRI1 to TRI8 inputs Four programmable antialiasing filters ADV7850 Data Sheet • STANDARD DEFINITION PROCESSOR The SDP is capable of decoding a large selection of baseband video signals in composite, S-Video, and 525i/625i component formats. The video standards supported by the SDP include PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The ADV7850 can automatically detect the video standard and process it accordingly. The SDP has a 3D temporal comb filter and a five-line adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter controls for brightness, contrast, saturation, and hue. The ADV7850 implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7850 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs, VCR players, and camcorders). Frame TBC ensures stable clock synchronization between the decoder and the downstream devices. The SDP also contains both a luma transient improvement (LTI) block and a chroma transient improvement (CTI) block. These increase the edge rate on the luma and chroma transitions, resulting in a sharper video image. The SDP has a Macrovision® detection circuit that allows Type I, Type II, and Type III Macrovision protection levels. The decoder is also fully robust to all Macrovision signal inputs. SDP features include: • • • • • • • • • • • Advanced adaptive 3D comb (using the external DDR2 memory) Adaptive 2D five-line comb filters for NTSC and PAL that give superior chrominance and luminance separation for composite video Full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM) Automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners IF filter block that compensates for high frequency luma attenuation due to tuner SAW filter LTI and CTI Vertical and horizontal programmable luma peaking filters 4× oversampling (54 MHz) for CVBS, and S-Video modes Free-run output mode that provides stable timing when no video input is present or video lock is lost Internal color bar test pattern • Advanced TBC with frame synchronization, which ensures nominal clock and data for nonstandard input Color controls that include hue, brightness, saturation, and contrast COMPONENT PROCESSOR The CP section of the ADV7850 is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The any-to-any, 3 × 3 CSC matrix is placed between the analog front end and the CP section. This enables YPbPr-to-RGB and RGB-to-YCbCr conversions. Many other standards of color space can be implemented using the color space converter. The CP section contains circuitry to enable the detection of Macrovision encoded YPbPr signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. CP features include: • • • • • • • • • • • • • • • Rev. 0 | Page 26 of 32 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats are supported Supports 720p at 24 Hz/25 Hz formats Manual adjustments including gain (contrast), offset (brightness), hue, and saturation Support for analog component YPbPr and RGB video formats with embedded synchronization, composite synchronization, or separate HS and VS Any-to-any, 3 × 3 CSC matrix that supports YCbCr-toRGB and RGB-to-YCbCr, fully programmable or preprogrammable configurations Synchronization source polarity detector (SSPD) that determines the source and polarity of the synchronization signals that accompany the input video Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) Free-run output mode that provides stable timing when no video input is present or video lock is lost Arbitrary pixel sampling support for nonstandard video sources 170 MHz conversion rate, which supports RGB input resolutions up to 1600 × 1200 at 60 Hz Automatic or manual clamp-and-gain controls for graphics modes 32-phase ADC DLL that allows optimum pixel clock sampling Automatic detection of synchronization source and polarity by SSPD block Standard identification enabled by STDI block RGB that can be color space converted to YCbCr and decimated to a 4:2:2 format for video-centric back-end IC interfacing Data Sheet ADV7850 VBI DATA PROCESSOR (VDP) Double Data Rate 2 (DDR2) VBI extraction of Teletext, CC, WSS, CGMS, PDC, UTC, VPS, GEMSTAR, and VITC data is performed by the VBI data processor of the ADV7850 at interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the SPI interface. The ADV7850 can use DDR2 external memory to simultaneously provide 3D comb and frame TBC operation. TMDS OUTPUT The ADV7850 incorporates a 297 MHz TMDS output. This interface is designed to connect to any internal IC with an HDMI or DVI input port. The digital video interface contains an HDMI and a DVI 1.0compatible transmitter, and supports all HDTV formats up to 3D 1080p at 60 Hz and 2160p at 24 Hz. The ADV7850 transmitter fully supports programmable AVI InfoFrames. With the inclusion of HDCP, the ADV7850 transmitter allows the secure transmission of protected content as specified by the HDCP protocol. The ADV7850 transmitter also fully supports EDID read operations. The ADV7850 TMDS output supports the audio mode received from the HDMI receiver, that is, PCM, HBR, DSD, and DST. It requires a minimum memory of 128 Mb with a speed grade of 200 MHz at CAS latency (CL) 3. The recommended DDR2 memory compatible with the ADV7850 include the MT47H32M16HR-25E:G from Micron Technology, Inc. OTHER FEATURES The ADV7850 has one I2C host port interface. The ADV7850 has two programmable interrupt request output pins, INT1 and INT2. It also features a number of low power modes and a full power-down mode. The ADV7850 contains an internal power regulator to accommodate power-off mode. In this mode, the ADV7850 is powered from the 5 V supply of the HDMI/VGA cable connected to a source device or devices. In this mode, EDID can be read over an HDMI/VGA DDC link. EXTERNAL MEMORY REQUIREMENTS The ADV7850 is provided in a 19 mm × 19 mm, RoHS-compliant CSP_BGA package and is specified over the −20°C to +70°C temperature range. The ADV7850 requires an external SDRAM for 3D comb and frame TBC. The ADV7850 supports DDR2 memories. For more detailed product information about the ADV7850, contact your local Analog Devices sales office. Rev. 0 | Page 27 of 32 ADV7850 Data Sheet AUDIO OVERVIEW AUDIO_L/R_1 AUDIO_L/R_2 AUDIO_L/R_3 AUDIO_L/R_4 AUDIO_L/R_5 5-CHANNEL STEREO INPUT MATRIX ADC I2S TO HDMI Tx BLOCK EXTERNAL IMPEDANCE INTERNAL IMPEDANCE ADV7850 2.8 V rms INPUT 22kΩ 10.1kΩ AC_SCLK AC_LRCLK AC_SDI 2.8 V rms INPUT 22kΩ 10.1kΩ 2.8 V rms INPUT 22kΩ 10.1kΩ The ADV7850 supports an audio codec comprising a stereo ADC and a stereo DAC. A 5:1 stereo mux is placed in front of the ADC input. The DAC output is available as a line level output and is passed through an internal headphone amplifier. The integrated headphone amplifier eliminates the need for an external amplifier when driving headphones. 2.8 V rms INPUT 22kΩ 10.1kΩ 2.8 V rms INPUT 22kΩ 10.1kΩ ANALOG AUDIO MUX FUNCTIONALITY A factory calibration is applied during final test to ensure that the gain through the mux circuit remains within ±5%. Calibration is also applied to the ADC reference current to ensure that the code swing from the ADC remains within ±5% across the part for a given input. External impedances with a tolerance of ±1% are required. Figure 11. Audio Block The ADV7850 has five stereo analog audio inputs and one stereo analog output. Any one of the stereo inputs can be connected to the stereo ADC, and any one of the inputs can be connected to the stereo output. In the case of the analog output, the ADV7850 also supports mono in-stereo output. The I/O connectivity is shown in Table 9. Table 9. Analog Audio Inputs to ADC and Analog Audio Outputs Connection Capability Mux Input 1 2 3 4 5 Left Right Left Right Left Right Left Right Left Right Mux Output Left Right OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK OK Left OK N/A OK N/A OK N/A OK N/A OK N/A ADC Input Right N/A OK N/A OK N/A OK N/A OK N/A OK The ADV7850 is designed to use a combination of internal and external resistances. Measured from the system audio input connector, the total nominal input impedance is 32.1 kΩ. All analog system audio inputs are designed to support 2.8 V rms audio input. Figure 12 shows a high level overview of the implementation. The input level at the analog audio input pins on the ADV7850 is 880 mV rms. However, the ADV7850 incorporates a gain stage to restore the mux output level to 1.0 V rms. An external line driver is required to restore the audio output signals to the SCART specification of 2.8 V rms. Analog audio mux output signals are inverted with respect to mux input signals. MUX OUTPUT 07758-014 DAC HP_L/R_OUT ADC MUX AUDIO PLL 07758-013 AC_MCLK AUDIO_L/R_OUT DAC_L/R_OUT Figure 12. High Level Overview of Analog Audio Input/Output Configuration AUDIO CODEC FUNCTIONALITY The ADV7850 audio codec requires an external MCLK. For MCLK with a frequency of 6.144 MHz, 12.288 MHz, or 24.576 MHz, the ADC and DAC sample rate is 48 kHz. If the MCLK is reduced to 5.6448 MHz, 11.2896 MHz, or 22.5792 MHz, the ADC and DAC sample rate reduces to 44.1 kHz. The bandwidth of the digital filter is sufficient so that 20 kHz pass band is maintained in this mode. The 32 kHz sampling is also possible but with pass-band reduction. The system controller must set an I2C control to select the correct mode of operation for the internal PLL so that it always generates an internal MCLK of 6.144 MHz. A fixed oversample rate of 128× is implemented. The word depth of both the ADC and DAC is 24 bits. The ADC and DAC have independent LRCLK and SCLK signals but use a common MCLK. The ADC supports I2S mode, providing LRCLK, SCLK, and I2S signals. These signals are sent to the HDMI Tx and embedded into the HDMI stream. The DAC supports I2S mode. The LRCLK, SCLK, and data signals must be provided by the back-end SOC and must be frequency locked with the MCLK but can be phase independent. The output level is 1 V rms full scale. There is one stereo headphone amplifier output capable of driving 32 Ω loads at 1 V rms. The headphone output incorporates circuitry to suppress pop/click sounds during power-on/off cycle. Rev. 0 | Page 28 of 32 Data Sheet ADV7850 REGISTER MAP ARCHITECTURE map addresses must be programmed. This ensures that no address clashes on the system. Figure 13 shows the register map architecture. The registers of the ADV7850 are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7850 has 17 maps. The IO map and HDMI Tx map has a static I2C addresses. All other Table 5. Register Map Name IO Map HDMI Tx Map VDP Map CP Map HDMI Rx Map HDMI Rx EDID Map KSV Map AFE Map InfoFrame Map SDP_IO Map SDP Map HDMI Tx EDID Map Tx UDP Map VFE Memory Map Audio Codec Map Tx TEST Map Default Address 0x40 0xB8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Programmable Address Not programmable Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Location at Which Address Can Be Programmed Not applicable Not applicable IO map, Register 0xFE IO map, Register 0xFD IO map, Register 0xFB IO map, Register 0xFA IO map, Register 0xF9 IO map, Register 0xF8 IO map, Register 0xF5 IO map, Register 0xF2 IO map, Register 0xF1 IO map, Register 0xF0 IO map, Register 0xEF IO map, Register 0xEC IO map, Register 0xEB IO map, Register 0xE7 IO map, Register 0xE3 IO MAP HDMI Tx MAP VDP MAP CP MAP HDMI Rx MAP HDMI Rx EDID MAP KSV MAP SLAVE ADDRESS: 0x40 SLAVE ADDRESS: 0xB8 SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SCL SDA SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE AFE MAP INFOFRAME MAP SDP_IO MAP SDP MAP HDMI Tx EDID MAP SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE Tx UDP MAP VFE MAP MEMORY MAP AUDIO CODEC MAP Tx TEST MAP 07758-015 SLAVE ADDRESS: PROGRAMMABLE Figure 13. Register Map Architecture Rev. 0 | Page 29 of 32 ADV7850 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 19.20 19.00 SQ 18.80 A1 BALL CORNER 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 A C E G 17.60 BSC SQ J L N 0.80 BSC R U W B D F H K M P T V Y AA AB AC TOP VIEW DETAIL A 0.65 NOM DETAIL A 0.35 NOM 0.30 MIN 0.35 NOM SEATING PLANE 1.11 1.01 0.91 0.50 COPLANARITY 0.12 0.45 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2. 11-22-2011-A 1.50 1.36 1.21 BOTTOM VIEW Figure 14. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-425-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7850KBCZ-5 EVAL-ADV7850EBZ Notes EVAL-ADV7850EB1Z 3 2, 3 3 Temperature Range −20°C to +70°C Package Description 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Low Cost, Blackfin-Based Evaluation Board with ADV7850 (with HDCP keys) ADV7850 Evaluation Board with Complete Audio Support (with HDCP Keys) 1 Package Option BC-425-1 Z = RoHS Compliant Part. Speed grade: 5 = 170 MHz. 3 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to purchase any components with internal HDCP keys. 2 Rev. 0 | Page 30 of 32 Data Sheet ADV7850 NOTES Rev. 0 | Page 31 of 32 ADV7850 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07758-0-5/12(0) Rev. 0 | Page 32 of 32