ISDN Exchange Power Controller (IEPC) PEB 2025 CMOS IC Features ● Supplies power to up to four transmission lines ● CCITT recommendations compatible for power feed at the “S” interface ● Each line is individually powered and controlled ● Wide field of applications: ● ● ● ● ● ● ● – two- and four wire transmission lines – point-to-point configurations – point-to-multipoint configurations Maximum output current programmable up to 150 mA Programmable switch-off characteristic by overcurrent detection Automatic restart after removing overload conditions Status detectors for each line driver Microprocessor compatible interface Interrupt output for detection of any malfunction High voltage CMOS technology (60 V) P-LCC-28-R P-DIP-22 Type Version Ordering Code Package PEB 2025-N V 1.5 Q67100-H6300 P-LCC-28-R (SMD) PEB 2025-P V 1.5 Q67100-H6241 P-DIP-22 The IEPC is an integrated power controller especially designed for feeding two- and four wire transmission lines. The IEPC is fully compatible to the CCITT recommendations on power feed at the “S”-interface. So the IEPC can be used in PABX/Central Office and in intelligent NT´s. The IEPC supplies power up to four transmission lines. Each line is individually powered and controlled via microprocessor interface. An interrupt output signals any malfunction to the microprocessor. The high voltage CMOS technology (60 V) ensures a wide field of applications: – two- and four wire transmission lines – point-to-point configurations – point-to-multipoint configurations etc. 1 05.92 PEB 2025 Programmable output current and thermal shut down guards the IEPC against overloads. The IEPC offers a special transient permitted overload state. Momentary overloads within a specified range e.g. by connecting a TE to a powered line, however, will not activate the currentlimit-circuits of the power controller. If overload is detected, the line driver will turn off according to a time and current dependent turn off characteristic. The IEPC offers an automatic restart-mode. In this case the IEPC tries to power up the line periodically, thus the feeding of a line will return automatically after the overload-conditions are removed. Pin Configurations (top view) P-DIP-22 P-LCC-28-R Semiconductor Group 2 PEB 2025 Pin Definitions and Functions Pin No. P-DIP-22 Pin No. P-LCC-28 Symbol Input (I) Output (O) Function 17 21, 22, 23 V BAT I Supply Voltage: This pin has to be connected to the negative supply voltage. V BAT supplies power to all line drivers. 22 1 V CC I Digital Supply Voltage: + 5V 11 14 GND I Ground: Digital Note: GND has to be connected to ground battery (positive supply voltage) 19, 18, 16, 15 25, 24, 20, 19 aF0 - aF3 O a-Line Feeding: aFi are the line driver outputs 12 15 R Imax I Current Limit: Using an external resistor connected between R Imax and GND, the maximum limit is the same to all line drivers. 21, 20, 14, 13 28, 26, 18, 16 CLC0 CLC3 I Current Limit Characteristic: By connecting external capacitors between CLCi and GND, the time-dependent turn off-characteristics of the line drivers are defined. 1 2 CS I Chip Select: A logic low on CS enables RD and WR communication between the processor and the IEPC. 3 4 WR I Write: A logic low on this pin, while CS is low, enables the IEPC to accept command words from the processor. 2 3 RD I Read: A low on this pin (while CS is low) enables the IEPC to release status onto the data bus for the processor. 6, 5, 4 8, 7, 5 D0 - D2 I/O Data Bus: Control, status and command information are transferred via this bus between IEPC and processor. 8, 7 11, 9 A0, A1 I Address Bus: These inputs select the internal registers while chip select is active. 10 13 RES I Reset: A logic high on the RES input sets the device into the initial state. Semiconductor Group 3 PEB 2025 Pin Definitions and Functions (cont’d) Pin No. P-DIP-22 Pin No. P-LCC-28 Symbol Input (I) Output (O) Function 9 12 INT O Interrupt: Open drain output. If any malfunction is detected by the IEPC, this interrupt-pin is activ low. – 6, 10, 17, 27 N.C. Not connected Figure 1 Functional Block Diagram Semiconductor Group 4 PEB 2025 Figure 2 IEPC Architecture Semiconductor Group 5 PEB 2025 Figure 3 Functional Diagram of One Line Driver Semiconductor Group 6 PEB 2025 Functional Description Figure 2 shows the IEPC organization. The exchange power controller contains one line driver for each of the four transmission lines. A line oriented register architecture allows very simple software control. Figure 3 shows the functional diagram of one of the four line drivers. The IEPC consists of a high voltage analog part and a low voltage digital part. The ground battery (positive supply voltage) has to be connected to GND (pin 11). When powering up the IEPC, the line drivers are switched off and all registers are cleared. The same initialized state can be achieved by an external high signal applied to the pin RES. Analog Part Power Switches The negative pole of the supply, e.g. an exchange battery, has to be connected to the pin V BAT. After an ON-command to line i, a high voltage MOS-FET will connect the negative supply voltage from V BAT to aFi. Current Control The current of each negative wire (aFi) is controlled individually. The maximum feeding current is programmed by an external resistor R I connected between pin R Imax and GND (see figure 1) and is same to all four lines. aFi Line Control: Connecting an external capacitor C Ti between CLCi and GND (see figure 1), the IEPC offers a special time and current dependent turn off characteristic. The IEPC will limit the aFi line current to protect the IEPC against over currents and to avoid discharging of the feeding source. Figure 4 shows this transient permitted overload (TPO) state. Semiconductor Group 7 PEB 2025 Figure 4 Diagram of the Transient Permitted Overload (TPO) State During the first timestep ( t OFF1 ) since overload of the negative wire aFi was detected ( I aFi ≥ I max ), the current will be limited. Within the next timestep ( till t OFF3 ) the current must drop from 1.5 I max to I max, otherwise the line driver turns off. After t OFF3 any current above I max results turn off the line driver. After t OFF4, if no turn off of the line driver has occured, the current limiting characteristics becomes active again and will be prepared for detection of further overload conditions. Timestep t OFF1 is defined by charging the capacitor C T with the current I the AC characteristics. t OFF3 and t OFF4 t depend on t OFF3 OFF1 ≈ 15 t OFF1 CLC which is specified in : t OFF4 =t AR ≈ 50 t OFF1 Note: If aFi has been switched off due to the time dependent current limiting circuit while C an ON command has no effect. To turn on the line driver C Ti has to be discharged. Ti is charged, C Ti will be discharged: – by an OFF command – if t OFF4 is reached – in non-automatic restart mode if the line driver has been switched off due to an overload condition. Semiconductor Group 8 PEB 2025 If overload is once detected, every exceeding of the current limits will turn off the line driver until t OFF4 is reached. The time dependent current limiting circuit will not be reseted if once overload is detected, even if the feeding current drops below I max until t OFF4 is reached. If pin CLC is connected to GND the time and current dependent turn off characteristic is disabled and the IEPC limits the driver current. Automatic Restart In connection with the time-dependent-current-limitation, the IEPC offers a programmable automatic restart mode (see digital part). If overload is detected ( I aFi ≥ I max ) at t 0, the IEPC starts charging the external capacitor C Ti. Automatic restart enabled: If the line driver has been switched off due to the time dependent turn off characteristic, C Ti will not be discharged by the IEPC. If t OFF4 is reached the line driver restarts automatically. So the time difference between turn off and automatic restart is variable and depends on the moment of turn off. Autorestart disabled: If t OFF4 is reached or if the line driver has been switched off due to the time dependent turn off characteristic, C Ti will be discharged by the IEPC. During the discharge time of C Ti, every restart of line i via microprocessor interface will be ignored by the IEPC. (With C Ti = 10 µF the maximum discharge time is 10 ms.) Temperature Shut-Off The temperature of each line driver is monitored separately. If the temperature of one line driver exceeds the shut-off temperature (approx. 120 ˚C), the transmission line will turn off. The shut-off temperature of the other three line drivers will be increased by approx. 25 ˚C. Open Loop Detection The IEPC offers an easy method to detect open loops. If the line driver aFi is in the OFF state a constant current source (approx. 100 µA) feeds the output aFi. In case of open loop (figure 5) the voltage at output aFi rises up to 3 V. Semiconductor Group 9 PEB 2025 Figure 5 Open Loop Detection Digital Part The microprocessor interface (MPI) communicates with a processor which controles the IEPC. This MPI contains a 3-bit data bus, a 2-bit address bus, read-, write-, chip select- and reset lines. If chip select is inactive (logic high) the data bus is in a high impedance state and no communication between the processor and IEPC is possible. The IEPC contains a line oriented register architecture, i.e. one read and one write register for each line. A read or write cycle affects the addressed register, which is related to the corresponding line driver. The write register consists of three control bits per line i: D0: Automatic Restart-bit (AR) D1: ON/OFF-bit (ON) D2: must be 0 The read register consists of three status bits per line i: D0: Interrupt-bit (INT) D1: Actual ON/OFF Driver status-bit (AO) D3: Current Overload-bit (CO) A logic high on the RES pin sets the device into an inital state: all registers of the IEPC are cleared (D0i - D2i are low). Semiconductor Group 10 PEB 2025 Address Table CS A1 A0 Selected Line 0 0 0 Line 0 0 0 1 Line 1 0 1 0 Line 2 0 1 1 Line 3 1 x x No access Write Register The write register is organized as shown below: D2i D1i D0i - D2i are bit 0 - 2 of line i (line number i = 0 - 3) D0i Automatic Restart-Bit (AR) ON/OFF-Bit (ON) must be 0 Automatic Restart Bit: Automatic restart mode is only possible in connection with the timedependent-current limitation, i.e. an external capacitor must be connected between pin CLCi and GND. If D0i is high, automatic restart mode is enabled. D2i D1i D0i AR enabled 0 x 1 AR disabled 0 x 0 Semiconductor Group 11 PEB 2025 ON/OFF-Bit: To turn a line driver on, D1i must be set to high, to turn it off, it must be set to low. An off command resets the time and current dependent turn off characteristic by discharging the external capacitor at pin CLCi. D2i D1i D0i ON 0 1 x OFF 0 0 x Read Register The read register is organized as shown below: D2i D1i D0i Interrupt-Bit (INT) Actual ON/OFF-Bit Driver Status-Bit (AO) Current Overload-Bit (CO) Interrupt-Bit: If malfunctions have been detected (current- or thermal overload) and the line driver of line i has been turned off the interrupt-bit will be set: D2i D1i D0i Interrupt x x 1 Operational x x 0 The interrupts INT0 - INT3 are anded to the device output-signal INT. Thus if any malfunction is detected an interrupt signal is sent to the microprocessor. Semiconductor Group 12 PEB 2025 Actual ON/OFF Driver Status-Bit: D1i shows the actual status of the line driver of line i: Driver D2i D1i D0i Driver ON x 1 x Driver OFF x 0 x Current Overload-Bit: If I aFi ≥ I max is detected and the line driver has been switched off the current overload bit will be set. If CLCi is connected to GND, the current overload bit will not be set. D2i D1i D0i Current overload 1 x x Operational 0 x x Semiconductor Group 13 PEB 2025 Figure 6 Line Driver State Diagram Semiconductor Group 14 PEB 2025 State Diagram Figure 6 shows the state diagram of one IEPC line driver. A logic high on the RES input sets the device into the initial state. The line driver is switched off and all registers are cleared. The same initialized state is achieved by powering up the IEPC. After an ON-command (ON = 1) the line drivers will turn on and the IEPC is in the FEEDING-state. To return to the OFF-state the ON-bit must be cleared (ON = 0). In the FEEDING-state the current I aFi is controlled. If overcurrent is detected one of the following cases happens: 1. If an external capacitor C Ti is connected between CLCi and GND and I aFi ≥ I max is detected the IEPC stays in the Transient Permitted Overload-state (TPO). Exceeding the time-current-limit the line driver turns off and the IEPC is in the STOP-state. The current overload-bit will be set (CO = 1) and C Ti will be discharged by an resistor of the IEPC. Until C Ti isn´t discharged completely, an ON command will be ignored. If no exceeding happens the line driver returns to the FEEDING-state. 2. If I aFi ≥ I max is detected and CLCi is connected to GND the IEPC limits the driver current. The current overload bit will not be set. The temperature of each line driver is controlled separately. If the temperature of the line driver exceeds the shut-off temperature, the transmission line will turn off and the line driver is in the STOP-state. In this case the shut-off temperature of the other three line drivers will be increased. There are two different ways to leave the STOP-state: 1. If the automatic restart bit is set (AR = 1) the IEPC returns after a delay time to the FEEDINGstate automatically. The ON/OFF register will not be cleared. 2. If no automatic restart mode is selected (AR = 0) the IEPC returns to the OFF-state. In this case the ON/OFF register will be cleared. As soon as the STOP-state is reached the IEPC sends an interrupt signal to the microprocessor (interrupt-pin is active low). If the line driver is not in the terminal overload state, every rising edge of the read signal resets the interrupt bit INTi (D0i) of the selected line i. The current overload-bit C0i (D2i) will be reseted too. If the line driver i is in the terminal overload state the rising edge of the read signal has no effect on the interrupt bit. The internal interrupts INT0 - INT3 are anded to the open drain output pin INT. So the interrupt pin stays activ low until all interrupt bits INTi are reseted. Semiconductor Group 15 PEB 2025 Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit V BAT referred to GND V BAT – 70 0.3 V V referred to GND V CC – 0.5 6 V Voltage on pins aF0 - aF3 VF V VCC V Continuous current on pins aF0 - aF3 only one channel IF 200 mA all channels at the same time; T A = 25 ˚C 150 mA all channels at the same time; T A = 70 ˚C 130 mA CC BAT Reverse current on pins at aF0 - aF3 IF 0 0 mA Voltage on any other pins referred to GND VI – 0.5 V CC + 0.5 V Power dissipation PD 1 W Ambient temperature under bias TA – 25 85 ˚C Storage temperature T stg – 40 125 ˚C Thermal resistance system to case R th SA 50 K/W Operating Range Operating voltage referred to GND V BAT – 60 – 12 V Digital supply voltage referred to GND V CC 4.75 5.25 V Ambient temperature TA 0 70 ˚C Semiconductor Group 16 PEB 2025 DC Characteristics T A = 0 to 70 ˚C; V BAT = – 12 to – 60 V, V CC = 5 V, GND = 0 V Parameter Symbol Limit Values min. typ. Unit Test Condition 200 µA a F0-3 = OFF 10 mA max. Supply Supply current I VBAT Digital supply current I VCC Current control limit I max 60 90 mA R I = 12 kΩ Current control limit I max 120 185 mA R I = 5.6 kΩ Current limiting factor (I aFi) I lim/I max 1.5 5 Turn on resistance (V BAT to aFi) R 9 Ω I aF = 50 mA T A = 25 ˚C 0.8 V 5 Line Drivers 7 DSon Logic L-input voltage V IL H-input voltage V IH L-output voltage V OL H-output voltage V OH Semiconductor Group 2.0 V 0.45 2.4 17 V I O = 2 mA V I O = – 1 mA PEB 2025 AC Characteristics T A = 25 ˚C; V BAT = – 12 to – 60 V, V CC = 5 V, GND = 0 V Parameter Symbol Limit Values min. typ. Unit Test Condition max. Line Driver & Current Control Delay: ON-command to turn on t ON line driver 0.2 ms for resistive loads Delay: ON-command to turn off t OFF line driver 1 ms for resistive loads C T charge current I CLC 100 120 140 µA till t OFF1 Current limiting time t OFF1 0.15 0.2 0.25 s C T = 10 µF Current control recovery time t OFF3 3 s C T = 10 µF Current control reset time t OFF4 7 10 15 s C T = 10 µF Automatic restart period t AR 7 10 15 s C T = 10 µF Unit Test Condition Switching Times Parameter Symbol Limit Values min. typ. max. RD pulse width t 1R 350 ns WR pulse width t 1W 180 ns Address and CS setup time to RD ↓ or WR ↓ t2 0 ns Address and CS hold time after t 3 RD ↓ or WR ↓ 30 ns Data setup time to WR ↑ t4 60 ns Data hold time after WR ↑ t5 100 ns Data valid after RD ↓ t6 Data valid after RD ↑ t7 Data bus inactive after RD ↑ t8 Reset pulse width t RES Semiconductor Group 350 50 ns ns 120 ns µs 5 18 PEB 2025 Figure 7 Waveforms Semiconductor Group 19 PEB 2025 Protection Requirements According to the absolute maximum ratings of the IEPC, the PEB 2025 has to be protected against overvoltage spikes comming in on aFi. This is done by the diodes D1 and D2 in figure 8. In some applications it could be necessary to protect the IEPC output aFi against reverse by using diode D3. Figure 8 Protection against Overvoltages and Reverse Currents Semiconductor Group 20 Package Outlines Plastic Leaded Chip Carrier, P-LCC-28-R (SMD) Plastic Dual In-Line Package, P-DIP-22 SMD = Surface Mounted Device Semiconductor Group Dimension in mm 21