STV7778S DEFLECTION PROCESSOR FOR MULTISYNC MONITOR .. .. . .. . .. . . . .. . . . .. . HORIZONTAL DUAL PLL CONCEPT SELF-ADAPTIVE (30 TO 70kHz) X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICATION WIDE RANGE DC CONTROLLED H-POSITION ON/OFF SWITCH (FOR PWR MANAGEMENT) TWO H-DRIVE POLARITIES VERTICAL VERTICAL RAMP GENERATOR 45 TO 120Hz AGC LOOP DC CONTROLLED V-AMP, V-POS, S-AMP AND S-CENTERING ON/OFF SWITCH The goal of this IC is to control all the functions related to the horizontal and vertical deflection in a multimodes or multisync monitor. As can be seen in the block diagram, the STV7778S includes the following functions : - Positive or Negative sync polarities, - Auto-sync horizontal processing, - H-PLL lock/unlock identification, - Auto-sync Vertical processing, - East/West signal processing block, - B+ controller, - Safety blanking output. An internal metal shield give to the STV7778S more immunity against electromagnetic and electrostatic fields, and therefore, additional safety for critical applications (for example, in case of CRTs with small coated area). B+ REGULATOR INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER DC ADJUSTABLE B+ VOLTAGE OUTPUT PULSES SYNCHRONISED ON HORIZONTAL FREQUENCY INTERNAL MAX CURRENT LIMITATION EWPCC VERTICAL PARABOLA GENERATOR WITH DC CONTROLLED KEYSTONE AND AMPLITUDE GENERAL COMPARED WITH THE STV7778, THE STV7778S HAS AN INTERNAL METAL SHIELD PROTECTION AGAINST OVERVOLTAGE. POS/NEG H AND V SYNC POL SEPARATED H AND V TTL INPUT SAFETY BLANKING OUTPUT SHRINK42 (Plastic Package) ORDER CODE : STV7778S DESCRIPTION The STV7778S is a monolithic integrated circuit assembled in a 42 pins shrunk dual in line plastic package. September 1998 1/11 STV7778S 2/11 PLL2C 1 42 ISENSE H-DUTY 2 41 COMP HFLY 3 40 REGIN HGND 4 39 B+-ADJ HREF 5 38 KEYST NC 6 37 E/W-AMP NC 7 36 E/WOUT NC 8 35 PLL1INHIB NC 9 34 VSYNC C0 10 33 V-POS R0 11 32 VDCOUT PLL1F 12 31 V-AMP HLOCK-CAP 13 30 VOUT FH-MIN 14 29 VS-CENT H-POS 15 28 VS-AMP XRAY-IN 16 27 VCAP HSYNC 17 26 VREF VCC 18 25 VAGCCAP GND 19 24 VDND H-OUTEM 20 23 SBLKOUT H-OUTCOL 21 22 B+OUT 7778S-01.EPS PIN CONNECTIONS STV7778S PIN-OUT DESCRIPTION Pin N° Name 1 PLL2C 2 H-DUTY Function Second PLL Loop Filter 3 H-FLY DC Control of Horizontal Drive Output Pulse Duty-cycle. If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a capacitor on this pin a soft-start function may be realized on h-drive output. Horizontal Flyback Input (Positive Polarity) 4 5 H-GND H-REF Horizontal Section Ground. Must be connected only to components related to H blocks. Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4 6 7 NC NC 8 9 NC NC 10 11 C0 R0 12 PLL1F 13 HLOCK-CAP First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change detected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the duration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4. 14 FH-MIN DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage generated by a resistor bridge connected between Pin 5 and 4. DC Control for Horizontal Centering Horizontal Oscillator Capacitor. To be connected to Pin 4. Horizontal Oscillator Resistor. To be connected to Pin 4. First PLL Loop Filter. To be connected to Pin 4. 15 H-POS 16 17 XRAY-IN H-SYNC 18 19 VCC GND 20 21 H-OUTEM H-OUTCOL Horizontal Drive Output (emiter of internal transistor) Horizontal Drive Output (open collector of internal transistor) 22 23 B+ OUT SBLK OUT 24 VGND B+ PWM Regulator Output Safety Blanking Output. Activated during frequency changes, when X-RAY input is triggered or when VS is too low. Vertical Section Signal Ground 25 26 VAGCCAP VREF 27 28 VCAP VS-AMP Vertical Sawtooth Generator Capacitor DC Control of Vertical S Shape Amplitude 29 30 VS-CENT VOUT DC Control of Vertical S Centering Vertical Ramp Output (with frequency independant amplitude and S-correction) 31 32 V-AMP VDCOUT DC Control of Vertical Amplitude Adjustment Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output 33 34 V-POS VSYNC DC Control of Vertical Position Adjustment Vertical TTL Sync Input 35 36 PLL1INHIB E/WOUT 37 38 E/W-AMP KEYST 39 40 B+ ADJ REGIN DC Control of B+ Adjustment Regulation Input of B+ Control Loop 41 42 COMP ISENSE B+ Error Amplifier Output for Frequency Compensation and Gain Setting Sensing of External B+ Switching Transistor Emiter Current X-RAY Protection Input (with internal latch function) TTL Horizontal Sync Input Supply Voltage (12V Typical) Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal) East/West Pincushion Correction Parabola Output 7778S-01.TBL DC Control of East/West Pincushion Correction Amplitude DC Control of Keystone Correction 3/11 STV7778S HSYNC 17 INPUT INTERFACE HLOCK-CAP HFLY PLL2C H-DUTY H-OUTEM H-OUTCOL 1 2 20 21 1st PHASE COMP FH-MIN 3 C0 15 12 11 10 14 13 R0 H-POS 35 PLL1F PLL1INHIB BLOCK DIAGRAM 2nd PHASE COMP VCO PULSE SHAPER OUTPUT BUFFER 23 SBLKOUT LOCK DETECT 39 B+-ADJ XRAY-IN 16 HREF VREF 5 42 I SENSE H-VREF HGND 4 VREF 26 VGND 24 V-VREF VCC R EA SAFETY PROCESSOR BANDGAP 22 B+OUT S Outputs Inhibition 41 COMP 40 REGIN PARABOLA GENERATOR 4/11 27 25 29 28 33 31 30 32 38 37 VS-CENT VS-AMP V-POS V-AMP VDCOUT KEYST E/W-AMP STV7778S 7778S-02.EPS 18 VOUT 19 VAGCCAP S CORRECTION VCAP VERTICAL OSCILLATOR VCC INPUT INTERFACE GND VSYNC 34 36 E/WOUT STV7778S Value Unit VCC Supply Voltage (Pin 18) 13.5 V VIN Max Voltage on 8 1.8 6 8 8 6 V 2 300 kV V -40, +150 °C 150 °C 0, +70 °C VESD Tstg Tj Toper Parameter Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39 Pin 3 Pins 17, 34 Pin 40 Pin 42 Pin 16 ESD Succeptibility Human Body Model, 100pF Discharge through 1.5kΩ EIAJ Norm, 200pF Discharge through 0Ω Storage Temperature Max Operating Junction Temperature Operating Temperature THERMAL DATA Symbol Rth (j-a) Parameter Junction-Ambient Thermal Resistance Value Unit 65 °C/W Max. 7778S-03.TBL Symbol 7778S-02.TBL ABSOLUTE MAX RATING HORIZONTAL SECTION Operating conditions Symbol Parameter Test conditions Min. Typ. Max. Unit VCO R0min Oscillator Resistor Min Value Pin 11 6 kΩ C0min Oscillator Capacitor Min Value Pin 10 390 pF Fmax Maximum Oscillator Frequency HsVR Horizontal Sync Input Voltage Pin 17 0 1 70 kHz 5.5 V INPUT SECTION µS MinD Minimum Input Pulses Duration Pin 17 Mduty Maximum Input Signal Duty Cycle Pin 17 25 % 2 mA HOI1 I3m Maximum Input Peak Current on Pin 3 Horizontal Drive Output Max Current Pin 20, sourced current 20 mA HOI2 Horizontal Drive Output Max Current Pin 21, sunk current 20 mA 6 V DC CONTROL VOLTAGES DCadj DC Voltage Range on DC Controls VREF-H = 8V, Pins 2-14-15 2 5/11 7778S-04.TBL OUTPUT SECTION STV7778S HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25°C) Symbol Parameter Test conditions Min. Typ. Max. Unit 10.8 12 13.2 V 40 60 mA 8 8.6 V 2 mA SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage Pin 18 ICC Supply Current Pin 18, See Figure 1 VREF-H Reference Voltage for Horizontal Section Pin 5 IREF-H Max Sourced Current on VREF-H Pin 5 VREF-V Reference Voltage for Vertical Section Pin 26 IREF-V Max Sourced Current on VREF-V Pin 26 7.4 7.4 8 8.6 V 2 mA 0.8 V V 6.2 V INPUT SECTION/PLL1 VINTH VVCO VCOG Hph FFadj CR PLLinh Hor Input Threshold Voltage Pin 17 Low level voltage High level voltage 2 VCO Control Voltage VREF-H = 8V, Pin 12 VCO Gain, dF/dV Pin 12 R0 = 6.49kΩ, C0 = 680pF 15 kHz/V Horizontal Phase Adjustment (Pin 15) % of Hor period ±10 % Free Running Frequency Adjustment (Pin 14) Without H-sync Signal ±20 % PLL1 Capture Range (F0 = 27kHz) Fh Min Fh Max See conditions on Figure 1 PLL 1 Inhibition (Pin 35) PLL ON PLL OFF 1.6 28 70 kHz kHz V V35 V35 0.8 2 SECOND PLL AND HORIZONTAL OUTPUT SECTION Hjit Flyback Input Threshold Voltage Pin 3 Minimum Hor Drive Output Duty-cycle Maximum Hor Drive Output Duty-cycle Pin 20 or 21, V2 = 2V Pin 20 or 21, V2 = 6V HDvd Horizontal Drive Low Level Output Voltage V21-V20, Iout = 20mA, Pin 20 to GND HDem Horizontal Drive High Level Output Voltage Pin 21 to VCC, IOUT = 20mA (output on Pin 20) XRAYth X-RAY Protection Input Threshold Voltage ISblkO Maximum Output Current on Safety Blanking I23 Output Low-Level Voltage on Safety Blanking Output Pin 16 V23 with I23 = 10mA Vphi2 Internal Clamping Voltage on 2nd PLL Loop Filter Vmin Output (Pin 1) Vmax VOFF Pin 2 Threshold Voltage to Stop H-out, V-out V2 B+out and to Activate S-BLK.OFF Mode when V2 < VOFF 6/11 0.75 150 ppm 35 45 30 50 % % 1.1 1.7 V Horizontal Jitter HDmin HDmin VSblkO 0.65 9.5 V 10 1.6 0.25 V 1.8 V 10 mA 0.5 V 1.6 3.2 V V 1 V 7778S-05.TBL FBth STV7778S Symbol EAOI FeedRes Parameter Test conditions Min. Maximum Error Amplifier Output Current Sourced by Pin 41 Sunk by Pin 41 Minimum Feedback Resistor Resistor between Pins 40 and 41 5 Test conditions Min. Typ. Max. Unit 0.5 2 mA mA kΩ 7778S-06.TBL B+ SECTION Operating Conditions Electrical Characteristics (VCC = 12V, Tamb = 25°C) OLG Parameter Typ. Max. Unit Error Amplifier Open Loop Gain At low frequency (see Note 1) 85 dB Unity Gain Bandwidth (see Note 1) 6 MHz Regulation Input Bias Current Current sourced by Pin 40 (PNP base) 0.2 µA EAOI Maximum Guaranted Error Amplifier Output Current Current sourced by Pin 41 Current sink by Pin 41 CSG Current Sense Input Voltage Gain Pin 42 3 Max Curent Sense Input Threshold Voltage Pin 42 1.2 V Current Sense Input Bias Current Current sunk by Pin 42 (NPN base) 1 µA Tonmax Maximum External Power Transistor on Time % of H-period, @ f0 = 27kHz 75 % B+OSV B+ Output Low Level Saturation Voltage V22 with I22 = 10mA 0.25 V Internal Reference Voltage On error amp (+) input for V39 = 4V 4.9 V Internal Reference Voltage Adjustment 2V < V39 < 6V ±14 % UGBW IRI MCEth ISI IVref VREFADJ 0.5 2 mA mA 7778S-07.TBL Symbol EAST WEST PARABOLA GENERATOR Electrical Characteristics (VCC = 12V, Tamb = 25°C) Vsym Kadj Paramp Parameter Parabola Symetry Adjustment Capability (for Keystone Adjustment ; with Pin 38) Test conditions Min. Typ. Max. Unit V See Figure 2 ; Internal voltage V38 = 2V V38 = 4V V38 = 6V 3.2 3.5 3.8 Keystone Adjustment Capability B/A ratio A/B ratio See Figure 2 ; V37 = 4V V38 = 2V V38 = 6V 2.3 2.0 Parabola Amplitude Adjustment Capability Maximum Amplitude on Pin 36 Maximum Ratio between Max and Min V38 = 4.3V, V28 = 2V V37 = 2V 2V < V37 < 6V 3.3 2.4 3.8 3 4.3 V 7/11 7778S-08.TBL Symbol VERTICAL SECTION Operating Conditions Symbol VSVR Parameter Vertical Sync Input Voltage Test conditions On Pin 34 Min. Typ. 0 Max. Unit 5.5 V Max. Unit µA 7778S-09.TBL STV7778S Electrical Characteristics (VCC = 12V, Tamb = 25°C) IBIASN VSth VSBI VRB VRT VRTF IR27 VSW VSmDut VSTD VFRF Parameter Test conditions Pin 23-28-29 Bias Current (Current sourced For V23-28-29 = 2V by PNP base) Pin 31 Bias Current (Current sunk by NPN For V31 = 6V base) Pin 34; High-level Vertical Sync Input Threshold Voltage Low-level Vertical Sync Input Bias Current (Current Sourced by PNP Base) Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Output Current Range on Pin 27 during Ramp Charging Time. Current to Charge Capacitor between Pin 27 and Ground Minimum Vertical Sync Pulse Width Vertical Sync Input Maximum Duty-cycle Vertical Sawtooth Discharge Time Duration Vertical Free Running Frequency (V28 = 2V) ASFR RATD AUTO-SYNC Frequency (see Note 3) Ramp Amplitude Thermal Drift RAFD Ramp Amplitude Drift Versus Frequency Rlin Rload Vpos IVPOS Vor VOUTDC V0I dVS Ccorr Ramp Linearity on Pin 27 ∆I27/I27 Min. Minimum Load on Pin 25 for less than 1% Vertical Amplitude Drift Vertical Position Adjustment Voltage on V33 = 2V Pin 32 V33 = 4V V33 = 6V Max Current on Vertical Position Control Output (Pin 32) Vertical Output Voltage (on Pin 30) V31 = 2V V31 = 4V (Peak to Peak Voltage on Pin 30) V31 = 6V DC Voltage on Vertical Output (Pin30) See Note 4 Vertical Output Maximum Output Current On Pin 30 Max Vertical S-Correction Amplitude ∆V/V30pp at T/4 (V28 = 2V Inhibits S-CORR; V28 = 6V gives ∆V/V30pp at 3T/4 Maximum S-CORR) (see Figure 3) C-Correction Adjustment Range Voltage on V29 = 2V Pin 27 for Maximum Slope on the Ramp V29 = 4V (with S-Correction) (see Figure 4) V29 = 6V µA 0.5 2 1 V V µA 2/8 5/8 VRT-0.1 VREF-V VREF-V V 0.8 V34 = 0.8V On Pin 27 On Pin 27 On Pin 27 V28 = 2V (Note 2), 2V < V27 < 5V Min current Max current Pin 34 Pin 34 On Pin 27, with 150nF cap Measured on Pin 27, Cosc (Pin27) = 150nF With C27 = 150nF ±5% On Pin 30 (see Note 1), (0°C < Tamb < 70°C) V31 = 6V, C27 = 150nF, 50Hz < F < 120Hz V28 = 2V, V25 = X = 4.3V, 2.5V < V27 < 4.5V Typ. 2 100 5 15 135 20 15 85 100 50 120 100 Hz ppm/°C 200 ppm/Hz 0.5 % 50 3.65 3.75 µA µA µS % µS Hz MΩ 3.2 3.5 3.8 ±2 3.3 V V V mA 2 3 4 7/16 ±5 -4 +4 2.2 V V V 3 3.5 4 VREF-V mA % % V V V Notes : 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 2. When 2V are applied on Pin 28 (Vertical S-Correction control), then the S-Correction is inhibited, consequently the sawtooth have a linear shape. 3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 4. Typically 3.5V for Vertical reference voltage typical value (8V). 8/11 7778S-10.TBL Symbol IBIASP 7778S-06.EPS 2.2m F 2.2m F 34 24 26 4 5 16 17 18 12V S5 19 INPUT INTERFACE V-VREF H-VREF INPUT INTERFACE 35 150nF 1% 27 25 470nF 1% VERTICAL OSCILLATOR BANDGAP 1.8kW VCO 6.49kW 10 29 28 33 Outputs Inhibition SAFETY PROCESSOR VCC 3 31 2nd PHASE COMP 220nF LOCK DETECT 14 13 680pF 1% S CORRECTION 11 4.7µF 15 12 1st PHASE COMP 10nF 30 1 2 32 PULSE SHAPER 22nF 21 4.7kW VREF 38 37 PARABOLA GENERATOR EA OUTPUT BUFFER 20 S6 12V STV7778S S R 36 40 41 22 42 39 23 10kW 47kW 470pF 3.9kW 4.7kW 10kW 12V 12V STV7778S Figure 1 : Testing Circuit 9/11 STV7778S Figure 2 : Keystone Adjustment V36 V38 = 2V A B V38 = 4V V38 = 6V V27 7778S-03.AI 3.8 3.5 3.2 Figure 3 : S Amplitude Adjustment V30 ∆V V30pp T/4 T/2 3T/4 T 7778S-04.AI 0 ∆V increase when V28 increase. ∆V = 0 when V28 = 0. Figure 4 : C Correction Adjustment V27 4.0V 3.5V 0 10/11 T 7778S-05.AI 3.0V STV7778S PACKAGE MECHANICAL DATA 42 PINS - PLASTIC PACKAGE E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 1 PMSDIP42.EPS Gage Plane e3 21 e2 SDIP42 A A1 A2 B B1 c D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70 2.54 Millimeters Typ. 3.81 0.46 1.02 0.25 38.10 13.72 1.778 15.24 3.30 Max. 5.08 4.57 0.56 1.14 0.38 38.35 16.00 14.48 18.54 1.52 3.56 Min. 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50 0.10 Inches Typ. 0.150 0.0181 0.040 0.0098 1.5 0.540 0.070 0.60 0.130 Max. 0.200 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570 0.730 0.060 0.140 SDIP42.TBL Dimensions Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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