Package lead inductance considerations in high-speed applications

Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
Authors: Stephen C. Hinkle, Jeffrey A. West
measured to be about 10nH. Switching 75mA through a ground lead
with an inductive value of 10nH causes a ground bounce of about:
INTRODUCTION
A circuits become faster, more concern needs to be focused on
packaging and interconnects in order to fully utilize device
performance. One area of concern is with the package leads
between the chip and the board environment. The current flowing
into or out of an integrated circuit is conducted through a lead frame
trace and bonding wire connecting the integrated circuit to outside
circuitry. these leads are circuit elements, inductors, and have a
definite effect on the circuit performance because they generate
noise in high-speed applications.
V L dI 10nH 75mA 750mV.
1ns
dt
Figure 1 illustrates the current surge and ground bounce during
switching. This was modeled using the equations:
V(t) Inductance is the measure of change in the magnetic field
surrounding a conductor resulting form the variation of the current
flowing through the conductor. The change in current through the
inductor induces a counter electromotive force, EMF, which opposes
that change in current.
3V
1 E (ttO)K
I C(t) C
dV(t)
dt
V L(t) L
dI C(t)
D 2V(t)
LC
dt
dt 2
If more than one output is switched at a time, this ground bounce
can get very large. Changing the ground reference on the chip can
have significant effects on circuit performance. A VCC bounce can
also be calculated when the 50pF load capacitors are being charged
and can also have serious effects on circuit performance.
An example is a buffer driver discharging a 50pF load. At a
switching rate of about 3V in 2ns, the current generated by
discharging that capacitor at that rate is:
I C dV 50pF 3v 75mA.
2ns
dt
Some of the problems caused by package lead inductance are:
1. Adding delay through buffer parts
All this current flows through the ground lead of the package.
Changing the current through this lead generates a ground lead
voltage or ground bounce. A typical lead inductance has been
2. Changing the state of flip-flop parts
3. Output glitching on unswitched outputs
4. Circuit oscillations.
GRAPHICAL OUTPUT–GROUND BOUNCE
4V
400mA
OUTPUT WAVEFORM
CURRENT SURGE
GROUND BOUNCE
–100mA
–1V
0.0
1.0E–00
SECONDS
SF01318
Figure 1.
1987 June
1
Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
bounce. The eighth flip-flop input was held at a DC bias of 2.0V. This
should result in its output being held at a constant 1 level.
GENERAL PROBLEMS ASSOCIATED WITH
GROUND BOUNCE IN HIGH-SPEED CIRCUITS
Figure 5 shows the corner mount results. The ground bounce is
sufficient to couple the output of the eighth flip-flop (Q7) to less than
2.0V during the transition of the other seven outputs represented by
Q6. The output then charges to a marginal VOH level.
Adding Delay Through Buffer Parts
Delay through a buffer part is not only a function of the gate itself but
is also a function of how many gates in the package are switching at
once. Switching more than one output at a time adds to the current
being forced through the ground lead of the package. the ground
potential seen by the chip rises because of the lead inductance. This
rise in ground potential raises the threshold of the gate and tends to
turn the gate back OFF slowing the discharge rate of the load
capacitor. The gate does not finish switching until the ground bounce
settles out.
Figure 6 shows the results from the side mount version. Output
glitching during the transition of the other seven outputs is still
present, but due to the approximately 50% reduction in lead
inductance over the corner mount version, the output is allowed to
charge back to its original VOH level.
Figure 2 shows an example of a buffer connected to a test load.
Probing on the ground pad, VG, shows the effect ground lead
inductance has on the ground pad potential.
VCC
Figures 3 and 4 show the ground and VCC bounce during switching
on a 74F240 Buffer. The effect of ground bounce on this part is to
slow the propagation delays from 3ns with only one output switching
to 5ns with all 8 outputs switching at once. AC specifications are
usually generated with only one gate switching at a time. For
example, the 74F240 tPHL limits are 2.0ns minimum, 3.5ns typical
and 4.7ns maximum. Therefore, when using AC specifications
based on single gate switching, a derating factor for multiple
switching should be used. A derating factor of 250 to 300ps per
output switching has been suggested as a reasonable number and
some customers are using this i their internal specifications.
VC
VIN
VOUT
500
50pF
Integrated Circuits Containing Flip-Flops
Integrated circuits containing flip-flops might be seriously affected by
inductive ground bounce because of the possibility of the flip-flops
changing states. To explore this effect, the 74F374, and Octal
D-type Flip-Flop, was analyzed by comparing test results from the
conventional corner mount VCC and ground package to that of a
side mount VCC and ground version. A test setup as used where
alternate 1’s and 0’s were clocked into seven of the eight flip-flops to
obtain simultaneous output switching and worst case ground
VG
L
SF01319
Figure 2.
SF01320
Figure 3.
1987 June
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Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
SF01321
Figure 4.
OE 1
1*
20 VCC
Q2 1
20 Q1
1*
Q0
2
19 Q7
D2
2
19 D1
D0
3
18 D7
D3
3
18 D0
D1
4
17 D6
Q3
4
Q1
5
16 Q6
GND
5
Q2
6
15 Q5
CP
6
D2
7
14 D5
Q4
7
14 Q7
D3
8
13 D4
D4
8
13 D7
Q3
9
12 Q4
D5
9
12 D6
GND 10
11 CP
Q5 10
11 Q6
F374
CORNER
MOUNT
74F374 Failure Analysis
17 Q0
F374
SIDE
MOUNT
15 VCC
74F374XL
5.0E – 07 S
5.0E – 07 S
CLK
2V
CLK
2V
0V
0V
0V
0V
2V
OUTPUT
(Q6)
2V
OUTPUT
(Q6)
0V
0V
3V
3V
OUTPUT
(Q7)
OUTPUT
(Q7)
74F374 FAILURE
ANALYSIS
74F374XL
0V
0V
SF01322
SF01323
Figure 5.
1987 June
16 OE
Figure 6.
3
Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
Output Glitching During Multiple Switching
In some cases, the effects of ground bounce can be minimized if
properly taken into consideration during the design and layout of the
integrated circuit. Note in Figure 7, the glitch that was present on the
output of the 74F11, a triple 3-input AND gate, during an early
transition of the other two outputs. A newer version of the 74F11 is
shown in Figure 8. Note that the glitch has been greatly minimized.
TIME/DIV: 5NS
VOLTS/DIV: 1V
WAVEFORM #2
OUTPUT 8
Circuit Oscillations
A fourth area of concern is the possibility of circuit oscillations during
slow input transitions through threshold. This would be of
importance if the delay through the part is on the order of the natural
period of the ground inductance and the load capacitance.
WAVEFORM #1
INPUTS 2.3
During testing, a particular problem has been seen when the inputs
are driven by a power supply by way of a cable. Because there is a
delay through the cable, it takes time for the power supply to sense
a change in the impedance at the input near threshold. This delay
sets up oscillations between the power supply and the input of the
part when the input is held near threshold.
0V
74F11 OUTPUT GLITCH #2
SF01324
Inductance Measurements and Verification
Figure 7.
To verify that lead inductance caused these problems, the lead
inductance was measured and circuit simulations done to show
circuit behavior. Measurement of lead inductance was accomplished
using an HP S-parameter test set. These measured values of lead
inductance were used in a circuit simulation program. The results of
the simulation show voltage and current wave forms similar to the
measured waveforms.
TIME/DIV: 5NS
VOLTS/DIV: 1V
WAVEFORM #2
OUTPUT 3
WAVEFORM #1
INPUTS 2.3
0V
74F11 OUTPUT GLITCH #2
SF01325
Figure 8.
1987 June
4
Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
Derivation of the S-parameter Method
I1
The general form for voltage and current along a transmission line
is:
+
V(z) = V+ e– γz + V– e γz
I(z) = I+e– γz –I–e!s
V+,
RGEN
Z0
VGEN
V–, I+, I–
are constants, usually complex, determined by
Where
the boundary conditions, z is the distance from the load and gamma
(γ) is a complex term involving a real or loss term and an imaginary
or phase shift term.
V1
Z1
=
–
γ = ∝ + jβ
Z=0
γ 1/2(R C/L + GL/C) + jω LC.
SF01326
Considering the lossless case where R = 0 and G = 0, γ = jβ and
only results in a phase shift. The equations for voltage and current
then become:
Figure 9.
Example
V(z) = V+ e– jβz + V– e jβz
A 16-pin package measuring from pin 8 to 16 has a reflection
coefficient ΓdB = –0.5 ∠ 162°, Z0 of the system is 50Ω and the
measurement frequency is 50MHz.
I(z) = I+ e– jβz – I– e jβz
To find Z1 set z = O. (See Figure 9).
ΓdB = –0.5 ∠ 162°
Z1 = V1/I1 = (V+ + V–)/(I+ – I–)
Γreal = 0.944 ∠ 162° = –0.898 + j0.292
since, I+ = V+ /Z0 and,
0.102 j0.292
Z 1 Z 0 1 50 *
1
1.898 j0.292
I– = V– /Z0,
Z1 = (V+ + V–)/(V– /Z0 – V+ /Z0), or,
Z1 Z0
50 * 0.309 70.7°
1.920 –8.74 °
1 V V 1 V V = 8.05 ∠ 79°
V–/V+ is called the reflection coefficient and is usually complex,
Z1 = 1.475 + j7.914
Γ = V– / V+.
L = 7.914/(2π*50MHz) = 25.19nH
The impedance at the load then becomes:
Alternately, using the approximation R = 0, so | Z1 | = ωL:
Z1 Z0 1 1
L
On the S-parameter test set, the magnitude of the reflection
coefficient, | Γ |, is measured in dB at a particular angle,
Γreal =
10( | Γ dB | / 20)
8.05
25.62nH
2 * 50MHz
Three packages were used to measure lead inductance, a 16-pin
CERDIP, a 24-pin CERDIP and a 24-pin skinny CERDIP. VCC and
ground were double bonded to an 80×80 mil blank die. Table 1
shows the results of the measurements.
∠ θ.
For an inductor,
Z 1 Z 0 1 R jL
1
These values are the total inductance VCC to ground. Each lead
inductance would be about one half these numbers.
usually R 0 and L can be solved for directly.
Table 1.
PACKAGE
REFLECTION COEFFICIENT
INDUCTANCE
16-pin (300mil-wide)
8 to 16
4 to 12
–0.50 ∠ 162°C
–0.32 ∠ 172°C
25.62nH
11.51nH
24-pin (600mil-wide)
12 to 24
6 to 18
–0.56 ∠ 157°C
–0.29 ∠ 157°C
32.78nH
18.33nH
24-pin (300mil-wide)
12 to 24
6 to 18
–0.47 ∠ 160°C
–0.34 ∠ 170°C
28.39nH
14.27nH
1987 June
5
Philips Semiconductors
Application note
Package lead inductance considerations
in high-speed applications
AN212
This represents noise to an integrated circuit chip and can cause
performance degradation. The faster the switching rates become,,
the more lead inductance can affect circuit performance.
Simulation of Measured Values
Both ground and VCC bounce for the 74F240 were simulated using
the inductive values measured. The results were similar to the
measured data of the 74F240. Figures 3 and 4. The simulation of
the 74F240 is shown in Figure 10. this shows the pad VCC, the pad
ground (VG) and the inputs (VIN) and output (VOUT) when all 8
buffers are switched simultaneously.
As circuits become faster, more care should be taken in packaging
and chip layout. In some cases like the 74F11, a better layout can
help remove potential problems but in most cases like the 74F240,
the noise is strictly a function of the package. Care should be taken
in integrated circuit packages to minimize lead lengths. Side mount
VCC and ground pins, smaller packages such as the surface
mounted SO, and High levels of board integration are fa few
possibilities which would help minimize lead lengths.
SUMMARY
A major contributor to noise in High-speed circuits is package lead
inductance. Integrated circuits are packaged with lead frame traces
and bonding wire. These leads act as inductors. Voltage generated
across these leads follow the law:
V L di
dt
GRAPHICAL OUTPUT
7.0E + 00
1.0E + 01
VOLTS/m AMPS
VCC
VOUT
2.0E + 00
0
VIN
–3.0E + 00
–1.0E + 01
NANOSECS 0
25.0
VG
50.0
SF01327
Figure 10.
1987 June
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